JP2010130213A - Image coding device and image coding method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image coding device and an image coding method, which can increase a substantial processing speed of variable length coding. <P>SOLUTION: The image coding device includes: a coefficient detection part 105 which detects non-zero coefficients where quantization coefficient values are not zero (0), zero run lengths showing the numbers of continuous zero coefficients where quantization coefficient values are zero, and non-zero coefficients which follow zero coefficients and where quantization coefficient values are not zero; an intermediate code generation part 105 which successively combines two or more every prescribed number of successively detected non-zero coefficients or zero run lengths and gives identifiers for discrimination between non-zero coefficients and zero run lengths per non-zero coefficient and zero run length to generate an intermediate code; and a plurality of coding parts 107 of which the number is equal to or larger than the prescribed number, wherein one non-zero coefficient and one zero run length are input to each coding part on the basis of non-zero coefficients or zero run lengths and the identifiers of the intermediate code and are subjected to variable length coding processing. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an image encoding device and an image encoding method.

  As a still image data compression method, there is a JPEG baseline method, and a Huffman code is used as a variable length coding method of the JPEG baseline method. Coefficients obtained by DCT transforming and quantizing image data divided into 8 × 8 pixel blocks consist of zero (0) and non-zero values. Huffman coding uses a combination of the number of zeros (zero run length) when the coefficient is zero (zero coefficient) and the nonzero coefficient that is a nonzero coefficient following the zero coefficient in order of increasing frequency. Assign a short code. Thereby, efficient encoding can be performed.

  In the conventional Huffman code, it is necessary to determine whether the DCT coefficient is zero or a non-zero coefficient for each block of all data in the DCT coefficient block at the time of encoding. For example, since the DCT coefficient block is an 8 × 8 block and has 64 data, when coding with a Huffman code, normally 64 clocks or more are required per block. Thus, for example, Patent Document 1 discloses a technique for shortening the processing time of the Huffman code.

JP 2003-333339 A

  Conventionally, in variable-length coding, consecutive zero coefficients are counted to calculate a zero run length, and one clock is required to count one zero coefficient. Therefore, in the technique of Patent Document 1, in order to suppress the number of processing clocks at the time of encoding, the zero run length and the non-zero coefficient are preceded by the variable length encoding that generates the variable length code from the zero run length and the non-zero coefficient. Are combined to generate one coefficient. In variable length coding, a variable length code is generated based on one generated coefficient. Therefore, in the variable length encoding of Patent Document 1, the number of processing clocks for calculating the zero run length becomes unnecessary, and the zero run length and the non-zero coefficient are directly input. Reduced.

  However, this method has an effect of reducing the number of processing clocks when the zero coefficients are long and continuous, that is, when the zero run length is large, but when the number of non-zero coefficients is large in one block, the number of processing clocks is reduced. Less effective. In addition, when all the quantized coefficients are non-zero coefficients, there is a problem that the effect of reducing the number of processing clocks is completely lost.

  Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a new and improved image capable of improving a substantial processing speed in variable-length coding. An encoding device and an image encoding method are provided.

  In order to solve the above problems, according to an aspect of the present invention, an orthogonal transform unit that orthogonally transforms image data to generate an orthogonal transform coefficient, a quantization unit that quantizes the orthogonal transform coefficient and generates a quantization coefficient, and A coefficient detection unit that detects a zero run length indicating the number of consecutive zero coefficients whose quantization coefficient value is zero (0), and a non-zero coefficient whose quantization coefficient value is not zero, following the zero coefficient; The sequentially detected non-zero coefficient or zero run length is sequentially combined every two or more predetermined numbers, and an identifier for identifying whether it is a non-zero coefficient or zero run length is provided for each non-zero coefficient and zero run length. An intermediate code generation unit that generates an intermediate code by adding the non-zero coefficient or zero run length of the intermediate code, and one non-zero coefficient and one zero run length based on the identifier, respectively It is input to process variable length coding, the image coding device having a plurality of encoding unit consisting of the predetermined number and above same number is provided.

  With this configuration, the orthogonal transform unit orthogonally transforms the image data to generate an orthogonal transform coefficient, and the quantization unit quantizes the orthogonal transform coefficient to generate a quantized coefficient. In addition, the coefficient detection unit calculates a zero run length indicating the number of consecutive zero coefficients whose quantization coefficient value is zero (0), and a non-zero coefficient whose quantization coefficient value is not zero following the zero coefficient. And the intermediate code generator sequentially combines the sequentially detected non-zero coefficients or zero run lengths every two or more predetermined numbers, and identifies an identifier that identifies whether the non-zero coefficient or zero run length is non-zero. An intermediate code is generated for each zero coefficient and zero run length. In addition, a plurality of encoding units having the same number or more as the predetermined number are inputted with one non-zero coefficient and one zero-run length based on the non-zero coefficient or zero run length of the intermediate code and the identifier, respectively. Variable-length encoding processing.

  The quantization unit, the coefficient detection unit, and the intermediate code generation unit may include a plurality of systems in parallel. With this configuration, image data can be processed in parallel in the quantization unit, the coefficient detection unit, and the intermediate code generation unit.

  In order to solve the above problem, according to another aspect of the present invention, an orthogonal transform unit orthogonally transforms image data to generate an orthogonal transform coefficient, and a quantization unit quantizes the orthogonal transform coefficient. And generating a quantized coefficient, and a coefficient detecting unit, a zero run length indicating a continuous number of zero coefficients whose quantized coefficient value is zero (0), and a quantized coefficient value following the zero coefficient Detecting a non-zero coefficient that is not zero, and an intermediate code generator sequentially combines the detected non-zero coefficient or zero run length every two or more predetermined numbers, and the non-zero coefficient and zero run length of A step of generating an intermediate code by assigning an identifier for identifying each for each non-zero coefficient and zero run length, and a plurality of encoding units having the same number or more as the predetermined number, And a non-zero coefficient or zero run length, based on the identifier, the image coding method and a step of processing variable-length coding are each one nonzero coefficient and one zero run length of the input is provided.

  With this configuration, image data is orthogonally transformed to generate orthogonal transform coefficients, and the orthogonal transform coefficients are quantized to generate quantized coefficients. Then, a zero run length indicating the number of consecutive zero coefficients whose quantization coefficient value is zero (0) and a non-zero coefficient whose quantization coefficient value is not zero following the zero coefficient are detected and sequentially detected. Non-zero coefficients or zero run lengths are sequentially combined every two or more predetermined numbers, and an identifier identifying whether the non-zero coefficient or zero run length is given to each non-zero coefficient or zero run length. Intermediate code is generated. Thereafter, one non-zero coefficient and one zero-run length are respectively input based on the non-zero coefficient or zero run length of the intermediate code and the identifier in a plurality of encoding units having the same number or more as the predetermined number. Thus, the variable length encoding process is performed.

  According to the present invention, a substantial processing speed can be improved in variable length coding.

  Exemplary embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

(First embodiment)
[Configuration of First Embodiment]
First, the image coding apparatus 100 according to the first embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating a configuration of an image encoding device 100 according to the present embodiment. The image encoding device 100 includes, for example, a two-dimensional DCT unit 101, a first buffer 102, a zigzag scan unit 103, a quantization unit 104, an intermediate code generation unit 105, a second buffer 106, and a variable length code. And the like.

The two-dimensional DCT unit 101 performs DCT transform (Discrete Cosine Transform) (orthogonal transform) on the input image data to generate DCT coefficients. Here, the input image data is, for example, data obtained by dividing the image signal output from the image sensor into blocks of 8 × 8 pixels. The two-dimensional DCT unit 101 performs DCT conversion on the image data, whereby an 8 × 8 DCT coefficient block is generated for each 8 × 8 pixel block.
The first buffer 102 stores the DCT coefficient data generated by the two-dimensional DCT unit 101 in units of DCT coefficient blocks.

  The zigzag scan unit 103 reads the DCT coefficient from the first buffer 102 and sends the read DCT coefficient to the quantization unit 104. The zigzag scanning unit 103 performs zigzag scanning for each DCT coefficient block when reading DCT coefficient data from the first buffer 102. FIG. 2 shows an 8 × 8 DCT coefficient block and is an explanatory diagram showing zigzag scanning in the DCT coefficient block. In the DCT coefficient block, the DCT coefficients generated by the two-dimensional DCT unit 101 are arranged in the order of 0 → 63 shown in FIG. As indicated by the arrows in FIG. 2, the zigzag scanning unit 103 reads the DCT coefficients by giving priority to the low frequency region of the DCT coefficient block, and gradually reads the DCT coefficients so as to become the high frequency region.

  The quantization unit 104 quantizes the DCT coefficient read by the zigzag scan by the zigzag scan unit 103 with a predetermined quantization value. The quantization unit 104 sends the quantized DCT coefficient to the intermediate code generation unit 105. At this time, the quantized DCT coefficient is output from the quantization unit 104 and then directly sent to the intermediate code generation unit 105 without being temporarily stored in a buffer or the like.

The intermediate code generation unit 105 generates an intermediate code based on the quantized DCT coefficient. The intermediate code includes a non-zero coefficient of DCT coefficient, a zero run length, and an identifier (ID). The intermediate code generation unit 105 sends the generated intermediate code to the second buffer 106.
The second buffer 106 stores the intermediate code generated by the intermediate code generation unit 105.

  The variable length encoding unit 107 reads the intermediate code from the second buffer 106 and determines the non-zero coefficient and the zero run length based on the ID indicating the non-zero coefficient and the zero run length of the intermediate code. Then, the variable length coding unit 107 generates a Huffman code based on the non-zero coefficient and the zero run length, and outputs the generated Huffman code. As will be described later, the variable length encoding unit 107 of the present embodiment has a plurality of encoding units corresponding to the number of intermediate codes included in one set (intermediate code set). For example, when there are two sets of intermediate codes included in one set, the variable length coding unit 107 has two coding units.

[Generate intermediate code]
Next, the generation of the intermediate code according to the present embodiment will be described.
The intermediate code is generated based on the quantized DCT coefficient. The quantized DCT coefficient consists of zero (0) and a non-zero value. Therefore, the intermediate code generation unit 105 is an example of a coefficient detection unit. First, for the DCT coefficient, the intermediate code generation unit 105 determines a non-zero coefficient that is a coefficient whose value is not zero and a coefficient whose value is zero (zero coefficient). When the intermediate code generation unit 105 determines that the DCT coefficient is a non-zero coefficient, the intermediate code generation unit 105 outputs the value. Further, the intermediate code generation unit 105 outputs an identifier (ID) indicating that the output value is a non-zero coefficient. In the present embodiment, the ID indicating a non-zero coefficient is “1”. The intermediate code generation unit 105 generates a set of intermediate codes by combining non-zero coefficient values and IDs. The ID is added to the MSB (most significant bit) of the intermediate code.

  On the other hand, when the intermediate code generation unit 105 determines that the DCT coefficient is a zero coefficient, the intermediate code generation unit 105 counts up the number of zero coefficients consecutive after the non-zero coefficient until the next non-zero coefficient is determined. The intermediate code generation unit 105 then outputs the counted number of zero coefficients as a zero run length. Further, the intermediate code generation unit 105 outputs an identifier (ID) indicating that the output value is zero run length. In the present embodiment, the ID indicating zero run length is “0”. The intermediate code generation unit 105 generates a set of intermediate codes by combining the zero run length value and the ID. The ID is added to the MSB (most significant bit) of the intermediate code.

[Placement of intermediate code]
Next, the arrangement of intermediate codes stored in the second buffer 106 will be described with reference to FIG. FIG. 3 is an explanatory diagram showing the arrangement of intermediate codes stored in the second buffer 106 of this embodiment.

  The second buffer 106 stores a plurality of time-sequential intermediate codes, one that precedes in time is arranged in the lower order and one that follows in time is arranged in the upper order. In the present embodiment, two sets of intermediate codes are defined as one set (intermediate code set). In FIG. 3, one set is represented by one line. “Coefficient data” in FIG. 3 indicates a non-zero coefficient value, and “zero run length” indicates a zero run length value. In the present embodiment, the value of the non-zero coefficient or the value of zero run length of the intermediate code is represented by 11 bits. The ID is represented by 1 bit. Therefore, in this embodiment, one set of intermediate codes is represented by 12 bits, and one intermediate code set including two sets of intermediate codes is represented by 24 bits. Therefore, since one DCT coefficient block is composed of 64 DCT coefficients, the buffer capacity of the intermediate code may be 768 bits (= 12 bits × 64) at the maximum.

  On the other hand, in Patent Document 1, one coefficient generated by combining a zero run length and a non-zero coefficient is represented by 15 bits including 4 bits representing a zero run length and 11 bits representing a non-zero coefficient. Accordingly, the buffer capacity of the coefficient is 960 bits (= 15 bits × 64) at the maximum. Therefore, the buffer capacity of the intermediate code of this embodiment may be smaller than that of Patent Document 1.

  An example of the intermediate code generated by the intermediate code generation unit 105 will be described with reference to FIG. FIG. 4 is an explanatory diagram showing a DCT coefficient after quantization (A) arranged in time series order and an intermediate code (B) generated from the DCT coefficient after quantization.

  As shown in FIG. 4B, the intermediate code includes an intermediate code value (a non-zero coefficient value or a zero run length value) and an ID. In FIG. 4B, the zero run length value is shown by shading. The intermediate code value can be identified as a non-zero coefficient value or a zero run length value by the ID added to the MSB of the intermediate code.

[Read intermediate code]
Next, reading of the intermediate code from the second buffer 106 by the variable length coding unit 107 will be described with reference to FIG. FIG. 5 is a block diagram showing the second buffer 106 and the variable length coding unit 107 that reads the intermediate code from the second buffer 106.

  The variable length encoding unit 107 includes a separation unit 110 as illustrated in FIG. The separation unit 110 separates the intermediate code (upper code) arranged in the higher order and the intermediate code (lower code) arranged in the lower order from the intermediate code set stored in the second buffer 106. The separation unit 110 includes a delay unit (DFF: D-type flip-flop) 111. The delay unit 111 receives an upper code of one preceding intermediate code set, and outputs the input upper code with a delay of one clock. Thus, when the delayed upper code is zero run length, it is possible to encode with the delayed upper code and lower code. As described above, the separation unit 110 simultaneously outputs the upper code, the lower code, and the upper code delayed by one clock.

[Encoding by variable length encoding unit 107]
Next, the encoding by the variable length encoding unit 107 will be described with reference to FIG. FIG. 6 is a block diagram showing the variable length coding unit 107 of this embodiment. Of the intermediate code set input to the second buffer 106, the lower code is C0, its ID is ID0, the higher code is C1, and its ID is ID1. The upper code delayed by one clock is suffixed with _d, for example, C1_d, and its ID is ID1_d.

  As shown in FIG. 6, the variable length encoding unit 107 includes selectors 121 and 122, a first encoding unit 131, a second encoding unit 132, and a connecting unit 141. When there are two sets of intermediate codes included in one set (intermediate code set), the variable length encoding unit 107 includes two code units of the variable length encoding unit 107. Therefore, the variable length encoding unit 107 Includes a first encoding unit 131 and a second encoding unit 132.

  “A” at the input of the first encoding unit 131 and the second encoding unit 132 indicates an input of a non-zero coefficient, and “Z” indicates an input of a zero run length. The first encoding unit 131 and the second encoding unit 132 output a Huffman code with reference to, for example, a two-dimensional Huffman table based on the non-zero coefficient and the zero run length. The Huffman coding in the first code unit 131 and the second code unit 132 is performed by calculating the number of zeros (zero run length) when the coefficient is zero (zero coefficient) and the nonzero non-zero coefficient following the zero coefficient. As a combination, codes with shorter code lengths are assigned in descending order of occurrence frequency. Thereby, efficient encoding can be performed.

  Based on the combination of IDs included in the intermediate code, the first encoding unit 131 switches between the selectors 121 and 122 in the previous stage and performs input processing of the input A and the input Z.

  As shown in FIG. 6, the non-zero coefficient input to the input A of the first encoding unit 131 is the upper code C1 or the lower code C0. The zero run length input to the input Z of the first encoding unit 131 is 0, the lower code C0, or the upper code C1_d one clock before. The non-zero coefficient input to the input A of the second encoding unit 132 is the upper code C1. The zero run length input to the input Z of the second encoding unit 132 has a value of zero. The second encoding unit 132 operates only when both the upper code C1 and the lower code C0 of the intermediate code set are non-zero coefficients, and outputs a Huffman code.

  The input A of the first code unit 131 and the second code unit 132 is a non-zero coefficient. When the non-zero coefficient exists in the low-order code C0 among the intermediate code sets composed of two sets of intermediate codes, the non-zero coefficient of the low-order code C0 is input to the input A of the first encoding unit 131. When the low-order code C0 has a non-zero coefficient and the high-order code C1 also has a non-zero coefficient, the non-zero coefficient of the low-order code C0 is input to the input A of the first code unit 131, and the non-zero coefficient of the high-order code C1 Is input to the input A of the second encoding unit 132. When the low-order code C0 has a zero run length and the high-order code C1 has a non-zero coefficient, the non-zero coefficient of the high-order code C1 is input to the input A of the first encoding unit 131.

  The input Z of the first encoding unit 131 is a zero run length, which is the zero run length immediately before the non-zero coefficient input to the input A of the first encoding unit 131. For example, when the input A of the first encoding unit 131 is a non-zero coefficient of the lower code C0 and the upper code C1_d delayed by one clock immediately before the lower code C0 has a zero run length, the zero run length of C1_d is the first 1 is input to the input Z of the encoding unit 131. Further, when the input A of the first encoding unit 131 is a non-zero coefficient of the lower code C0 and the higher code C1_d delayed by one clock immediately before the lower code C0 has a non-zero coefficient, the non-zero coefficient input to the input A The zero run length immediately before the zero coefficient is zero. Accordingly, zero run length value = 0 is input to the input Z of the first encoding unit 131. Further, when the input A of the first encoding unit 131 is a non-zero coefficient of the upper code C1, the zero run length of the lower code C0 is input to the input Z of the first encoding unit 131.

  The input Z of the second encoding unit 132 is a zero run length, which is the zero run length immediately before the non-zero coefficient input to the input A of the second encoding unit 132. The input to the inputs A and Z of the second encoding unit 132 is when both the upper code C1 and the lower code C0 of the intermediate code set are non-zero coefficients. Accordingly, since the zero run length immediately before the non-zero coefficient input to the input A of the second encoding unit 132 is 0, zero run length value = 0 is input to the input Z of the second encoding unit 132.

  The input switching in the selectors 121 and 122 is performed based on the ID included in the intermediate code. When the intermediate code set is input to the selectors 121 and 122, a combination of ID1 that is the ID of the higher code included in the intermediate code set, ID0 that is the ID of the lower code, and ID1_d that is the ID of the higher code before one clock To switch the input A and the input Z. FIG. 7 shows the relationship between ID combinations and the types of intermediate codes that are input. FIG. 7 is a table showing the relationship between ID combinations and the types of intermediate codes that are input.

  For example, if the combination is (ID1, ID0, ID1_d) = (0, 1, 0), the upper code C1 has a zero run length, the lower code C0 has a non-zero coefficient, and the upper code C1_d before one clock has a zero run length. It is. In the example shown in FIG. 4, for example, the coefficient is a part of 0 → 0 → 0 → 0 → 6 → 0 → 0 → 0 (FIG. 4A), and the intermediate code has 4 upper codes C1_d before one clock. The lower code C0 is 6 and the upper code C1 is 3 (FIG. 4B). At this time, according to FIG. 7, the lower code C0 is input as the input A to the first encoding unit 131, and the upper code C1_d one clock before is input as the input Z. The second encoding unit 132 is not used.

  For example, if the combination is (ID1, ID0, ID1_d) = (1, 0, 1), the upper code C1 is a non-zero coefficient, the lower code C0 is a zero run length, and the upper code C1_d before one clock is a non-zero coefficient. It is. In the example shown in FIG. 4, for example, the coefficient is a part of 2 → 0 → 1 (FIG. 4 (A)), and the intermediate code is 2 for the upper code C1_d, 1 for the lower code C0, and 1 for the upper code C1. Is 1 (FIG. 4B). At this time, according to FIG. 7, the first code unit 131 receives the upper code C1 as the input A and the lower code C0 as the input Z. The second encoding unit 132 is not used.

  For example, if the combination is (ID1, ID0, ID1_d) = (1, 1, 1), the upper code C1 is a non-zero coefficient, the lower code C0 is a non-zero coefficient, and the upper code C1_d before one clock is not Zero coefficient. In the example shown in FIG. 4, for example, the coefficient is a part of 1 → 1 → 2 (FIG. 4A), and the intermediate code is 1 for the upper code C1_d, 1 for the lower code C0, and 1 for the upper code C1. Is 2 (FIG. 4B). At this time, according to FIG. 7, the lower code C0 is input as the input A and the value 0 is input as the input Z to the first encoding unit 131. The second code unit 132 receives the upper code C1 as the input A and the value 0 as the input Z.

  Note that combinations not shown in FIG. 7 are combinations that do not appear. For example, when the upper code one clock before is zero run length (ID is 0), the lower code is never zero run length, and the lower code ID is never 0. This is because the intermediate code always becomes an intermediate code having a non-zero coefficient after the zero run length.

  The concatenation unit 141 combines the Huffman codes output from the first encoding unit 131 and the second encoding unit 132 in units of bits. For example, when the Huffman code output from the first encoding unit 131 is 11 bits and the Huffman code output from the second encoding unit 132 is 5 bits, the concatenating unit 141 outputs a 16-bit combined Huffman code. .

  According to the present embodiment, an intermediate code including non-zero coefficients of DCT coefficients, zero run lengths, and respective identifiers (IDs) is generated before the variable length coding. The variable length encoding unit 107 is provided with a plurality of encoding units, so that the processing time required for encoding can be shortened. For example, by combining two intermediate codes into one intermediate code set and providing two encoding units, the number of processing clocks required for encoding can be reduced to ½ or less.

  Furthermore, in the technique of Patent Document 1 described above, the coefficient after quantizing the image data is temporarily stored in a buffer, and then zigzag scan is performed to combine one zero run length and a non-zero coefficient. Coefficients are generated. However, this processing order has a problem that the number of processing clocks is increased as compared with the case where quantization is performed after zigzag scanning. On the other hand, according to this embodiment, since quantization is performed after zigzag scanning, there is no problem that the number of processing clocks increases as in Patent Document 1.

[First Modification of First Embodiment]
Next, a first modification of the image encoding device 100 according to the first embodiment of the present invention will be described.
In the image coding apparatus 100 described above, the case where two sets of intermediate codes are used as one intermediate code set has been described, but the present invention is not limited to such an example. For example, three sets of intermediate codes may be set as one set, such as three sets of intermediate codes as one intermediate code set.

  First, a case where three sets of intermediate codes are used as one intermediate code set will be described. In this case, the variable length coding unit 107 includes three coding units, that is, a first coding unit 231, a second coding unit 232, and a third coding unit 233, as shown in FIG. FIG. 8 is a block diagram illustrating a modification of the variable length coding unit 107 of the present embodiment.

  First, the intermediate code generation unit 105 generates an intermediate code including a non-zero coefficient value or a zero-run length value and an ID based on the non-zero coefficient and the zero run length. The generated intermediate code is sent to the variable length coding unit 107 via the second buffer 106. In this modification, three sets of intermediate codes are set as one set (intermediate code set).

  Next, encoding by the variable length encoding unit 107 will be described. Of the intermediate code set consisting of three intermediate codes input to the second buffer 106, C0, C1, and C2 are assigned to the lower-order intermediate codes, and the IDs are ID0, ID1, and ID2, respectively. The most significant code delayed by one clock is suffixed with _d, for example, C2_d, and its ID is ID2_d.

  As shown in FIG. 8, the variable length encoding unit 107 includes selectors 221, 222, 223, 224, a first encoding unit 231, a second encoding unit 232, a third encoding unit 233, and a connecting unit 241. When there are three intermediate codes included in one set (intermediate code set), the variable length encoding unit 107 includes three variable length encoding units 107. Therefore, the variable length encoding unit 107 Includes a first encoding unit 231, a second encoding unit 232, and a third encoding unit 233.

  The first encoding unit 231, the second encoding unit 232, and the third encoding unit 233 output a Huffman code with reference to, for example, a two-dimensional Huffman table based on the non-zero coefficient and the zero run length. The first encoder 231, the second encoder 232, and the third encoder 233 are switched by the preceding selectors 221, 222, 223, and 224 based on the combination of IDs included in the intermediate code, and input A and input Z Perform input processing.

  As shown in FIG. 8, the non-zero coefficient input to the input A of the first encoding unit 231 is the middle code C1 or the lower code C0. The zero run length input to the input Z of the first encoding unit 231 is 0, the lower code C0, or the upper code C2_d one clock before. The non-zero coefficient input to the input A of the second encoding unit 232 is the upper code C2 or the middle code C1. The zero run length input to the input Z of the second encoding unit 232 has a value of 0 or a middle code C1. The non-zero coefficient input to the input A of the third encoding unit 233 is the upper code C2. The zero run length input to the input Z of the third encoding unit 233 has a value of 0. The third encoding unit 233 operates only when all the intermediate codes C2, C1, and C0 of the intermediate code set are non-zero coefficients, and outputs a Huffman code.

  The input A of the first code unit 231, the second code unit 232, and the third code unit 233 is a non-zero coefficient. Among the intermediate code set composed of three sets of intermediate codes, the non-zero coefficients are the first code unit 231 → the second code unit 232 → the third code in the order of the lower non-zero coefficient to the higher non-zero coefficient. Assigned to the input A in the order of the unit 233. For example, the low-order code C0 has a zero run length, and when the intermediate code C1 has a non-zero coefficient, the non-zero coefficient of the intermediate code C1 is input to the input A of the first encoding unit 231. When the lower code C0 has a non-zero coefficient and the middle code C1 also has a non-zero coefficient, the non-zero coefficient of the lower code C0 is input to the input A of the first code unit 231 and the non-zero coefficient of the middle code C1 The zero coefficient is input to the input A of the second encoding unit 232. When all of the intermediate codes C2, C1, and C0 are non-zero coefficients, the non-zero coefficients of the intermediate code C1 are input to the input A of the first encoding unit 231 in order from the non-zero coefficient of the lower intermediate code. The non-zero coefficient of the upper code C2 is input to the input A of the second encoding unit 232, and the non-zero coefficient of the upper code C2 is input to the input A of the third encoding unit 233.

  The input Z of the first encoding unit 231 is a zero run length, and is the zero run length immediately before the non-zero coefficient input to the input A of the first encoding unit 231. For example, when the input A of the first encoding unit 231 is a non-zero coefficient of the lower code C0 and the upper code C2_d delayed by one clock immediately before the lower code C0 has a zero run length, the zero run length of C2_d is the first It is input to the input Z of the 1 encoding unit 231. Further, when the input A of the first encoding unit 231 is a non-zero coefficient of the lower code C0, and the higher code C2_d delayed by one clock immediately before the lower code C0 has a non-zero coefficient, the non-zero coefficient input to the input A The zero run length immediately before the zero coefficient is zero. Accordingly, zero run length value = 0 is input to the input Z of the first encoding unit 231. Further, when the input A of the first encoding unit 231 is a non-zero coefficient of the middle code C1, the zero run length of the lower code C0 is input to the input Z of the first encoding unit 231.

  The input Z of the second encoding unit 232 is a zero run length, which is the zero run length immediately before the non-zero coefficient input to the input A of the second encoding unit 232. For example, when the input A of the second encoding unit 232 is a non-zero coefficient of the upper code C2, and the intermediate code C1 immediately before the upper code C2 has a non-zero coefficient, the non-zero coefficient input to the input A The immediately preceding zero run length is zero. Accordingly, zero run length value = 0 is input to the input Z of the second encoding unit 232. Further, when the input A of the second encoding unit 232 is a non-zero coefficient of the intermediate code C1, zero run length value = 0 is input to the input Z of the second encoding unit 232.

  The input Z of the third encoding unit 233 is a zero run length, which is the zero run length immediately before the non-zero coefficient input to the input A of the third encoding unit 233. The input to the inputs A and Z of the third encoding unit 233 is when all of the upper code C2, the intermediate code C1, and the lower code C0 of the intermediate code set are non-zero coefficients. Accordingly, since the zero run length immediately before the non-zero coefficient input to the input A of the third encoding unit 233 is 0, zero run length value = 0 is input to the input Z of the third encoding unit 233.

  The input switching in the selectors 221, 222, 223, and 224 is performed based on the ID included in the intermediate code. When the intermediate code set is input to the selectors 221, 222, 223, and 224, ID2 that is the ID of the higher code included in the intermediate code set, ID1 that is the ID of the intermediate code, ID0 that is the ID of the lower code, The input A and the input Z are switched according to the combination of ID2_d which is the ID of the upper code one clock before. FIG. 9 shows the relationship between ID combinations and the types of intermediate codes that are input. FIG. 9 is a table showing the relationship between ID combinations and the types of intermediate codes that are input.

  For example, if the combination is (ID2, ID1, ID0, ID2_d) = (0, 1, 1, 0), the upper code C2 is a zero run length, the middle code C1 is a nonzero coefficient, and the lower code C0 is nonzero. The upper code C2_d one coefficient before the coefficient is zero run length. At this time, according to FIG. 9, the first code unit 231 receives the lower code C0 as the input A and the higher code C2_d one clock earlier as the input Z. The second code unit 232 receives the lower code C1 as the input A and the value 0 as the input Z. The third encoding unit 233 is not used.

  Also, for example, if the combination is (ID2, ID1, ID0, ID1_d) = (1, 0, 1, 0), the upper code C2 is a non-zero coefficient, the middle code C1 is zero run length, and the lower code C0 is The non-zero coefficient, the upper code C2_d one clock before is the zero run length. At this time, according to FIG. 9, the first code unit 231 receives the lower code C0 as the input A and the higher code C2_d one clock earlier as the input Z. The second code unit 232 receives the upper code C2 as the input A and the middle code C1 as the input Z. The third encoding unit 233 is not used.

  For example, if the combination is (ID2, ID1, ID0, ID1_d) = (1, 1, 0, 1), the upper code C2 is a non-zero coefficient, the middle code C1 is a non-zero coefficient, and the lower code C0 is a zero run. The upper code C2_d with a length of one clock is a non-zero coefficient. At this time, according to FIG. 9, the middle code C <b> 1 is input as the input A and the lower code C <b> 0 is input as the input Z to the first encoding unit 231. The second code unit 232 receives the upper code C2 as the input A and the lower code C0 as the input Z. The third encoding unit 233 is not used.

  The concatenating unit 241 combines the Huffman codes output from the first encoding unit 231, the second encoding unit 232, and the third encoding unit 233 in units of bits. For example, when the Huffman code output from the first encoding unit 231 is 11 bits, the Huffman code output from the second encoding unit 232 is 5 bits, and the Huffman code is not output from the third encoding unit 233, the connecting unit 241 outputs a 16-bit combined Huffman code.

  According to this modification, an intermediate code including a non-zero coefficient of a DCT coefficient, a zero run length, and each identifier (ID) is generated before the variable length coding. Then, by combining three intermediate codes to form one intermediate code set and providing three encoding units, the number of processing clocks required for encoding can be suppressed to 1/3 or less.

[Second Modification of First Embodiment]
The case of one intermediate code set including four or more sets of intermediate codes can be processed in the same manner as the case of the intermediate code set including two or three sets of intermediate codes described above. For example, when four sets of intermediate codes are used as one intermediate code set, the variable-length encoding unit 107 includes four encoding units, that is, a first encoding unit 331, a second encoding unit 332, as shown in FIG. A third encoding unit 333 and a fourth encoding unit 334 are included. FIG. 10 is a block diagram illustrating a modification of the variable length coding unit 107 that performs coding.

  First, the intermediate code generation unit 105 generates an intermediate code including a non-zero coefficient value or a zero-run length value and an ID based on the non-zero coefficient and the zero run length. The generated intermediate code is sent to the variable length coding unit 107 via the second buffer 106. In this modification, four sets of intermediate codes are set as one set (intermediate code set).

  Next, encoding by the variable length encoding unit 107 will be described. Of the intermediate code set consisting of four sets of intermediate codes input to the second buffer 106, C0, C1, C2, and C3 are assigned from the lower intermediate code, and the IDs are ID0, ID1, ID2, and ID3, respectively. . The most significant code delayed by one clock is suffixed with _d, for example, C3_d, and its ID is ID3_d.

  As shown in FIG. 10, the variable length encoding unit 107 includes selectors 321, 322, 323, 324, 325, 326, a first encoding unit 331, a second encoding unit 332, a third encoding unit 333, and a fourth encoding unit. 334 and a connecting portion 341. When there are four intermediate codes included in one set (intermediate code set), the variable-length encoding unit 107 includes four variable-length encoding units 107, so the variable-length encoding unit 107 Includes a first encoding unit 331, a second encoding unit 332, a third encoding unit 333, and a fourth encoding unit 334.

  The first code unit 331, the second code unit 332, the third code unit 333, and the fourth code unit 334 output a Huffman code with reference to, for example, a two-dimensional Huffman table based on the non-zero coefficient and the zero run length. The first encoding unit 331, the second encoding unit 332, the third encoding unit 333, and the fourth encoding unit 334 are based on the combination of IDs included in the intermediate code, and the selectors 321, 322, 323, 324, 325 of the previous stage. Switching is performed at 326 to perform input processing of input A and input Z.

  As shown in FIG. 10, the non-zero coefficient input to the input A of the first encoding unit 331 is the intermediate code C1 or C0. The zero run length input to the input Z of the first encoding unit 331 has a value of 0 and an intermediate code C0 or C3_d. The non-zero coefficient input to the input A of the second encoding unit 332 is the intermediate code C3, C2 or code C1. The zero run length input to the input Z of the second encoding unit 332 has a value of 0 and an intermediate code C2 or C1. The non-zero coefficient input to the input A of the third encoding unit 333 is the intermediate code C3 or C2. The zero run length input to the input Z of the third encoding unit 333 has a value of 0 or an intermediate code C2. The non-zero coefficient input to the input A of the fourth encoding unit 334 is the intermediate code C3. The zero run length input to the input Z of the fourth encoding unit 334 has a value of zero. The fourth encoding unit 334 operates only when all the intermediate codes C3, C2, C1, and C0 of the intermediate code set are non-zero coefficients, and outputs a Huffman code.

  The input A of the first code unit 331, the second code unit 332, the third code unit 333, and the fourth code unit 334 is a non-zero coefficient. Among the intermediate code set consisting of four sets of intermediate codes, the non-zero coefficients are the first code unit 331 → the second code unit 332 → the third code in the order of the low-order non-zero coefficient to the high-order non-zero coefficient. Assigned to input A in the order of part 333 → fourth encoding part 334.

  The input Z of the first encoding unit 331 is a zero run length, which is the zero run length immediately before the non-zero coefficient input to the input A of the first encoding unit 331. The input Z of the second encoding unit 332 is a zero run length, which is the zero run length immediately before the non-zero coefficient input to the input A of the second encoding unit 332. The input Z of the third encoding unit 333 is a zero run length, and is the zero run length immediately before the non-zero coefficient input to the input A of the third encoding unit 333. The input Z of the fourth code unit 334 is a zero run length, and is the zero run length immediately before the non-zero coefficient input to the input A of the fourth code unit 334.

  The input switching in the selectors 321, 322, 323, 324, 325, 326 is performed based on the ID included in the intermediate code. When the intermediate code set is input, the selectors 321, 322, 323, 324, 325, and 326 input the inputs A and Z according to the combination of ID3, ID2, ID1, ID0, and ID3_d included in the intermediate code set. Switch. FIG. 11 shows the relationship between the combination of IDs and the type of intermediate code to be input. FIG. 11 is a table showing the relationship between ID combinations and the types of intermediate codes that are input.

  For example, if the combination is (ID3, ID2, ID1, ID0, ID2_d) = (1, 0, 1, 1, 0), C3 is a non-zero coefficient, C2 is a zero-run length, C1 is a non-zero coefficient, C0 Is the non-zero coefficient, and C3_d one clock before is the zero run length. At this time, as shown in FIG. 11, C0 is input as the input A and C3_d one clock before is input as the input Z to the first encoding unit 331. The second encoding unit 332 receives C1 as input A and 0 as input Z. The third encoding unit 333 receives C3 as input A and C2 as input Z. The fourth code unit 334 is not used.

  The concatenating unit 341 combines the Huffman codes output from the first encoding unit 331, the second encoding unit 332, the third encoding unit 333, and the fourth encoding unit 334 in units of bits. For example, the Huffman code output from the first encoding unit 331 is 11 bits, the Huffman code output from the second encoding unit 332 is 5 bits, and the Huffman codes are output from the third encoding unit 333 and the fourth encoding unit 334. If not, the connecting unit 341 outputs a 16-bit combined Huffman code.

  According to this modification, an intermediate code including a non-zero coefficient of a DCT coefficient, a zero run length, and each identifier (ID) is generated before the variable length coding. Then, by combining four intermediate codes into one intermediate code set and providing four encoding units, the number of processing clocks required for encoding can be suppressed to 1/3 or less.

(Second Embodiment)
Next, an image encoding device 200 according to the second embodiment of the present invention will be described with reference to FIG. FIG. 12 is a block diagram illustrating a configuration of the image encoding device 200 according to the present embodiment.

  The image coding apparatus 200 includes, for example, a two-dimensional DCT unit 401, first buffers 402-1 and 402-2, zigzag scanning units 403-1 and 403-2, and quantization units 404-1 and 404-2. And intermediate code generators 405-1 and 405-2, second buffers 406-1 and 406-2, a variable length encoder 407, and the like.

  Unlike the image encoding device 100 according to the first embodiment, the image encoding device 200 according to the present embodiment includes each of the first buffers 402-1 and 402-2 to the second buffers 406-1 and 406-2. Functional blocks are composed of two systems in parallel. First buffers 402-1 and 402-2, zigzag scanning units 403-1 and 403-2, quantization units 404-1 and 404-2, intermediate code generation units 405-1 and 405-2, The configurations and operations of the two buffers 406-1 and 406-2 are the same as the first buffer 102, the zigzag scan unit 103, the quantization unit 104, the intermediate code generation unit 105, and the second buffer 106 of the first embodiment. Therefore, detailed description is omitted.

  The two-dimensional DCT unit 401 performs DCT conversion on the image data to generate an 8 × 8 DCT coefficient block for each 8 × 8 pixel block. The two-dimensional DCT unit 401 alternately outputs the generated DCT coefficient block to the first buffer 402-1 and the first buffer 402-2. FIG. 13 is a timing chart showing the operation of the image encoding device 200 of the present embodiment. “BLK” in FIG. 13 is an abbreviation for block.

  The two-dimensional DCT unit 401 performs, for example, double speed compared to the two-dimensional DCT unit 101 of the first embodiment. For example, the two-dimensional DCT unit 401 processes one DCT coefficient block within 32 clocks.

  The function blocks from the first buffer 402-1 and 402-2 to the second buffer 406-1 and 406-2 are configured in parallel in two systems, so that processing from zigzag scanning to intermediate code generation is performed. The 1 DCT coefficient block can be processed within 32 clocks.

  Then, the variable length coding unit 407 performs Huffman coding of the DCT coefficient based on the intermediate code. Since the variable length encoding unit 407 includes a plurality of encoding units as in the variable length encoding unit 107 of the first embodiment, the number of clocks required for encoding can be suppressed to ½ or less of the number of data. . Therefore, even if the processes from zigzag scanning to intermediate code generation are processed within 32 clocks for a substantial 1 DCT coefficient block, the variable length encoding unit 407 finishes encoding one DCT coefficient block, Coding of the DCT coefficient block can be started.

  Therefore, according to the second embodiment, not only encoding as in the first embodiment but also, for example, encoding of the entire JPEG can be performed at double speed. FIG. 14 is a timing chart showing the operation of the conventional image coding apparatus. Conventionally, the number of processing clocks for variable length encoding is the same as the number of processing clocks for two-dimensional DCT.

  If the processes from zigzag scanning to intermediate code generation are performed in three or more systems in parallel, and the variable length encoding unit 407 has three or more encoding units according to the number of systems, the entire JPEG Can be shortened.

  The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious that a person having ordinary knowledge in the technical field to which the present invention pertains can come up with various changes or modifications within the scope of the technical idea described in the claims. Of course, it is understood that these also belong to the technical scope of the present invention.

It is a block diagram which shows the structure of the image coding apparatus which concerns on the 1st Embodiment of this invention. It is explanatory drawing which shows the zigzag scan in an 8x8 DCT coefficient block and a DCT coefficient block. It is explanatory drawing which shows arrangement | positioning of the intermediate code stored in the 2nd buffer of the embodiment. It is explanatory drawing which shows the DCT coefficient (A) after the quantization arrange | positioned in time series order, and the intermediate code (B) produced | generated from the DCT coefficient after quantization. It is a block diagram which shows the variable length encoding part which reads an intermediate code from a 2nd buffer and a 2nd buffer. It is a block diagram which shows the variable length encoding part of the embodiment. It is a table | surface which shows the relationship between the combination of ID, and the kind of intermediate code input. It is a block diagram which shows the example of a change of the variable length encoding part of the embodiment. It is a table | surface which shows the relationship between the combination of ID, and the kind of intermediate code input. It is a block diagram which shows the example of a change of the variable-length encoding part which performs encoding. It is a table | surface which shows the relationship between the combination of ID, and the kind of intermediate code input. It is a block diagram which shows the structure of the image coding apparatus which concerns on the 2nd Embodiment of this invention. It is a timing chart which shows operation | movement of the image coding apparatus of the embodiment. It is a timing chart which shows operation | movement of the conventional image coding apparatus.

Explanation of symbols

100, 200 Image encoding device 101, 401 Two-dimensional DCT unit 102, 402-1, 402-2 First buffer 103, 403-1, 403-2 Zigzag scanning unit 104, 404-1, 404-2 Quantization unit 105, 405-1, 405-2 Intermediate code generation unit 106, 406-1, 406-2 Second buffer 107, 407 Variable length encoding unit 110 Separation unit 111 Delay unit 121, 122, 221, 222, 223, 224 , 321, 322, 323, 324, 325, 326 Selector 131, 231, 331 First code part 132, 232, 332 Second code part 141, 241, 341 Connection part 233, 333 Third code part 334 Fourth code part

Claims (3)

An orthogonal transform unit that orthogonally transforms image data and generates orthogonal transform coefficients;
A quantization unit that quantizes the orthogonal transform coefficient to generate a quantization coefficient;
Coefficient detection for detecting a zero run length indicating the number of consecutive zero coefficients whose quantization coefficient value is zero (0) and a non-zero coefficient whose quantization coefficient value is not zero following the zero coefficient. And
The non-zero coefficient or the zero run length sequentially detected is sequentially combined every two or more predetermined numbers, and an identifier for identifying whether the non-zero coefficient or the zero run length is the non-zero coefficient and the zero run length. An intermediate code generation unit that generates an intermediate code by giving each zero run length;
Based on the non-zero coefficient or the zero-run length of the intermediate code, and the identifier, one non-zero coefficient and one zero-run length are respectively input and variable length coding is performed, and the predetermined number An image encoding apparatus having a plurality of encoding units including the same number or more.   The image coding apparatus according to claim 1, wherein the quantization unit, the coefficient detection unit, and the intermediate code generation unit include a plurality of systems in parallel. An orthogonal transform unit orthogonally transforms the image data to generate an orthogonal transform coefficient;
A quantizing unit that quantizes the orthogonal transform coefficient to generate a quantized coefficient;
A coefficient detection unit includes a zero run length indicating the number of consecutive zero coefficients whose value of the quantization coefficient is zero (0), and a non-zero coefficient whose value of the quantization coefficient is not zero, which follows the zero coefficient. Detecting steps,
An intermediate code generation unit sequentially combines the detected non-zero coefficient or the zero-run length every two or more predetermined numbers, and an identifier for identifying whether the non-zero coefficient or the zero-run length is Providing an intermediate code for each non-zero coefficient and zero run length; and
A plurality of encoding units having the same number or more as the predetermined number are each configured to have one non-zero coefficient and one zero run based on the non-zero coefficient or the zero-run length of the intermediate code and the identifier, respectively. And a variable length encoding process by inputting a length.

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