JPH10163880A - Data decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To fast decide the code length of a code word when a data stream that is encoded with variable length is decoded by comparing the data held by a flip-flop with the minimum value of each code word held by a register group via a comparator group and encoding the code length of the code word equivalent to the data. SOLUTION: The data held by a flip-flop 14a and equivalent to 16 bits are inputted in sequence to an input terminal A of every comparator 18a from the head of the data in response to the number of bits which are compared with each other by every comparator 18a. At the same time, the outputs of a register group 16a, i.e., the minimum value of the code word length equal to 1 to 16 bits of the encoding/decoding table definition are inputted to an input terminal B of the comparator 18a and compared with each other. Then the result accordant with the code length of the code word equivalent to the data held by the flip-flop 14a is inputted to an encoder 20a. Thus, the code length is encoded into a code SIZE [3:0] of 4 bits and outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data decoder for decoding a variable-length coded data stream into original data before being coded.

[0002]

2. Description of the Related Art In a medium such as a facsimile or a telecommunication conference system which samples image data and converts it into digital information and transmits the digital information to a remote place, the demand for image quality is increasing year by year. For example, there is an image which is converted into a multi-tone image from a black-and-white binary image and further converted into a color image at present. Generally, the amount of information of image data is large, and particularly, the amount of information of multi-tone image data and color image data is enormous.

For this reason, for example, when transmitting or storing image data to a remote place, a data compression technique for compressing the image data and reducing the amount of information is used. For example, taking advantage of the fact that human vision is insensitive to high-frequency components, high-frequency components of image data, that is, portions that are difficult to be identified by human eyes are deleted, and image data is compressed to completely reduce image quality. The amount of information can be reduced without being dropped or with only a slight deterioration that cannot be recognized by human eyes.

One of such data compression techniques is, for example, the JPEG (Joint Photographic Experts Group) algorithm which is an international standard encoding method for color still images. As shown in FIG. 6, for example, JPEG
In the DCT (Discrete Cosine Transform) system, encoding and decoding of image data is performed, for example, by dividing original image data into blocks of 8 pixels in the horizontal direction by 8 pixels in the vertical direction, and a block of 64 pixels is used as a unit. It is performed as.

First, encoding of original image data is performed by an encoding device 22. In the encoding device 22, D
The discrete cosine transform is performed on the value of each pixel of each block by the CT circuit 24, quantized by the quantization circuit 26 based on the quantization table 28, and encoded by the entropy coding circuit 30. For example, the original image data that has been subjected to, for example, Huffman encoding and compression, and has been subjected to variable-length encoding, is transmitted through, for example, a transmission path.

On the contrary, decoding of the original image data is
This is performed by the decoding device 34. In the decoding device 34, the value of each pixel of the variable-length coded data stream block is Huffman-decoded by the entropy decoding circuit 36 using the same coding table 32, and is inversely quantized. The circuit 38 performs inverse quantization using the same quantization table 28, performs inverse discrete cosine transform and expands the inverse DCT circuit 40, and obtains decoded image data.

Here, a block of eight horizontal pixels (X = 0 to 7) × eight vertical pixels (Y = 0 to 7) = 64 pixels (P _XY ) is converted into 64 coefficients (S _XY )
Of the coefficient S ₀₀ is called a DC component, the remaining 63 coefficients S ₀₁ to S ₇₇ are called AC components. The DC component is
It shows the average value (DC component) of 64 pixels. In Huffman encoding / decoding, different encoding and decoding are performed on these DC and AC components.

In Huffman coding, for example, for coding AC coefficients, a zigzag scan is performed on quantized data, and a run length indicating the length of successive 0 coefficients is obtained.
, A group number (SSSS) of the AC coefficient is obtained from the value of the AC coefficient other than 0, and a code word having a code length of 1 to 16 bits is assigned according to the run length and the group number. Word, depending on the group number,
This is performed by adding 0-15 additional bits.

On the other hand, for example, a variable-length coded A
The decoding of the data stream of the C coefficient is performed by first determining the code length of the data corresponding to the first code word of the data stream because the code word corresponding to the individual AC coefficient is of variable length. This is performed by extracting a code word having the number of bits corresponding to the code length from the head, obtaining a run length and a group number according to the code word, and then calculating the number of additional bits from the group number.

As described above, in order to decode a variable-length-encoded data stream into original data before being encoded, it is necessary to first determine the code length of data corresponding to each codeword. is there. Similarly, the circuit, operation, and its problems for determining the code length of data corresponding to each code word in a variable-length-encoded data stream will be described using the JPEG color still image coding method as an example. I do.

Similarly, the Huffman coding / decoding method is used as the coding / decoding method, and the coding / decoding table is used for the luminance component of the AC coefficient recommended by JPEG shown in FIG. A Huffman table shall be used. The Huffman table in the illustrated example is one in which codewords having a code length of 1 to 16 bits are allocated according to the run length and the group number (SSSS).
These 16 kinds of code lengths are 4 bits code SIZ.
It is assumed that E [3: 0] is used.

FIG. 7 is a circuit diagram showing an example of a conventional data decoder. This data decoder 42
As described above, 1 to 1 represented by a 4-bit code
When decoding a data stream that has been variable-length coded into a code word having a code length of 6 bits, the code length of each code word is determined, and a shifter 44, a flip-flop 46, a memory 48, It comprises a device 50, a multiplexer group 52 (52a, 52b, 52c, 52d), a register group 54 (54a, 54b, 54c, 54d) and a control circuit 56.

In the illustrated data decoder 42, the variable-length coded data stream is input to a shifter 44, the output of the shifter 44 is input to a flip-flop 46, and the output of the flip-flop 46 is the output of the data stream. The data is input to an input terminal A of a comparator 50 that compares the data with the output of the memory 48. Therefore, the comparator 5
The output of the memory 48 is input to the input terminal B of 0, and the output of the comparator 50 is input to one input terminal of each of the multiplexer groups 52.

The output of the multiplexer group 52 is input to each register group 54 for temporarily holding a code representing the size of the code length of the code word.
Is input to the other input terminal of each of the multiplexer groups 52, the memory 48, and the shifter 44, and a 4-bit code SIZ representing the code length of the code word is input.
It is output as E [3: 0]. In addition, shifter 4
4 and the control terminal of the multiplexer group 52 are connected to the output of a control circuit 56 for controlling these operations.

In the data decoder 42, for example, 1101011100100 as a data stream
Assume that 001101111100101... Have been input. In the data decoder 42 in the illustrated example, first, the control circuit 56 sets the code length code SIZE [3] to 1
That is, SIZE [3: 0] is h'8 (hexadecimal), and the code length of the data corresponding to the first codeword of the data stream is 9 bits or more, or 9 bits Is detected.

Thus, the data stream is first
The shifter 44 shifts and outputs 9-bit data 110101110 from the first data,
The data output from the shifter 44 is held in a flip-flop 46, and the data held in the flip-flop 46 is input to an input terminal A of a comparator 50. on the other hand,
From the memory 48, the minimum value 111 of the 9-bit codeword is read.
110110 is output and similarly input to the input terminal B of the comparator 50.

In the comparator 50, the data 11010
1110 and the minimum value of the 9-bit codeword 111110
110 is compared. Here, data 110101
110 <minimum value of a code word having a length of 9 bits 11111011
Since it is 0, the comparison result of the comparator 50 is 0, that is, the code length of the data corresponding to the first code word is smaller than 9 bits, and the code SIZE [3] of the code length is 0. The result is held in the register 54a via the multiplexer 52a.

In the same manner, the code SIZE of the code length
[2] is set to 1, that is, SIZE [3: 0] is h′4
The data 11010 of 5 bits from the head of the data stream and the minimum value 1101 of the code word having a length of 5 bits
0 is compared. Here, since the data 11010 is the minimum value 11010 of the 5-bit codeword, the code length code SIZE [2] is 1, and the comparison result is
The data is held in the register 54b via the multiplexer 52b.

Next, the code SIZE [1] of the code length is set to 1, that is, SIZE [3: 0] is set to h'6,
7-bit data 110 from the beginning of the data stream
1011 and the minimum value 111100 of a 7-bit codeword
0 is compared. Here, data 1101011 <
Since the minimum value of the 7-bit code word is 1111000, the code length code SIZE [1] is 0, and the comparison result is stored in the register 54 via the multiplexer 52c.
c.

Finally, the code length code SIZE [0] is set to 1, that is, SIZE [3: 0] is set to h'5,
6-bit data 110 from the beginning of the data stream
101 is compared with the minimum value 1111010 of the 6-bit codeword. Here, since the data 110101 <the minimum value 111010 of the code word having a 6-bit length, the code SIZE [0] of the code length is 0, and the comparison result is as follows.
The data is held in the register 54d via the multiplexer 52d.

As described above, the code length code SIZE
By sequentially determining [3: 0] bit by bit, it is determined that the code length code SIZE [3: 0] of the data corresponding to the first codeword of the data stream is h′4, It is detected that the code length is 5 bits.

However, the conventional data decoder 42
, When decoding a variable-length-encoded data stream, it is necessary to determine the code of the code length of each codeword in steps of 1 bit, so that the processing speed is slow. was there. Further, when the encoding / decoding table to be used is determined in advance as in the above-described Huffman encoding / decoding, there are many useless circuits such as the multiplexer group 52, the register group 54, and the control circuit 56. There was also a problem that unnecessary processing was performed.

[0023]

SUMMARY OF THE INVENTION An object of the present invention is to determine the code length of a code word at a high speed when decoding a variable-length coded data stream in view of the above-mentioned problems in the prior art. Another object of the present invention is to provide a data decoder which can greatly reduce the circuit scale.

[0024]

In order to achieve the above object, the present invention provides a shifter for shifting variable-length coded data in accordance with the code length of a code word corresponding to the data, and a shifter for shifting the data. And a register group for holding the minimum value of each code word having a predetermined code length defined in the encoding / decoding table, and a data group for storing the data held in the flip-flop. And a comparator group for comparing the minimum value of each code word held in the register group with an encoder for encoding a code length of a code word corresponding to the data based on a comparison result of the comparator group. A data decoder is provided.

Also, the present invention provides a shifter for shifting variable-length encoded data in accordance with the code length of a code word corresponding to the data, a flip-flop for holding data output from the shifter, A comparator group for comparing the data held in the flip-flop with the minimum value of each code word having a predetermined code length defined in a predetermined encoding / decoding table; An encoder for encoding a code length of a code word corresponding to the data based on a result of the comparison is provided.

The present invention also provides a shifter for shifting variable-length encoded data in accordance with the code length of a code word corresponding to the data, a flip-flop for holding data output from the shifter, A register group for holding the maximum value of each code word having a predetermined code length defined in the encoding / decoding table; data held in the flip-flop; and respective code words held in the register group And a encoder that encodes the code length of a code word corresponding to the data based on the comparison result of the comparator group. Things.

Further, the present invention provides a shifter for shifting variable-length encoded data in accordance with the code length of a code word corresponding to the data, a flip-flop for holding data output from the shifter, A comparator group for comparing the data held in the flip-flop with the maximum value of each code word having a predetermined code length defined in a predetermined encoding / decoding table; An encoder for encoding a code length of a code word corresponding to the data based on a result of the comparison is provided.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a data decoder according to the present invention will be described in detail based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a circuit diagram of a data decoder according to an embodiment of the present invention. Illustrated data decoder 10a
Is used to determine the code length of each codeword when decoding a data stream that has been variable-length coded into codewords having a code length of 1 to 16 bits represented by a 4-bit code, for example. In the illustrated example, the shifter 12a, the flip-flop 14a, the register group 16a,
The comparator group 18a (CMP16a, CMP15a,..., C
MP1a) and the encoder 20a.

In the illustrated data decoder 10a,
The variable-length coded data stream is transmitted to the shifter 12a.
, And the output of the shifter 12a is input to the flip-flop 14a. The input terminal A of the comparator 18a,
The output of the flip-flop 14a and the output of the register 16a are input to B, and the output of the comparator 18a is input to the encoder 20a. The output of the encoder 20a is input to the shifter 12a and a 4-bit code SIZE representing the code length of the code word.
It is output as [3: 0].

Here, the shifter 12a shifts the data which has been variable-length coded to be a data stream in accordance with the code length of a code word corresponding to this data. In the illustrated example, data of 16 bits from the head of the shifted data stream is output. The flip-flop 14a holds data output from the shifter 12a, in the illustrated example, 16-bit data.

The register group 16a stores the minimum value of each code word having a predetermined code length defined in the encoding / decoding table, here, the minimum value of each code word having a code length of 1 to 16 bits. It holds the value. Before decoding data, the register group 16a holds the minimum value of each code word having a predetermined code length defined in an encoding / decoding table used for encoding / decoding. Is done.

The minimum value of each code word is stored in the register group 1
As a method of writing to the 6a, for example, a memory such as a RAM or a ROM for holding the minimum value of each code word having a predetermined code length defined in the encoding / decoding table is provided. , The minimum value of each codeword may be written,
Alternatively, the minimum value of each codeword may be directly written into the register group 16a by a program.

The comparator group 18a includes the flip-flop 14
The comparison is made between the data held in a and the minimum value of each code word having a predetermined code length defined in the encoding / decoding table, held in the register group 16a. In this embodiment, the data held in the flip-flop 14a is compared with the minimum value of each code word having a code length of 1 to 16 bits.
Is greater than or equal to the minimum value of each codeword.

The encoder 20a encodes the code length of the code word corresponding to the data held in the flip-flop 14a from the comparison result of the comparator group 18a.

As described above, the data decoder 10 in the illustrated example is used.
a, like a conventional data decoder, a multiplexer and a register for holding a code having a code length,
It is possible to omit a useless circuit, such as a control circuit for controlling the operation of the data decoder, which is necessary to determine the code of the code length step by step by one bit, and to reduce the circuit scale of the data decoder. Can be greatly reduced. Also,
Since complicated circuit control is not required, there is an advantage that circuit design is extremely easy.

The data decoder of the present invention basically has the above configuration. Next, the operation of the data decoder of the present invention will be described.

In the data decoder 10a, first, an input data stream is shifted by a shifter 12a, and data of 16 bits from the head is output. The 16-bit data output from the shifter 12a is held in the flip-flop 14a,
As for the 16-bit data held in the flip-flop 14a, the number of bits corresponding to the number of bits compared by each comparator 18a is input to the input terminal A of each comparator 18a from the beginning of the data.

On the other hand, the input terminal B of the comparator group 18a
The output of the register group 16a, that is,
The minimum value of each codeword having a code length of 1 to 16 bits defined in the decoding table is input. For example,
The comparator 18a (CMP5a) has a flip-flop 1
Of the 16 bits of data held in 4a, the data of 5 bits from the beginning of the data and the minimum value of a code word having a code length of 5 bits held in register 16a are input.

In the comparator group 18a, of the 16-bit data held in the flip-flop 14a, each of the comparators 18a (CMP 16
a, CMP15a,..., CMP1a) are compared with the data of the number of bits corresponding to the number of bits to be compared with the minimum value of the codeword having each code length held in each register 16a. The group 18a outputs a comparison result corresponding to the code length of the code word corresponding to the data held in the flip-flop 14a.

For example, when the code length of the code word corresponding to the data held in the flip-flop 14a is 5 bits, the comparator 18a (CMP 16
, CMP15a,..., CMP6a) outputs 0, and the comparator 18a (CMP5a, CMP4a,.
1 is output from P1a).

The comparison result output from the comparator group 18a is input to the encoder 20a, where the code length of the code word corresponding to the data held in the flip-flop 14a is a 4-bit code SIZE.
Encoded to [3: 0]. Code SIZE [3: 0] having a code length encoded by the encoder 20a
Is fed back to the shifter 12a, and the shifter 1
2a, the data stream is of code length code S
The shift is performed according to ISE [3: 0], and thereafter, the above-described operation is repeatedly performed.

As described above, the data decoder 10 in the illustrated example is used.
According to a, when decoding a variable-length-encoded data stream, instead of determining the code length code step by step by one bit as in the conventional data decoder 42, Since the data held in the flip-flop 14a and the minimum value of the code word having each code length held in each register 16a are simultaneously compared in parallel and the code of the code length is encoded, There is an advantage that the processing speed can be extremely increased by eliminating unnecessary processing.

The data decoder of the present invention basically operates as described above. As described above, the data decoder of the present invention has been described in detail. However, the present invention is not limited to the above embodiments, and various improvements and modifications may be made without departing from the spirit of the present invention. It is.

For example, the register group 16a is provided so as to correspond to all kinds of encoding / decoding tables, and an encoding / decoding table to be used is determined in advance. When the minimum value of each code word having each code length defined in the decoding table is known, that is, each minimum value of each code word having each code length is a fixed value. In that case, it is not always necessary.

The comparator group 18a may be designed so as to be compatible with all types of encoding / decoding tables. Similarly, the encoding / decoding tables to be used are determined in advance. In such a case, the size can be extremely reduced.

In the JPEG color still image coding system, it is determined in advance that the Huffman table of JPEG recommended AC coefficient luminance components shown in FIG. 2 is used as the coding / decoding table. The circuit configuration of a group of comparators used in the data decoder of the present invention will be described by taking a case as an example. Here, the minimum values of the codewords of the respective code lengths extracted from the Huffman table of the luminance component of the AC coefficient recommended by JPEG shown in FIG. 2 are shown.

[0048]

As shown in the minimum values of the code words of the respective code lengths, the code words having the code lengths of 1 bit, 13 bits, and 14 bits do not exist, and the minimum value of the code word having the code length of 2 bits. The value is 00. As for the minimum value of the code word having a code length other than this, 1 is continuously arranged on the upper bit side. From these facts, the circuit configuration of each comparator detects consecutive ones on the upper bit side,
In addition, it can be seen that it is sufficient to detect that the bit following this is equal to or larger than the minimum value of the code word.

FIGS. 3 (a) and 3 (b) show a conceptual diagram of a comparator and an example of a circuit configuration of a comparator group optimized according to the Huffman table of the luminance component of the AC coefficient. In the figure, for example, a comparator CMP1
6a compares data A [15: 0] with a minimum value B of a code word having a code length of 16 bits, and a comparison result T
Is output. In addition, CMP15a to CMP1
The same applies to a.

For example, the circuit configuration of the comparator CMP16a is such that the data A [15: 0] having a continuous value of 1 among the data A [15: 0] in order to detect the consecutive 1s on the upper bit side.
In order to take a logical product (AND) up to [15: 7] and detect that the following bit is greater than or equal to the minimum value of the codeword, the remaining data A [6: 0] The logical sum (OR) up to the data A [6: 1] is calculated, and the logical product of these detection results is calculated.

Thus, in the comparator CMP16a, when the data A [15: 0] is equal to or larger than the minimum value B of the code word having the code length of 16 bits, the comparison result T
And 1 is output, and conversely, data A [15:
0] is smaller than the minimum value B of the code word having the code length of 16 bits, 0 is output as the comparison result T. Similarly, for the comparators CMP15a to CMP1a, the data A is compared with the minimum value of the code word.
The comparison result T is output.

Although the Huffman table of the luminance component of the AC coefficient has been described as an example, for the color difference component of the AC coefficient, for example, similarly, the circuit of the comparator group 18a is simply simplified without using the register group 16a. Can be configured and
Alternatively, even when a DC coefficient or an encoding / decoding table other than the Huffman table is used, similarly, the circuit configuration of the comparator group 18a can be simplified without using the register group 16a. Needless to say.

As described above, in the data decoder of the present invention, when the encoding / decoding table to be used is determined in advance, as in Huffman encoding / decoding, etc.
The register group 16a for holding the minimum value of each code word having a predetermined code length defined in the encoding / decoding table becomes unnecessary, and the configuration of the comparator group 18a can be extremely reduced in size. Therefore, the circuit scale of the data decoder 10a can be significantly reduced.

In the above embodiment, the variable length coded data is compared with the minimum value of each code word having a predetermined code length defined in the coding / decoding table, and the variable length coded data is compared with the variable length coded data. Although the case where the code length of the code word corresponding to the long-coded data is obtained has been described as an example, conversely, each code having a predetermined code length defined in the coding / decoding table is described. Using the maximum value of the codeword, the code length of the codeword corresponding to the variable-length encoded data may be obtained.

FIG. 4 is a circuit diagram showing another embodiment of the data decoder of the present invention. Illustrated data decoder 10
b is the data decoder 10a shown in FIG.
Instead of the minimum value of the codeword of each code length, using the maximum value of the codeword of each code length, the code length of the codeword corresponding to the variable-length coded data is obtained. , A shifter 12b, a flip-flop 14b,
Register group 16b, comparator group 18b (CMP 15b, C
MP14b,..., CMP1b) and encoder 20b
Having.

Here, in the data decoder 10b, there is no code decoder having a code length of 16 bits larger than the maximum value of the code word, so that the variable-length coded data and the coding / decoding table Does not need to be compared with the maximum value of a code word having a code length of 16 bits as defined in.

Therefore, in the data decoder 10b in the illustrated example, the shifter 12b outputs 15-bit data from the head of the data stream after being shifted according to the code length of the data, and the flip-flop 14b
Holds the 15-bit data output from the shifter 12b. The register group 16b stores the maximum value of each code word having a predetermined code length defined in the encoding / decoding table. In this embodiment, each of the register groups 16b has a code length of 1 to 15 bits. Holds the maximum value of the codeword.

The comparator group 18b stores the data held in the flip-flop 14b and the codewords held in the register group 16b and having the predetermined code length defined in the encoding / decoding table. Compare with the maximum value.
In this embodiment, the data held in the flip-flop 14b is compared with the maximum value of each code word having a code length of 1 to 15 bits, and the data held in the flip-flop 14b is Is greater than or equal to the maximum value.

As described above, in the data decoder 10b, the comparison between the variable-length coded data and the maximum value of the code word having the code length of 16 bits defined in the coding / decoding table is performed. Since it is unnecessary, the data decoder 10a shown in FIG. 1 further does not need a circuit for one bit for the 16th bit data of the flip-flop 14b, the register 16, and the comparator 18b.
There is an advantage that the circuit scale of the data decoder can be further reduced.

The operation of the data decoder 10b is to compare the variable-length coded data with the minimum value of the code word having each code length, instead of comparing the maximum value of the code word having each code length. The operation is the same as that of the data decoder 10a shown in FIG. That is, first, the data stream is shifted by the shifter 12b according to the code length of the codeword corresponding to the data,
The 15-bit data from the top is held in the flip-flop 14b.

Subsequently, in each of the comparators CMP15b, CMP14b,..., CMP1b of the comparator group 18b, of the 15-bit data held in the flip-flop 14b, each of the comparators CM starts from the head of the data.
P15b, CMP14b,..., CMP1b are compared with the data of the number of bits corresponding to the number of bits to be compared with the maximum value of the codeword having the code length held in each register 16b, and the comparison result Is output.

For example, if the code length of the code word corresponding to the data held in the flip-flop 14b is 5 bits, the comparators CMP15b and CMP14
,..., CMP5b output 0, and the comparator CMP
4b, CMP3b,..., CMP1b output 1. The comparison result is encoded by the encoder 20b, the data stream is shifted by the shifter 12b according to the code length of the codeword corresponding to the data, and thereafter, the above-described operation is repeated.

The data decoder 10 shown in FIG.
As in the case of a, the encoding / decoding table to be used is determined in advance in the data decoder 10b, and the respective code lengths defined in the encoding / decoding table are used. If the maximum value of each of the codewords having the following is known, the register group 16b can be omitted, and the comparator group 18b can be optimized and downsized.

Similarly, in the JPEG color still image coding method, a case where a Huffman table of luminance components of AC coefficients recommended by JPEG shown in FIG. 2 is used as an encoding / decoding table will be described as an example. The circuit configuration of the comparator group 18b used in the data decoder 10b will be described. Here, the maximum value of the codeword of each code length extracted from the Huffman table of the luminance component of the AC coefficient recommended by JPEG shown in FIG. 2 is shown.

[0066]

As indicated by the maximum values of the code words of the respective code lengths, the code words of the code lengths of 1 bit, 13 bits and 14 bits do not exist, and the maximum of the code words of the code length of 2 bits is not present. The value is 01. As for the maximum value of the codeword having a code length other than this, 1 is continuously arranged on the upper bit side. From these facts, the circuit configuration of each comparator detects consecutive ones on the upper bit side,
In addition, it can be seen that it is sufficient to detect that the following bit is larger than the maximum value of the code word.

FIGS. 5A and 5B show conceptual diagrams of the comparator and an example of a circuit configuration of the comparator group optimized according to the Huffman table of the luminance component of the AC coefficient. In the figure, for example, a comparator CMP1
5b compares the data A [15: 1] with the maximum value B of the code word having a code length of 15 bits, and the comparison result T
Is output. In addition, CMP14b to CMP1
The same applies to b.

For example, the circuit configuration of the comparator CMP15b is such that the data A [15: 1] having a continuous value of 1 among the data A [15: 1] in order to detect consecutive 1s on the upper bit side.
The remaining data A [6:] are ANDed up to [15: 7] to detect that the following bit is greater than the maximum value of the 15-bit codeword.
1] are all 0, the data A
All logical sums (OR) of [6: 1] are calculated, and the logical product of these detection results is calculated.

Thus, in the comparator CMP15b, when the data A [15: 1] is larger than the maximum value B of the code word having the code length of 15 bits, 1 is output as the comparison result T, Conversely, data A [1
5: 1] is equal to or smaller than the maximum value B of the code word having the code length of 15 bits, 0 is output as the comparison result T. Similarly, for the comparators CMP14b to CMP1b, the data A is compared with the maximum value of the code word.
The comparison result T is output.

As described above, in the data decoder of the present invention, the same applies to the case where the code length of the data is obtained using the minimum value of the codeword and the case where the maximum value is used.
The coding / decoding table to be used is not limited to the Huffman table of the luminance components of the coefficients, and the maximum value of the codeword of each code length in the coding / decoding table is known. For example, the register group 16b can be omitted, and the comparator group 18b can be optimized and downsized.

[0072]

As described above in detail, according to the data decoder of the present invention, the data corresponding to the variable length coded code word and the minimum value of the code word having each code length or Since the maximum value is simultaneously compared in parallel to encode a code having a code length, useless processing can be omitted, and the processing speed can be extremely increased. Further, according to the data decoder of the present invention, in the conventional data decoder, it is possible to omit a useless circuit that is necessary to determine the code length code step by step by one bit. Furthermore, since the configuration of the comparator group can be extremely reduced in accordance with the encoding / decoding table to be used, the circuit scale of the data decoder can be significantly reduced, and the circuit design can be extremely reduced. There is an advantage that it becomes easy.

[Brief description of the drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a data decoder according to the present invention.

FIG. 2 is a Huffman table of luminance components of AC coefficients recommended by JPEG (interface: published by CQ Publisher,
(December 1991, p. 170).

FIGS. 3A and 3B are circuit diagrams of an embodiment of a comparator group optimized according to a conceptual diagram of a comparator and a Huffman table of luminance components of AC coefficients, respectively.

FIG. 4 is a configuration circuit diagram of another embodiment of the data decoder of the present invention.

5A and 5B are circuit diagrams of another embodiment of a comparator group optimized according to a conceptual diagram of a comparator and a Huffman table of luminance components of AC coefficients, respectively.

FIG. 6 is a conceptual diagram of encoding / decoding in the JPEG DCT method.

FIG. 7 is a configuration circuit diagram of an example of a conventional data decoder.

[Explanation of symbols]

10a, 10b, 42 Data decoder 12a, 12b, 44 Shifter 14a, 14b, 46 Flip-flop 16a, 16b, 54 (54a, 54b, 54c, 54
d) Register group 18a (CMP16a, CMP15a,..., CMP1)
a), 18b (CMP15b, CMP14b, ..., CM
P1b) Comparator group 20a, 20b Encoder 22 Encoding device 24 DCT circuit 26 Quantization circuit 28 Quantization table 30 Entropy encoding circuit 32 Encoding table 34 Decoding device 36 Entropy decoding circuit 38 Inverse quantization circuit 40 Inverse DCT Circuit 48 Memory 50 Comparator 52 (52a, 52b, 52c, 52d) Multiplexer group 56 Control circuit

Claims (4)

[Claims] 1. A shifter for shifting variable-length encoded data according to the code length of a code word corresponding to the data, a flip-flop for holding data output from the shifter, and encoding / decoding. Registers holding the minimum value of each code word having a predetermined code length defined in the conversion table, data held in the flip-flop and minimum value of each code word held in the register group, And a encoder that encodes the code length of a code word corresponding to the data based on the comparison result of the comparator group. 2. A shifter for shifting variable-length encoded data in accordance with the code length of a code word corresponding to the data, a flip-flop holding data output from the shifter, A comparator group for comparing the held data with the minimum value of each codeword having a predetermined code length defined in a predetermined encoding / decoding table, and a comparison result of the comparator group, An encoder for encoding a code length of a code word corresponding to the data. 3. A shifter for shifting variable-length encoded data in accordance with a code length of a code word corresponding to the data, a flip-flop for holding data output from the shifter, and encoding / decoding. A register group that holds the maximum value of each code word having a predetermined code length defined in the conversion table, the data held in the flip-flop and the maximum value of each code word held in the register group. And a encoder that encodes the code length of a code word corresponding to the data based on the comparison result of the comparator group. 4. A shifter for shifting variable-length encoded data according to a code length of a code word corresponding to the data, a flip-flop for holding data output from the shifter, A comparator group for comparing the held data with the maximum value of each code word having a predetermined code length defined in a predetermined encoding / decoding table, and a comparison result of the comparator group, An encoder for encoding a code length of a code word corresponding to the data.