JP2007104194A - Decoding system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To speed up decoding processing in a decoding system while decoding a code string encoded by a canocical Huffman coding. <P>SOLUTION: The decoding system is provided with a code length specification part that executes code length specification processing for specifying a code length of the decoding target included in a processing unit. The system is composed so as to instruct the start of the code length specification processing regarding the next-time processing unit to the code length specification, after the code length specification processing regarding a current processing unit is finished, and before the decoding processing is finished. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a decoding system that outputs a symbol string in which a plurality of symbols are arranged by repeatedly decoding a code string encoded by the canonical Huffman method for each processing unit of a predetermined code length.

  Canonical Huffman coding is known as one of the data compression methods. In this encoding, after normalizing the appearance frequency information, the bit length of the codeword obtained by the Huffman code is directly calculated. This eliminates the need to pass the appearance frequency information to the decoding side, thereby reducing the memory consumption on the decoding side. For example, Patent Document 1 discloses a Huffman decoder that increases the processing speed without increasing the circuit scale. The Huffman decoder selectively outputs cueing data of the next Huffman code from among the prediction values held in advance according to the code length of the additional bits of the output data obtained by decoding.

JP 2004-179752 A

  However, in the Huffman decoder of Patent Document 1, although the code length of the next Huffman code can be determined simultaneously with the generation of the current decoded data, the next Huffman code is generated during the generation of the decoded data. The code length cannot be determined. In addition, a buffer for holding a plurality of prediction values is required in the Huffman decoder, and the size of the buffer changes according to the number of prediction values, which can be a factor in increasing the scale of the circuit.

  The present invention has been made in view of such circumstances, and an object thereof is to speed up the decoding process by starting the decoding process of the next processing unit even during the decoding process of the current processing unit. That is.

  Another object of the present invention is to reduce the size of the circuit by reducing a buffer for holding a plurality of prediction values in the Huffman decoder.

  In order to solve such a problem, the first invention repeats the decoding process for each processing unit of a predetermined code length that constitutes a part of the code string with a code string encoded by the canonical Huffman method as a decoding target. By doing so, a decoding system is provided that outputs a symbol string in which a plurality of symbols are arranged. This decoding system compares a base table in which a head code is described in association with each of a plurality of different code lengths, a head code for each code length described in the base table, and a head code in a processing unit. A code length specifying unit that performs a code length specifying process that specifies a code length of a decoding target included in the processing unit, and a decoding process that decodes the decoding target whose code length is specified by the code length specifying unit The decoding processing unit that outputs a symbol corresponding to the decoding target and the start of the code length specifying process for the next processing unit after the end of the code length specifying process for the current processing unit and before the end of the decoding process And a control unit that instructs the code length specifying unit.

  In the second invention, a code string encoded by the canonical Huffman method is a decoding target, and a plurality of symbols are obtained by repeatedly performing decoding processing for each processing unit of a predetermined code length constituting a part of the code string. Provided is a decoding system that outputs a sequence of arranged symbols. This decoding system refers to a determination table in which a code is described in association with each specific symbol set in advance based on the arrangement characteristics of the symbol sequence, and includes the code of the specific symbol in the current processing unit If it is determined that, a specific symbol corresponding to the code is output as a decoding result, and a main decoder that selectively designates a processing subject regarding a processing unit after this time, and a main decoder are provided in parallel, A plurality of processing units to be processed by the self are processed by the pipeline, and symbols obtained by decoding the processing units to be processed by the self are selectively selected as decoding results according to the designation from the main decoder. The first sub-decoder for output and the main decoder are provided in parallel and designated from the main decoder. Correspondingly, a second sub-decoder for selectively outputting the decoded result obtained symbol by decoding processing unit itself to be processed.

  In the second invention, the first sub-decoder includes a base table in which a head code is described in association with each of a plurality of different code lengths, a head code for each code length described in the base table, A code length specifying unit that performs a code length specifying process for specifying a code length of a decoding target included in the processing unit by comparing the head code of the processing unit, and a decoding target whose code length is specified by the code length specifying unit The decoding processing unit that outputs a symbol corresponding to the decoding target and the code length specifying process for the current processing unit and the end of the decoding process It is preferable to include a control unit that instructs the code length specifying unit to start the code length specifying process related to the processing unit.

  In the second invention, the code string includes a plurality of types of character symbols and a run symbol indicating the number of consecutive same type of character symbols, and the main decoder selects a character symbol immediately before the run symbol. The first sub-decoder decodes the current processing unit when the current processing unit does not include the specific symbol and the previous processing unit does not include the specific symbol. The second sub-decoder does not include the specific symbol in the current processing unit and includes the specific symbol in the previous processing unit. If it is, it is preferable to output a run symbol obtained by decoding the current processing unit as a decoding result.

  In the second invention, when the main decoder determines that the code of the specific symbol is included in a predetermined order in the continuous processing unit including the current time, the main decoder outputs the specific symbol corresponding to the code as a decoding result. In addition, it is preferable to selectively specify the processing subject relating to the processing unit from this time onward.

  According to the first aspect of the present invention, the code length specifying unit that performs the code length specifying process for specifying the code length of the decoding target included in the processing unit is provided. Then, after the end of the code length specifying process for the current processing unit and before the end of the decoding process, the code length specifying unit is instructed to start the code length specifying process for the next processing unit. As a result, a pipeline process of starting the decoding process of the next processing unit is executed in the middle of the decoding process of the current processing unit. Such pipeline processing relies on the characteristics peculiar to canonical Huffman coding, whereby the speed of decoding processing can be increased. Further, since there is no need for a buffer for holding a plurality of predicted values in the Huffman decoder, it is possible to prevent the circuit from being scaled up.

  According to the second aspect of the invention, the main decoder is provided that refers to the determination table in which the code is described in association with each of the specific symbols set in advance based on the arrangement characteristics of the symbol string. The main decoder selectively designates a sub-decoder related to the subsequent processing units depending on whether or not the code of the specific symbol is included in the current processing unit. As a result, the decoding process of the next processing unit can be started in the middle of the decoding process of the current processing unit even in the case of the symbol string based on the arrangement characteristics of the symbol sequence, so that the decoding process can be speeded up. .

(First embodiment)
FIG. 1 is a configuration diagram of a decoding system in the present embodiment. This decoding system uses a code string encoded by the canonical Huffman method as a decoding target, and outputs a symbol string in which a plurality of symbols are arranged by repeatedly performing the decoding process for each processing unit. The processing unit is a partial code string that constitutes a part of the code string, and has a predetermined code length. The decoding system includes a buffer 1, a shifter 2, and an arithmetic decoder 3.

  The buffer 1 stores a code string encoded by the canonical Huffman method. The shifter 2 bit-shifts a part of the code string stored in the buffer 1 in accordance with an instruction from the control unit 7 which is a part of the arithmetic decoder 3, and uses the arithmetic decoder 3 (specifically, the code length) as an input code. Input to the specifying unit 5 and the table address generating unit 6c) is performed. The arithmetic decoder 3 includes a base table management unit 4, a code length specifying unit 5, a decoding processing unit 6, and a control unit 7.

  The base table management unit 4 manages a base table in which a head code is described in association with each of a plurality of different code lengths. The code length specifying unit 5 compares the head code for each code length described in the base table management unit 4 with the head code of the processing unit, thereby specifying the code length of the decoding target included in the processing unit. A long identification process is performed. The decoding processing unit 6 outputs a symbol corresponding to the decoding target by performing a decoding process for decoding the decoding target whose code length is specified by the code length specifying unit 5.

  The decoding processing unit 6 includes an offset table management unit 6a, a symbol table management unit 6b, and an address generation unit 6c. The offset table management unit 6a manages an offset table in which an offset value is described in association with each of a plurality of different code lengths. The symbol table management unit 6b manages a symbol table in which symbols are described in association with each address. The address generation unit 6c outputs a symbol corresponding to a part of the code sequence based on a part of the code sequence to be decoded input from the buffer 1 and the offset value input from the offset table management unit 6a. .

  Note that these tables (base table, offset table, symbol table) are generated as needed during decoding based on the code length information generated during encoding. This code length information is composed of an input (encoded) symbol and a code length corresponding to the symbol. Specifically, the value “0” (for example, code length “1”: code “0”, code length “2”: code “00”) is assigned to the symbol indicating the minimum code length. Thereafter, a table (direct table) is generated by assigning consecutive codes in order of increasing code length. Each table is generated by normalizing this table. Each table is not limited to a separate configuration as in the present embodiment, and each table may be logically configured, and is stored in the physically same buffer (not shown). May be.

  The control unit 7 instructs the code length specifying unit 5 to start the code length specifying process for the next processing unit after the end of the code length specifying process for the current processing unit and before the end of the decoding process. Specifically, when the control unit 7 detects the end of the code length specifying process from the code length specifying unit 5 together with the code length of the current processing unit, the next decoding process for the shifter 2 based on the code length The code length specifying unit 5 is instructed to start the code length specifying process for the next processing unit. As a result, pipeline processing that starts processing of the next processing unit in the middle of processing of a certain processing unit is executed instead of sequential processing of starting processing of the next processing unit upon completion of processing of a certain processing unit. become. The reason why such pipeline processing is possible depends on the characteristics peculiar to canonical Huffman coding, which will be described later.

  FIG. 2 is a configuration diagram of a table provided in the arithmetic decoder 3. FIG. 2A is a base table provided in the base table management unit 4, and FIG. 2B is an offset table provided in the offset table management unit 6a. FIG. 7C relates to a symbol table provided in the symbol table management unit 6b. As an example, a case where the code “1001...” Is decoded into one symbol will be described using these tables. The code string decoding process (so-called arithmetic decoding) in the present embodiment includes a shift process, a code length specifying process, and a table access process.

(Shift processing)
The shift process is a process for inputting a part of the code string as an input code. Specifically, the control unit 7 instructs the shifter 2 to perform a bit shift process on the decoding target code string stored in the buffer 1 by a predetermined number of bits. The shifter 2 performs bit shift of the buffer 1 in response to this instruction. The shifted data is input as an input code to the code length specifying unit 5 and the address generating unit 6c.

  In this case, the shifter 2 shifts the buffer 1 so that the 4-bit code string “1001” stored in the buffer 1 is read into the code length specifying unit 5 as an input code. The bit length read here is set in advance in consideration of the maximum code length of the input code, that is, the maximum code length corresponding to the symbol output by one decoding. This is because the code length of the code input to the input operation decoder 3 is initially unknown, and the code length specifying unit 5 must grasp the entire bit within the range that can be decoded with the symbol.

(Code length identification process)
The code length specifying process is a process of specifying, based on the code length, where an input code is from another code string (that is, a code string used in the next decoding process). Specifically, the code length of the input code to be decoded this time is specified using the base table of the base table management unit 4 (FIG. 2A). In this case, the code length specifying unit 5 reads the current input code “1001” from the buffer 1 and specifies the code length of the input code “1001”. In order to specify the code length, a comparison between the head code “1001” of the input code and the head code stored in the base table is used. The reason why the code length can be specified only by referring to the base table is that a code string by canonical Huffman coding has the following principle.

(1) The code length is the same as that determined by the normal Huffman algorithm.
(2) The value of the short code string is smaller than the value of the long code string.
(3) If the code lengths are the same, the values are continuous.

If the value of each upper bit of the input code is larger than the value of the head code corresponding to this code length (number of bits), it is guaranteed that the code length of this input code is greater than or equal to the code length corresponding to this head code. Is done. In this case, the comparison between the two is as follows.

10 (first two bits of input code)> 00 (first code of code length 2)
100 (first two bits of input code)> 010 (first code of code length 3)
1001 (first two bits of input code) <1110 (first code of code length 4)

  According to the above process, since the code length is “3” or more and less than “4”, the code length is specified as “3”. At the same time as this specification, it is determined that “1” of the lower 1 bit of the input code is used in the next decoding process. The identified code length “3” is input to the decoding processing unit 6 (offset table management unit 6a) and the control unit 7. The code length specifying unit 5 ends the necessary processing for the input code by outputting the code length of the input code. Therefore, it should be noted that a new (next) input code can be accepted at this point.

(Table access processing)
The table access process is a process for outputting a symbol that mainly corresponds to the input code with the code length specified by the above-described encoding specifying process. First, the offset table management unit 6a specifies an offset address corresponding to the code length input from the code length specifying unit 5 with reference to the offset table (FIG. 2B). In this case, since the input code length is “3”, “1” is specified as the corresponding offset address. The specified offset address “1” is input to the table address generation unit 6 c together with the code length “3”.

  Next, the table address generator 6c generates a symbol table (FIG. 2 (c) based on the input code, the offset address and code length input from the offset table manager 6a, and the head code stored in the base table. )) Is calculated. Specifically, the difference (displacement from the offset address) between the input code and the head code corresponding to the code length is calculated, and the symbol table address is calculated by adding the difference and the offset address. . In this case, a value “2” that is a difference between the input code “100” and the head code “010” corresponding to the code length “3” is calculated, and the difference value “2” and the offset address “1” are calculated. Is added to calculate address “3”. The calculated address “3” is input to the symbol table management unit 6b.

  Then, the symbol table management unit 6b refers to the symbol table and specifies / outputs the symbol of the code to be decoded this time. In this case, since the input address is “3”, the corresponding symbol “C” is specified. The identified symbol “C” is output as a symbol corresponding to the current input code “100”.

  In parallel with the above-described table access processing relating to the current processing unit, shift processing relating to the next processing unit is performed. Specifically, based on the input of the code length from the code length specifying unit 5, the control unit 7 again uses the lower bits that have not been decoded in the current processing unit as the code of the next processing unit, The data is output to the length specifying unit 5 and the decoding processing unit 6. In this case, the code length “3” is input to the control unit 7, and the code 4 bits including the lower 1 bit “1” input in the current shift processing is the code length from the buffer 1 as the code of the next processing unit. The data is newly input to the specifying unit 5 and the decoding processing unit 6.

  The code including the lower bit “1” is newly input from the buffer 1 to the code length specifying unit 5 and the decoding processing unit 6 as the code of the next processing unit. Instead, this code is stored in advance in the decoding system. In addition, the decoding process may be performed by merging this with the next code. For example, when the lower bit “1” is held in the code length specifying unit 5 and the decoding processing unit 6 as it is, the 3 bits following the lower bit “1” from the buffer 1 are converted into the code length specifying unit 5 and the decoding processing unit. Entering 6 is sufficient.

  FIG. 3 is an explanatory diagram of the decoding process. This explanatory diagram is a time chart showing the processing order of each decoding process for a plurality of codes performed by the arithmetic decoder 3. In this explanatory diagram, the horizontal axis is a time axis and the vertical axis is a code corresponding to a symbol, and three consecutive codes (one symbol corresponds to one code) are sequentially decoded. It shows the processing time in time. For the same code, the above-described series of processing (shift processing, code length specifying processing, table access processing) is sequentially executed. In this case, a shift process (plain color in the figure) and a code length specifying process (shaded line in the figure) are performed in the period t0 to t1 in the period t0 to t1, and the table access process (see FIG. (Shaded inside) shall be performed.

  First, in a period t0, a shift process for code 1 is performed, and then a code length specifying process is performed. When the original code length (corresponding to one symbol) is specified for code 1 by this code length specifying process, this time (code 1) decoding process (table access process) and next time (code 2) are specified in period t1. ) Decoding process (shift process / code length specifying process) is started in parallel. At this time, the table access process, the shift process, and the code length specifying process are performed independently of each other, so that the process for a plurality of continuous processing units is performed in a pipeline manner, that is, simultaneously in parallel. To be processed.

  Then, in the period t2, the current decoding process (reference 2) (table access process) and the next decoding process (reference 3) (shift process / code length identification process) are started in parallel. Further, in parallel with these processes, a decoding process of code 1 is performed. At this time, the contents of the three tables (the base table, the offset table, and the symbol table) are unchanged even during the decoding process, and even when different code sequences are decoded, a plurality of different input codes are targeted for the same table. Can be accepted. Therefore, a plurality of table access processes can be processed in parallel.

  The decoding process of code 1 is completed in the second half of the period t2 to t3, the decoding process of code 2 is completed in the second half of the period t3 to t4, and the decoding process of code 3 is completed in the second half of the period t4 to t5. The obtained symbols are output continuously.

  According to the present embodiment, since the code length specifying process (and the shift process) and the table access process are independent of each other, the code length of the input code using the base table can be specified at an early stage. As a result, processing can be pipelined. In addition, since the contents of each table remain unchanged even during decoding processing, it is possible to accept multiple accesses to the same table even during decoding of different code strings, so multiple table access processing can be performed in parallel. It is. As a result, the processing speed of the entire code string can be increased.

  Further, according to the present embodiment, since it is not necessary to hold a code string that can be input next time in the decoding system, it is possible to suppress an increase in circuit scale of the entire decoding system.

(Second Embodiment)
FIG. 4 is a configuration diagram of the decoding system in the present embodiment. Similar to the decoding system of the first embodiment, a code string encoded by the canonical Huffman method is to be decoded, and a symbol string in which a plurality of symbols are arranged is output. However, the decoding target of the present embodiment includes a symbol string having an arrangement characteristic, specifically, another type of symbol immediately after a specific character symbol, and the specific character symbol has been previously determined. This is a symbol string. For example, the symbol string “a, 4” includes a specific character symbol (specific symbol) of the symbol “a” and another type of character symbol (run symbol) immediately after the specific character symbol. Note that the symbol sequence that is the basis of this symbol sequence is “a, a, a, a”.

  The decoding system includes a buffer 1, a shifter 2, a main decoder 8, and two sub decoders (9a, 9b). The buffer 1 stores a code string encoded by the canonical Huffman method, similarly to the buffer of the first embodiment described above. The shifter 2 performs a shift process on the buffer 1 as in the first embodiment, but the instruction of the shift process itself is the main decoder 8 and the first and second sub-decoders (9a, 9b). The point that is done depends on. The shifted bit (sign) is input to these decoders (8, 9a, 9b).

  The main decoder 8 decodes a code corresponding to a specific symbol among the input codes. The main decoder 8 includes a determination table management unit 8a, a decoding unit 8b, and a control unit 8c. The determination table management unit 8a has a determination table in which a code is stored in association with each preset specific symbol based on the arrangement characteristics of the symbol string. The decoding unit 8b refers to the determination table of the determination table management unit 8a and outputs a specific symbol corresponding to the input code as a decoding result. If the control unit 8c determines that the code string of the current processing unit includes the code of the specific symbol, the control unit 8c selectively designates the processing subject relating to the subsequent processing units.

  The first sub-decoder 9a is provided in parallel with the main decoder 8. The sub-decoder 9a pipelines a plurality of processing units to be processed by itself and decodes the processing units to be processed by the sub-decoder 9a according to the designation from the main decoder 8 (control unit 8c). The obtained symbol is selectively output as a decoding result. The configuration and operation of the first sub-decoder 9a is similar to that of the arithmetic decoder 3 in the first embodiment, and codes are decoded with reference to a plurality of tables. Note that the storage contents of each table of the first sub-decoder 9a in the present embodiment are the same as those of the arithmetic decoder 3 in the first embodiment.

  The second sub-decoder 9b is provided in parallel with the main decoder 8 in the same manner as the first sub-decoder 9a. Further, according to the designation from the main decoder 8 (control unit 8c), a symbol obtained by decoding a processing unit to be processed by itself is selectively output as a decoding result. The configuration and operation of the second sub-decoder 9b is similar to that of the arithmetic decoder 3 and the first sub-decoder 9a in the first embodiment, and codes are decoded with reference to a plurality of tables. Note that the content stored in each table of the second sub-decoder 9b in the present embodiment is different from that of the arithmetic decoder 3 in the first embodiment.

  FIG. 5 is a configuration diagram of a determination table of the determination table management unit 8a. In this determination table, a code, a symbol corresponding to the code, and a code length are stored in association with each other. The determination table shown in FIG. 6 includes run symbols (symbols “2” to “4”) for the character symbols of the first embodiment (when a symbol string composed of symbols “A” to “F” is encoded). Among the symbols with the symbol added, the stored contents are given when the specific symbols are symbols “F”, “H” and “4”.

  FIG. 10A is a configuration diagram of a determination table in the case where decoding processing is performed in parallel with the first sub-decoder 9a. The codes described in this table are all composed of a bit string consisting of the maximum code length. For example, when the maximum code length is 4, the codes described are all composed of 4 bits. This is because a symbol corresponding to this is directly calculated only by referring to a table (determination table) using a 4-bit code input from the buffer 1 as an input. FIG. 6B is a configuration diagram of a determination table when decoding processing is performed in parallel with the second sub-decoder 9b. The code is composed of a bit string consisting of the maximum code length as in FIG. 5A, but can be input when decoding in parallel with the second sub-decoder (corresponding to the run symbol). Since the maximum code length of the code is 2, the stored code consists of 2 bits. Note that the specific symbol in the present embodiment also includes an end symbol indicating the end of the decoding process (for example, the last symbol in the symbol string), and the decoding target includes a code obtained by encoding the end symbol. (In this embodiment, symbol “H” and symbol “4” are end symbols).

  As a specific example using this determination table, a case where a symbol is decoded from an input code “0001” will be described. Note that the decoding process of the code string is referred to as direct decoding with respect to arithmetic decoding in which decoding is performed using a plurality of tables in the first embodiment. Direct decoding is composed of shift processing and table access processing. Further, it is assumed that the immediately preceding symbol is not a specific symbol.

(Shift processing)
The shift process performed by the main decoder 8 is a process of inputting a part of the code string as an input code, similarly to the shift process in the first embodiment. However, the specific control is different from that of the first embodiment. First, the control unit 8c and the control unit (not shown) built in the first and second sub-decoders instruct the shifter 2 to the buffer 1 for bit shift processing. Then, the shifter 2 bit-shifts the buffer 1 according to this instruction, and inputs the input code to the main decoder 8 (decoding unit 8b) and the first and second sub-decoders (9a, 9b). In this case, the shifter 2 shifts the buffer 1 so that a 4-bit code string “0001” is read as an input code into each decoder.

(Table access processing)
The table access process performed by the main decoder 8 is a process of directly outputting a symbol from the input code input by the shift process described above. Specifically, the decoding unit 8b outputs a symbol and a code length based on the input code and information (code / code length / symbol) of the determination table input from the determination table management unit 8a. Then, a symbol corresponding to a code having the same code as the input code is output, and a code length corresponding to this code is also output. In this case, since the input code “0001” corresponds to the symbol “F”, the symbol “F” is output as an output symbol, and the code length “2” corresponding to the symbol “F” is also output. . Receiving these data, the control unit 8c controls the shift amount to be input to each decoder (8, 9a, 9b) next time based on this code length “2”.

  FIG. 6 is a configuration diagram of each table of the second sub-decoder 9b. The table type of the second sub-decoder is the same as that of the table in the first embodiment, but the described contents are different. Specifically, this description includes a symbol (number) indicating a run symbol (following immediately after) for a specific symbol in the symbol string. FIG. 4A is a configuration diagram of a base table, FIG. 4B is a configuration diagram of an offset table, and FIG. 4C is a configuration diagram of a symbol table. It should be noted here that the run symbol is encoded using a table different from a normal (character) symbol, so that the size of the table to be used can be reduced. In the present embodiment, according to the base table of FIG.

  FIG. 7 is a flowchart of the decoding process. First, in step 1, a code as a current processing unit is input. Specifically, the shifter 2 inputs a part of the code string stored in the buffer 1 as an input code to the main decoder 8 and the first sub-decoder 9a. In the subsequent step 2, the main decoder 8 and the first sub-decoder 9a decode this input code.

  In step 3, the main decoder 8 determines whether or not a specific symbol is output from the input code to be decoded in step 2. Specifically, the control unit 8c determines whether or not a specific symbol (a symbol indicating the end of decoding) is output from the decoding unit 8b, that is, the next input code to be input is a run symbol or an end symbol. Detect whether or not. If a specific symbol is detected, the process proceeds to step 4. On the other hand, if a specific symbol is not detected, the process returns to step 1.

  In step 4, it is determined whether or not the specific symbol output in step 3 is an end symbol. Specifically, the control unit 8c detects whether or not the specific symbol is an end symbol, that is, whether or not to end the next decoding process. If the specific symbol is not an end symbol, the process proceeds to step 5. If the specific symbol is an end symbol, the decoding process ends.

  In step 5, the first sub-decoder 9a stops the decoding process for the input code input in step 2. Specifically, the control unit 8c instructs the first sub-decoder 9a to stop the decoding process of the input code input in step 2. In response to this instruction, the first sub-decoder 9a stops the decoding process. At that time, the control unit 8c instructs the shifter 2 to input a new code (perform shift processing) based on the code length generated together with the symbol by the decoding unit 8b.

  Next, in step 6, a new code that is a code immediately following the input code in step 1 is input. Specifically, the shifter 2 inputs a part of the code string stored in the buffer 1 as a new input code to the main decoder 8 and the second sub-decoder 9b. In the subsequent step 7, the main decoder 8 and the second sub-decoder 9b decode the new input code.

  In step 8, the main decoder 8 determines whether or not a specific symbol is output from the new input code to be decoded in step 7. Specifically, the control unit 8c detects whether or not a specific symbol is output from the decoding unit 8b, that is, whether or not the next input code to be input is a run symbol or an end symbol. If a specific symbol is detected, the process proceeds to step 9. On the other hand, if a specific symbol is not detected, the process returns to step 1.

  In step 9, it is determined whether or not the specific symbol output in step 8 is an end symbol. Specifically, the control unit 8c detects whether or not the specific symbol is an end symbol, that is, whether or not to end the next decoding process. If the specific symbol is not an end symbol, the process proceeds to step 10. If the specific symbol is an end symbol, the decoding process ends.

  In step 10, the second sub-decoder 9b stops the decoding process for the new input code input in step 6. Specifically, the control unit 8c instructs the second sub-decoder 9b to stop the decoding process of the input code input in step 6. In response to this instruction, the second sub-decoder 9b stops the decoding process. At that time, the control unit 8c instructs the shifter 2 to input a new code based on the code length generated together with the symbol by the decoding unit 8b. This is because the specific symbol that appears after the specific symbol (run symbol) in the symbol string of this embodiment is only the end symbol (the run symbols are not continuous), and the end symbol was not detected in step 9. This is because the next symbol in the case is a normal (character) symbol.

  In step 1 and step 6, the input code input may be input to the second sub-decoder 9 b in step 1 and also to the first sub-decoder 9 a in step 6. However, in this case, each sub-decoder 9a, 9b outputs a symbol obtained by decoding a processing unit to be processed as a decoding result, so that a correct decoding result cannot be obtained. Therefore, these decoding results are discarded or deleted.

  FIG. 8 is an explanatory diagram of the decoding process. This explanatory diagram is a time chart showing the processing order of the respective decoding processes for a plurality of input codes performed by the respective decoders 8, 9a, 9b based on the processing flowchart of FIG. The main decoder 8 sequentially executes the above-described two processes (shift process and table access process) for one code. Similarly to the arithmetic decoder 3 of the first embodiment, the first sub-decoder 9a and the second sub-decoder 9b perform the above-described three processes (shift process / code length specifying process) for one code. -Table access processing) is executed sequentially.

  Next, a decoding process of a code string (reference numerals 1 to 6) corresponding to six consecutive symbols will be described based on this explanatory diagram. As an example, the code sequence includes symbols “A”, “B”, “F”, and “F” with specific symbols as symbols “F”, “H”, and “4”, of which “H” and “4” are end symbols. , 4 "are encoded. Here, the values in parentheses described in the shift process (plain color) indicate the order of the input codes (a group including one symbol), and shift processes having values in the same parentheses have the same signs. To be done. For example, (1) shows the code 1 and (2) shows the code 2, and the process that continues beside it is the process for the same code.

  First, in a period t0, shift processing by the shifter 2 is performed, and code 1 is read into the main decoder 8 and the first sub-decoder 9a (step 1). Then, the main decoder 8 performs a table access process for the code 1, and at the same time, the first sub-decoder 9a performs a code length specifying process (step 2).

  In the period t1, since the main decoder 8 does not decode the specific symbol from the code 1, the first sub-decoder 9a, which has performed the code length specifying process in parallel with this, performs the calculation based on the calculated code length of the code 1, A shift process is instructed to the shifter 2 (step 3). Then, code 2 is read into the main decoder 8 and the first sub-decoder 9a (step 1). Next, as in the period t0, the main decoder 8 and the first sub-decoder 9a perform decoding processing on the code 2 (step 2). On the other hand, the decoding process of code 1 is continuously performed by the first sub-decoder 9a.

  In the period t2, as in the period t1, the main decoder 8 does not decode the specific symbol from the code 1, so that the first sub-decoder 9a that has performed the code length specifying process in parallel with the code 1 calculates the code 2 Based on the code length, a shift process is instructed to the shifter 2 (step 3). The code 3 is read into the main decoder 8 and the first sub-decoder 9a (step 1). Next, as in the period t0, the main decoder 8 and the first sub-decoder 9a perform decoding processing on the code 2 (step 2).

  On the other hand, the decoding process (table access process) of code 2 is continuously performed by the first sub-decoder 9a. This is because, as in the first embodiment, the description content of the table of the first sub-decoder 9a is not changed during the decoding process. Thereby, even when different code strings are decoded, it is possible to accept a plurality of accesses to the same table, and it is possible to perform pipeline processing of decoding processing for a plurality of codes.

  In the period t3, the main decoder 8 decodes the specific symbol “F” which is not the end symbol from the code 3 (steps 3 and 4), so that the main decoder 8 (control unit 8c) uses the code 3 of the first sub-decoder 9a. The decoding process for is stopped (step 5). Based on the code length calculated in parallel with the specific symbol, the main decoder 8 instructs the shifter 2 to perform the shift process, and the code 4 is read into the main decoder 8 and the second sub-decoder 9b (step 6). ). Next, the main decoder 8 and the second sub-decoder 9b perform a decoding process on the code 4 (step 7). Note that the decoding process for code 2 is continued by the first sub-decoder 9a.

  Since the main decoder 8 does not decode the specific symbol from the code 1 in the period t4, the second sub-decoder 9b that has performed the code length specifying process in parallel performs the shift process based on the calculated code length of the code 4. To the shifter 2 (step 8). The code 5 is read into the main decoder 8 and the first sub-decoder 9a, and is decoded (steps 1 and 2). Note that the decoding process of code 4 is continued by the second sub-decoder 9b.

  In the period t5, as in the period t3, the main decoder 8 decodes the specific symbol “F” which is not the end symbol from the code 5 (steps 3 and 4), so the main decoder 8 uses the code 3 of the first sub-decoder 9a. The decoding process for is stopped (step 5). Then, the main decoder 8 instructs the shifter 2 to perform the shift process, and the code 6 is read into the main decoder 8 and the second sub-decoder 9b and decoded (steps 6 and 7). Subsequently, since the main decoder 8 decodes the specific symbol “4” as the end symbol from the code 6 in the period t6 (steps 8 and 9), the decoding process is ended.

  As described above, according to the present embodiment, as in the first embodiment, in addition to performing decoding processing in a pipeline, a code obtained by encoding a symbol string including a run symbol immediately following a specific symbol is encoded. Even for columns, the decoding process can be pipelined. As a result, the processing speed of the entire code string can be increased. Further, according to the present embodiment, as in the first embodiment, since it is not necessary to store a code that can be input next time in the decoding system, the scale of the circuit of the entire decoding system is increased. Can be prevented.

  In the embodiment described above, the code sequence obtained by encoding the symbol sequence including the specific symbol and the run symbol immediately after the specific symbol is decoded. However, the present invention is not limited to this. For example, the present invention can also be applied to a code string obtained by encoding a symbol string including a correlation between two preceding and following symbols. Here, the correlation refers to a relationship that has a high probability that the next (time) symbol after a certain symbol is a predetermined symbol.

  As an example, the symbol that appears next to the symbol “A” is the symbol “B” as in the symbol string “A, B, C, A, A, B, C, A, A, B, C, D”. Consider the case with a high probability of. In this case, the specific symbol set in the determination table is the symbol “A”, and the operation decoder dedicated to the symbol next to the symbol “A” is the second sub-decoder 9b. That is, the same effect as described above can be obtained by replacing the run symbol correlated with the specific symbol with another character symbol. In this case, when the symbol “A” continues in the decoding process from the code string, the second sub-decoder 9b uses the same table as in the operation decoder 3 of the first embodiment. Can be processed.

  Furthermore, the present invention can also be applied to a code string obtained by coding a symbol string in which a plurality of symbols including such correlations are continuous. Specifically, there is a high probability that a symbol next to a symbol that appears (decoded) in a certain order is a predetermined symbol.

  As an example, the following symbols appearing in the order of the symbols “A, B”, such as the symbol string “A, B, C, B, A, B, C, C, A, B, C, D”, Consider the case where the probability of being symbol “C” is high. In this case, the specific symbols set in the determination table are symbols “A” and “B”, and a buffer capable of storing recently output symbols is provided in the main decoder 8 (for example, the control unit 8c). Further, a third sub-decoder (not shown) is provided in parallel with each decoder (8, 9a, 9b), and an operation decoder dedicated to the next symbol after the symbol “A” is set as the second sub-decoder 9b. This can be dealt with by using a third sub-decoder as an arithmetic decoder dedicated to the symbol following the symbol “B”. That is, the same effect as described above can be obtained by providing sub-decoders that are arithmetic decoders according to the number of specific symbols having continuous correlation. At this time, when the main decoder 8 determines that the code of the specific symbol is included in a predetermined order in the continuous processing unit including the current time, the main decoder 8 outputs the specific symbol corresponding to the code as a decoding result, and The processing subject relating to subsequent processing units is further selectively specified. Specifically, when the main decoder 8 determines that the specific symbol outputs “A” in the previous processing unit and the current processing unit specific symbol “B” is output, the control unit 8c determines the next code. The processing subject is designated as the third sub-decoding.

  Further, in this case, in the decoding process from the code string as in the above-described extended example, when the symbol “A” is continuously decoded, the second sub-decoder 9b determines that the symbol “B” In the case of continuous decoding, the third sub-decoder may execute pipeline processing using the same table, similarly to the arithmetic decoder 3 of the first embodiment.

  In the two extended examples described above, the main decoder 8 that decodes a specific symbol has one determination table. However, the present invention is not limited to this, and the main decoder 8 determines (outputs) symbols. You may have two or more according to the kind of. For example, in the extension plan 1, a determination table used when decoding the symbol next to the symbol “A” (in parallel with the second sub-decoder 9b) and a normal (first sub-decoder 9a) It may be separated from the determination table used for the decoding process. This is because the symbol sequence corresponds to a code sequence encoded using a different table by considering the above correlation.

  Further, in each of the embodiments including the above-described extension plan, a symbol string including a text (character) such as “a” or “b” or a numerical value (number) such as “2” or “3” is encoded. The coded code string has been described. However, the present invention is not limited to these, and is naturally applicable to data formats such as image data and audio data.

Configuration diagram of a decoding system according to the first embodiment Arithmetic decoder table configuration diagram Illustration of decryption process Configuration diagram of decoding system in second embodiment Judgment table configuration diagram Structure of second sub-decoder table Decoding process flowchart Illustration of decryption process

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Buffer 2 Shifter 3 Operation decoder 4 Base table management part 5 Code length specific | specification part 6 Decoding process part 6a Offset table management part 6b Symbol table management part 6c Address generation part 7 Control part 8 Main decoder 8a Judgment table management part 8b Decoding part 8c control unit 9a first sub-decoder 9b second sub-decoder

Claims (5)

A code string encoded by the canonical Huffman method is to be decoded, and a decoding process is repeated for each processing unit of a predetermined code length that constitutes a part of the code string, whereby a symbol string in which a plurality of symbols are arranged is obtained. In the output decryption system,
A base table in which a head code is described in association with each of a plurality of different code lengths;
A code length specifying unit that performs a code length specifying process for specifying a code length of a decoding target included in a processing unit by comparing the starting code for each code length described in the base table with the starting code of the processing unit. When,
A decoding processing unit that outputs a symbol corresponding to the decoding target by performing a decoding process for decoding the decoding target whose code length is specified by the code length specifying unit;
A control unit that instructs the code length specifying unit to start the code length specifying process for the next processing unit after the end of the code length specifying process for the current processing unit and before the end of the decoding process; A decoding system comprising: A code string encoded by the canonical Huffman method is to be decoded, and a decoding process is repeated for each processing unit of a predetermined code length that constitutes a part of the code string, whereby a symbol string in which a plurality of symbols are arranged is obtained. In the output decryption system,
Based on the arrangement characteristics of the symbol sequence, it is determined that the code of the specific symbol is included in the current processing unit by referring to the determination table in which the code is described in association with each of the predetermined specific symbols. A main decoder that outputs a specific symbol corresponding to the code as a decoding result and selectively designates a processing subject relating to a processing unit after this time;
A plurality of processing units to be processed by itself are processed by a pipeline provided in parallel to the main decoder, and the processing units to be processed by itself are decoded according to the designation from the main decoder. A first sub-decoder that selectively outputs a symbol obtained by the above as a decoding result;
Secondly provided in parallel with the main decoder, and selectively outputs a symbol obtained by decoding a processing unit to be processed by itself as a decoding result in accordance with a designation from the main decoder. And a sub-decoder. The first sub-decoder includes:
A base table in which a head code is described in association with each of a plurality of different code lengths;
A code length specifying unit that performs a code length specifying process for specifying a code length of a decoding target included in a processing unit by comparing the starting code for each code length described in the base table with the starting code of the processing unit. When,
A decoding processing unit that outputs a symbol corresponding to the decoding target by performing a decoding process for decoding the decoding target whose code length is specified by the code length specifying unit;
A control unit that instructs the code length specifying unit to start the code length specifying process for the next processing unit after the end of the code length specifying process for the current processing unit and before the end of the decoding process; The decoding system according to claim 2, further comprising: The code string is composed of a plurality of types of character symbols and run symbols indicating the number of consecutive same type of character symbols,
The main decoder outputs a character symbol immediately before a run symbol as the specific symbol,
The first sub-decoder decodes the current processing unit when the specific symbol is not included in the current processing unit and the specific symbol is not included in the previous processing unit. Output the character symbol obtained by the decoding result,
The second sub-decoder decodes the current processing unit when the specific symbol is not included in the current processing unit and the specific symbol is included in the previous processing unit. 4. The decoding system according to claim 2, wherein the obtained run symbol is output as a decoding result.   When the main decoder determines that the code of the specific symbol is included in a predetermined order in the continuous processing unit including the current time, the main decoder outputs the specific symbol corresponding to the code as a decoding result, and processes subsequent to the current time 5. The decoding system according to claim 2, wherein a processing subject relating to the unit is further selectively specified.

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