JPH0883347A - Picture processor - Google Patents

Abstract

PURPOSE: To shorten time to be required for the detection of a delimitation code by allowing a parallel delimitation code detecting part to input data to be decoded from a program search shifting part and simultaneously detect the delimitation codes of plural leading bit positions. CONSTITUTION: The parallel delimitation code detecting part 13 has 31 delimitation code detectors 27-1 to 27-31, which respectively input 24-bit data respectively having the 1st bit to 31-th bit of a code D11 to be decoded on their leading bits. Namely the detector 27-1 inputs 1st to 24th bits, the detector 27-2 inputs 2nd to 25-th bits, the following detectors also similarly input data, and finally the detector 27-31 inputs 31-th to 54-th bits. Each of the detectors 27-1 to 27-31 compares the inputted 24-bit data with '000001H' and outputs a compared result. A control circuit 28 inputs respective compared results, and when any one of the results indicates a start code, judges the position of the start code.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an increase in processing speed of an image processing apparatus, and more particularly, to a buffer memory of an image processing apparatus for decompressing compressed image data and a processing speed of a decoder. It is about speeding up.

[0002]

2. Description of the Related Art Conventionally, an image processing apparatus that compresses / expands image data has been known.

As an image processing apparatus for compressing image data, for example, a combination of DCT (Discrete Cosine Transform), quantization, run length coding and variable length / fixed length coding is known. In such an image processing apparatus, first, the image data is divided into small blocks (for example, blocks of 8 × 8 pixels), and each block is a two-dimensional DCT.
After performing orthogonal transformation such as, the quantization is performed for each pixel. Next, after each block is converted so that the number of consecutive "0" s becomes high (scan order conversion), it is arranged in one dimension and the number of leading "0s" (hereinafter referred to as "zero run") and "0" The number of symbols is reduced by expressing it as a set with a value other than "(hereinafter referred to as" level ") (run length encoding). Then, this data is converted into data consisting of a variable length code, a fixed length code and a delimiter code (variable length / fixed length coding) and output.

Here, the above-mentioned scan order conversion and run-length coding will be described in more detail with reference to FIG. FIG. 7A shows a block after orthogonal transform (DCT etc.) and quantization. Two-dimensional D
Data that has undergone orthogonal transformation such as CT uses the fact that the resolution of the high frequency component is not visually high, and gives a large quantization width to the data corresponding to this high frequency component,
The frequency of appearance of "0" is increased. Next, with respect to these pixel data, each pixel forming an 8 × 8 matrix is read in a zigzag manner as indicated by an arrow in FIG. As a result, a data string as shown in FIG. 7B is obtained. Then, by performing run-length coding on this data string, data (run-length code) as shown in FIG. 7C is obtained. In FIG. 7C, the value on the left side in each parenthesis is zero run, and the value on the right side is a level. The run-length code generated in this way is variable-length / fixed-length coded and output. Here, as shown in FIG. 7A, the reason why the pixels of the pixel block are read in zigzag is that the deviation of the values of the zero runs is larger when the run length code is variable length encoded. This is because the compression rate becomes high.

Next, an image processing apparatus for decompressing the image data thus compressed will be described. Figure 8
FIG. 3 is a block diagram schematically showing a configuration of such an image processing device. As shown in the figure, the compressed image data input to the image processing apparatus is taken into the variable length / fixed length decoder 82 via the buffer 81, and the data as shown in FIG. It is decoded into a sequence (run length code). The output data of the variable length / fixed length decoder 82 is
Next, it is input to the run length decoding / scan order converter 83.

Here, in the run length decoding and the scan order conversion, as shown in FIG. 7A, the scan order conversion is performed after the data string shown in FIG. 7B is generated by the run length decoding. Although it is possible to generate data of a large 8 × 8 pixel block, it is assumed here that run length decoding and scan order conversion are performed simultaneously using a buffer memory as described below.

After that, the image data subjected to run-length decoding and scan order conversion is subjected to inverse quantization and inverse discrete cosine transform by an inverse quantizer 85 and an inverse orthogonal transformer 86, and then decompressed image data. Is output as.

Here, the processing (variable length / fixed length decoding) in the variable length / fixed length decoder 82 will be described in more detail. Here, a case where the MPEG (Moving Pictures Expert Group) method is adopted as a variable-length / fixed-length encoding method will be described as an example.

The image data (compressed image data) input to the variable-length / fixed-length decoder 82 is composed of a continuous data string without a break (see FIG. 10 described later).
(See "Decoded code" in (a)). Here, this data string includes a start code that is a code indicating a data delimiter. As this start code, for example, a start code indicating the start of image data for one screen
(picture start code) and the like (see FIG. 10B described later). This start code will not be decoded (decoded) mistakenly for other data or flags even if the decoding is started in the middle of the data string, and the start code will not be affected by any combination of other data or flags. It is set so that it will not be mistakenly deciphered. Therefore, it is used for determining the position to start decoding and the decoding return position when a decoding error occurs.

The operation of the variable length / fixed length decoder 82 will be described below with reference to FIGS. 9 to 11.

FIG. 9 is a block diagram schematically showing the internal structure of the variable length / fixed length decoder 82. In the figure, the code decoding unit 92 first inputs 32 bits of the code to be decoded D ₉₁ from the cue shift unit 91, and the value of the code to be decoded D ₉₁ is "00" for the first 24 bits.
0001H ”(“ H ”indicates hexadecimal notation. The same applies hereinafter) is determined (S111 in FIG. 11). The decoded code D ₉₁ is "000001.
If it is not "H", the decoded code D ₉₁ is sent to the cue shift unit _91.
Is shifted by 1 bit (S112 in the figure). Next, for the decoded 24-bit decoded code D ₉₁ (that is, from the second bit counted from the first input code, 2
For the 5th bit), it is determined whether or not it matches "000001H" (S111 in the same figure). Below, "00
The same operation is repeated until "0001H" is detected.

Here, as shown in FIG. 10B, the upper 6 bits of the start code (24 bits in binary)
Is always "000001H". Therefore, when the code decoding unit 92 detects "000001H", it can be known that any start code exists.

When "000001H" is detected, the code decoding unit 92 extracts the code to be decoded D ₉₁ by 24 bits (16 bits) in order to cut out the portion corresponding to "000001H".
It shifts by 6 digits of the decimal number) (S1 in FIG. 11)
13). Then, in order to cut out the remaining digits of the detected start code, the input code is further shifted by 8 bits (corresponding to two hexadecimal digits) (S11 in FIG. 11).
4).

Subsequently, the code decoding unit 92 decodes (decodes) the variable length / fixed length code following the start code. In FIG. 10A, the first 3
The digit is "101", and this variable length code corresponds to "3" (see FIG. 10C). Therefore, the code decoding unit 9
2 outputs “3” as the decoding result (run length code), and further outputs “3” which is the pattern length (number of digits) of the variable length code as the cue shift amount information D ₉₂ . Upon receiving the cue shift amount information D ₉₂ , the cue shift section 91 shifts the decoded code D ₉₁ by 3 bits. As a result, the code to be decoded D ₉₁ input by the code decoding unit 92 after this shift has a value as shown in (b) of FIG. Then, the code decoding unit 92 identifies that the first two digits "01" of the decoded code _D91 corresponds to "2", outputs "2" as the decoding result, and also outputs the pattern length "2". The output shift amount information D ₉₂ is output.
Thereafter, similarly, the detection of the start code and the decoding of the variable length / fixed length code are continued.

The data string (run length code) of the decoding result generated in this way is sent to the run length decoding / scan order converter 83 (see FIG. 8).

Here, during decoding of the variable length / fixed length code,
When a code pattern that does not exist in the variable length code table (see FIG. 10C) or the fixed length code table (not shown) appears, the code decoding unit 92 determines that some decoding error has occurred. To do. In the case of decoding a code including a variable length code, if the decoding start position is once displaced due to a decoding error, it is meaningless to continue decoding the remaining input code. Therefore, the code decoding unit 92 stops decoding the variable-length / fixed-length code and detects the next start code (see FIG. 11). Then, when the start code is detected, the decoding of the variable length / fixed length code as described above is restarted (see FIG. 10A).

Next, regarding the processing (run length decoding and scan order conversion) in the run length decoding / scan order converter 83 of the image processing apparatus shown in FIG.
This will be described in more detail.

FIG. 12 is a block diagram schematically showing the internal structure of the run length decoding / scan order converter 83. As shown in the figure, a buffer memory is used as the run-length decoding / scan order converter 83.

In FIG. 12, the bank memories 121a and 121b in the memory section 121 have a writing area corresponding to 8 × 8 pixels (that is, one block). Then, these write areas are all initialized to zero before data is written.

The write address generator 122 includes an adder 122a and a register 122b. here,
The output of the register 122b is initialized to "0" before writing data. The adder 122a is
Output of register 122b and variable length / fixed length decoder 8
The zero run of the data string (run length code) input from 2 is input. Then, the result of adding this register output and zero run is sent to the memory unit 121 as a write address. Thereby, the "level" signal of the run length code can be sequentially written to the corresponding address of either the bank memory 121a or the bank memory 121b (specified by the controller 124). Then, as described above, since the addresses other than the address in which the "level" signal is written are initialized to "0", run length decoding can be performed by this writing.

The read address generator 123 comprises a counter 123a and an address converter 123b.
As a result, the data string written in the bank memory 121a or the bank memory 121b (designated by the controller 124) can be read out while the scan order is being converted, and the quantized DC as shown in FIG.
The T coefficient can be obtained. Further, at the time of this reading, the read address S _R is used as the write address S _R ′, and by sequentially writing “0”, the initialization for the next writing can be performed.

As described above, the controller 124 selects a bank memory for writing / reading data, outputs a write inhibit signal to the variable length / fixed length decoder 82, and outputs the variable length / fixed length decoder. The write timing is controlled by the input of the write end signal from 82.

[0023]

A conventional image processing apparatus as shown in FIG. 8 (image processing apparatus for expanding image data)
Was not fast enough.

Here, in the variable-length / fixed-length decoder 82 (see FIG. 9), it takes a lot of time to detect the delimiter code, which is one of the causes of slowing down the processing speed. Was there. That is, in the conventional variable-length / fixed-length decoder 82, the delimiter code is detected while shifting the code to be decoded one bit at a time at a rate of 1 bit / cycle. I needed time.

The conventional variable-length / fixed-length decoder 82 is also used.
When a decoding error is detected after a part of the delimiter code is used for erroneous decoding, the error recovery position becomes the next delimiter code, so discard it when a decoding error occurs. There is also a drawback that the amount of image data that can be stored increases.

On the other hand, in the run length decoding / scan order converter 83 (see FIG. 12), the bank memory 1
Although the time required for writing / reading 21a and 121b is not actually constant, the time interval for switching between the bank memory for writing and the bank memory for reading is constant, which means that the processing speed is Was one of the causes to slow down. The reason for this will be described below.

If the time required for writing / reading to / from the bank memories 121a and 121b is always constant, the time interval for switching the bank memories may be determined in accordance with whichever of writing / reading is later. Here, for example, it is assumed that there are always 16 fixed-length / variable-length codes in a data string for one block (8 × 8 = 64 pixels), and the time required for run-length decoding (that is, to the bank memory). If the time required for writing) is 3 clocks for each piece of data, the time required for writing the data string for one block is 16 × 3 = 48 clocks. On the other hand, if the time required to read the data from the bank memory is 1 clock per data, the time required to read the data string for 1 block is 64 clocks. Therefore, the switching between the bank memory for writing and the bank memory for reading may be performed every 64 clocks as shown in FIG. 13, and the processing time is not wasted, so that high-speed processing can be performed.

However, in the image data, the amount of information is increased when the image corresponding to the block is a complicated portion such as an edge, and the amount of information is reduced when the image is a simple image with almost no change. It is common. For this reason,
The number of fixed-length / variable-length codes included in the data string for one block is not fixed, but increases or decreases depending on the complexity of the image. Here, considering the case where all the data included in the data string for one block are fixed-length / variable-length codes, the time required for writing is 64 × 3 = 192 clocks. Therefore, switching between the bank memory for writing and the bank memory for reading must also be performed every 198 clocks, as shown in FIG.

Considering the entire image data, there is almost no probability that the majority of the data string for one block will be occupied by the fixed length / variable length code. Nevertheless, in the conventional run-length decoding / scan order converter 83, when the time required for writing is the longest (that is, all the data included in the data string for one block are fixed-length / variable-length codes). In some cases), the time interval for switching the bank memory has to be set, which causes the processing speed to slow down.

The present invention has been made in view of the above drawbacks of the prior art, and an object of the present invention is to provide an image processing apparatus capable of high-speed processing.

[0031]

[Means for Solving the Problems]

(1) An image processing apparatus according to a first aspect of the present invention is an image processing apparatus including a decoder for decoding compressed image data having at least a variable length code and a delimiter code, wherein the decoder is the A compressed image data and cue shift amount data are input, and a cue shift unit that generates decoded data by shifting the compressed image data according to the cue shift amount data, and fetched from the cue shift unit. By cutting out the data to be decoded,
A code decoding unit for generating decoded data and detection of the delimiter code from the decoded data fetched from the cue shift unit are simultaneously performed for a plurality of head bit positions,
And a parallel delimiter code detection unit that generates the shift amount data based on the detection result. (2) An image processing device according to a second aspect of the present invention is an image processing device having a buffer memory including a plurality of bank memories and a control circuit for controlling reading and writing of these bank memories. , At the time when the writing to one of the bank memories is finished, if there is another bank memory that has already been read, the next write is performed to the other bank memory, and the reading is already finished. If there is no such bank memory, the write control means waits until the reading of one of the bank memories is completed and then writes to the bank memory whose reading is completed and prohibits the writing during the waiting period. Then, when the reading from one of the bank memories is completed, the writing has already been completed. If another bank memory exists, the next read operation is performed according to the order in which the other bank memory was written. If no bank memory has already been written, either bank After waiting until the writing of the memory is completed, the bank memory in which the writing has been completed is read, and a read control unit that prohibits the reading during the waiting period is provided.

[0032]

[Action]

(1) According to the first invention, the parallel delimiter code detection unit takes in the data to be decoded from the cue shift unit and simultaneously detects the delimiter code for a plurality of head bit positions. The time required to detect the delimiter code can be shortened. (2) According to the second aspect of the present invention, the control for switching the bank memory is such that, for writing, if there is a bank memory that has finished reading when writing to any of the bank memories ends, If there is no bank memory that has been written to and read from it, wait until the read is completed and then write.When reading, write from any bank memory is completed. If there is a bank memory for which writing has been completed, the next read is performed in the order of writing, and if there is no bank memory for which writing has finished, it is decided to wait until the writing has finished and then read. The time during which reading is not performed can be reduced.
The processing speed can be improved by improving the operation efficiency in this way.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An image processing apparatus according to an embodiment of the present invention will be described below.

The overall structure of the image processing apparatus according to this embodiment is the same as that of the conventional image processing apparatus shown in FIG.
The configurations of the variable-length / fixed-length decoder and the run-length decoding / scan order converter are different from those of the conventional apparatus.

First, the variable length / fixed length decoder according to this embodiment will be described. This variable-length / fixed-length decoder corresponds to the "decoder" of the first invention (claim 1).

FIG. 1 shows such a variable length / fixed length decoder 1.
It is a block diagram which shows the structure of 0 roughly.

In the figure, the cue shift section 11 shifts the input code D _i inputted from the outside in accordance with the cue shift amount information D ₁₂ inputted from the shift amount switching section 14, thereby decoding the decoded code. Generate D ₁₁ . In this embodiment, the maximum value of the number of bits that can be shifted by one shift operation of the cue shift unit 11 (hereinafter referred to as "maximum shift amount") is 31 bits. The bit width of the code to be decoded D ₁₁ is 64 bits. That is, when the maximum shift amount is M, the bit width of the decoded code D ₁₁ is 2 × (M +
It becomes 1).

The code decoding unit 12 inputs the target decryption code D _11, performs the pattern detection and decoding of the variable length code from the head of the object to be decrypted code D _11, and a cut-out of the fixed-length code. Then, the run length code obtained thereby is output as the decoding result D _o , and the pattern length of the variable length code or the fixed length code which has been decoded / cut out is output as the cue shift amount information D ₁₂ ′. . As will be described later, the code decoding unit 12 selects the lower 32 bits of the 64-bit decoded code D ₁₁ output by the cue shift unit 11.
Decodes and cuts out variable-length / fixed-length codes by inputting only bits.

The parallel delimiter code detector 13 simultaneously detects the start code from the decoded code D ₁₁ fetched from the cue shifter 11 at the head bit position of 31 bits, and detects the delimiter code based on this detection result. The shift amount information D ₁₂ ″, the control signal D _13, and the shift amount switching signal D ₁₄ are generated and output.

The shift amount switching unit 14 inputs the cue shift amount information D ₁₂ ′ output by the code decoding device 12 and the delimiter code detection shift amount information D ₁₂ ″ output by the parallel delimiter code detecting unit 13 described later. Then, by controlling the shift amount switching signal D ₁₄ output from the parallel delimiter code detection unit 13, either one of the shift amount information D ₁₂ ′ and D ₁₂ ″ is output as the cue shift amount information D ₁₂ . .

Next, an example of the internal configuration of the cue shift section 11 and the parallel delimiter code detection section 13 will be described with reference to FIG.

In the cue shift unit 11 shown in FIG. 2, the input code is input from one input of the switch 21-1 and the output value of the register 22-1 is input from the other input. On the other hand, the output of the switch 21-1 is input to the register 22-1. The switch 21-2 inputs the output values of the registers 22-1 and 22-2. Then, the output of the switch 21-2 is input to the register 22-2. Further, the switching device 21
-3 inputs the output values of the registers 22-2 and 22-3,
The output of the switch 21-3 is output to the register 22-
Input to 3. Here, these registers 22-1.
As 22-3, 32-bit shift registers are used. That is, assuming that the maximum shift amount of the cue shift unit 11 is M, the registers 22-1 to 22-
As for 3, M + 1 bits are used. An overflow signal D ₂₅ output from the shift amount cumulative adder 24, which will be described later, is used as a control signal for switching the outputs of the switchers 21-1 to 21-3.

The shift amount cumulative adder 23 adds the cue shift amount information D ₁₂ input from the shift amount switching unit 14 and the output value of the shift amount cumulative register 24 to obtain the overflow signal D ₂₅ described above. And the shift amount D ₂₆ for the shift circuit are generated. In addition, the shift amount accumulation register 24
Inputs the shift amount D ₂₆ for the shift circuit. In addition,
Shift amount cumulative adder 23 and shift amount cumulative register 2
The bit width of 4 is log ₂ (M + 1) bits, where M is the maximum shift amount of the cue shifter 11.

The shift circuit 25 includes the switches 21-1 to 21-1.
Output data D _{21 to} D ₂₃ of 21-3 are fetched in parallel. That is, the bit width of the input of the shift circuit 25 is 96 bits (3 (M + 1) bits when the maximum shift amount is M).
Becomes Then, this data is shifted under the control of the shift amount D ₂₆ for the shift circuit output from the shift amount cumulative adder 24, and is output as 64-bit (that is, 2 (M + 1) -bit) data D ₂₇ . This shift circuit 2
The output data of No. 5 is sent to the decoded code D through the register 26.
It is output as ₁₁ .

According to such a configuration, the switch 21
-1 to the input code input to registers 22-1 to 22-
96 bits of output data D _{21 to} D sequentially shifted by 3
It is possible to output the decoded code D ₁₁ while outputting it as ₂₃ and shifting it according to the cue shift amount information D ₁₂ in the shift circuit 25.

On the other hand, the parallel delimiter code detector 13 shown in FIG. 2 has 31 (that is, the same number as the maximum shift amount M) delimiter code detectors 27-1 to 27-31. These delimiter code detectors 27-1 to 27-31 respectively input 24-bit data having the first bit to the 31st bit of the decoded code D ₁₁ as the leading bits. That is, the delimiter code detector 27-1 inputs the 1st to 24th bits, the delimiter code detector 27-2 inputs the 2nd to 25th bits, and so on. -M inputs the 31st bit to the 54th bit. Then, each delimiter code detector 27-1 to 27-M
Compares the input 24-bit data with "000001H" and outputs the comparison result.

The control circuit 28 controls each delimiter code detector 27.
Input the comparison result from -1 to 27-31. And
If any of these comparison results indicates the detection of the start code, the position of the start code is determined by which delimiter code detector detected the start code. Then, based on this judgment result and the above-mentioned comparison result, the delimiter code detection shift amount information D ₁₂ ″, the control signal D _13, and the shift amount switching signal D ₁₄ are generated.

Next, the operation of the variable length / fixed length decoder 10 of this embodiment will be described in detail with reference to FIG.

First, the operation for detecting the start code will be described.

When the start code is detected, the parallel delimiter code detector 13 first shifts the shift amount switching signal D.
₁₄ is output, and the shift amount switching unit 12 is caused to select the delimiter code detection shift amount D ₁₂ ″. Then, the 64-bit decoded code D ₁₁ is input from the cue shift unit 11 and the first bit to the 31st bit. When each of the above is used as the leading bit, the value of the decoded code D ₁₁ is “000001”.
At the same time, it is determined whether or not it matches "H" (this value is 24 bits in binary). That is, of the 64-bit decoded code D ₁₁ as shown in FIG. 3, the 1st to 24th bits, the 2nd to 25th bits, and the 3rd bit
Bits to 26th bit ... Each of 31st bit to 54th bit is compared with “000001H”.

[0051] Then, if not present the decryption code string matching "000001H", as delimiter detect the shift amount D ₁₂ ", outputs" 31 bits ". Here, this information value “31 bits” is used for the cue shift unit 11
Matches the maximum shift amount of. That is, in the present embodiment, the 31 delimiter codes that can be simultaneously performed by the parallel delimiter code detection section 13 are set in accordance with the maximum shift amount of the cue shift section 11.

This delimiter code detection shift amount D ₁₂ ″ is sent to the cue shift amount information D ₁₂ via the shift amount switching unit 14.
Is input to the cue shift unit 11. As a result, the decoded code D ₁₁ output by the cue shift unit 11 is
As shown in FIG. 3, it is shifted by 31 bits.

Then, as in the case of the first detection, the parallel delimiter code detection unit 13 determines "000001H" in the case where the first bit to the 31st bit of the decoded code D ₁₁ after the shift are set as the leading bits. It is determined whether or not it matches. Hereinafter, the same operation is repeated until "000001H" is detected.

Here, as indicated by in FIG. 3, "00"
When "0001H" is detected, the parallel delimiter code detection device 13 further shifts the code to be decoded D ₁₁ in order to cut out a portion corresponding to "000001H". That is, taking the case shown in FIG. 3 as an example, since the 14th bit to the 37th bit of the decoded code D ₁₁ match “000001H”, the delimiter code detection shift amount D ₁₂ ″ is set. "13 bits" is output. As a result, the decoded code D ₁₁ output by the cue shifter 11 is shifted by 13 bits. In this way, the decoded code D ₁₁ starting from the start code as shown in FIG. 3 can be obtained.

Next, the operation for decoding variable-length / fixed-length codes (that is, the operation for generating run-length codes) will be described.

First, the code decoding unit 12 starts decoding / cutting out a variable length / fixed length code. Here, as described above, the code decoding unit 12 inputs only the lower 32 bits of the code to be decoded D ₁₁ . Therefore, when the code to be decoded D ₁₁ as shown in FIG. 3 is output from the cue shift section 11, the code decoding section 12 should start decoding / cutting out the variable length / fixed length code as it is. You can

Decoding of this variable-length / fixed-length code is performed in the same manner as in the conventional case (see FIG. 10). Then, every time the decoding is performed, the decoding result D _o is output. In addition to this, the pattern length of the decoded variable length code or fixed length code is output as the cue shift amount information D ₁₂ ′. As a result, the cue shift unit 11 causes the cue shift amount information D ₁₂ ′ (that is, cue shift amount information D ₁₂ ).
Is input, the decoded code D ₁₁ to be output is shifted according to the value of the cue shift amount information D ₁₂ . Thereafter, similarly, decoding / cutout of variable-length / fixed-length code is continued. The data string (run-length code) of the decoding result generated in this way is run-length decoded and
It is sent to the scan order converter (described later).

While the variable length / fixed length code is being deciphered / cut out in this manner, the parallel delimiter code detecting section 13 continues to detect the start code. Then, when the start code is detected during the decoding operation of the variable length / fixed length code, the parallel delimiter code detecting section 13 temporarily stops the code decoding section 12 by the control signal D ₁₃ and shift amount switching signal D ₁₄ Shift both switching unit 12
To select the cue shift amount information D ₁₂ ′, and shift the decoded code D ₁₁ to start from the start code.

If a code pattern that does not exist in the variable length code table (see FIG. 10C) or the fixed length code table (not shown) appears during decoding of the variable length / fixed length code, the code The decoding unit 12 determines that some decoding error has occurred, stops the decoding of the variable length / fixed length code by the code decoding unit 12, and detects the next start code. Then, when the next start code is detected, the decoding of the variable length / fixed length code as described above is restarted. Here, in the variable-length / fixed-length decoder 10 of the present embodiment, 32 bits after decoding, the parallel delimiter code detecting unit 13
Since it is stored in, the next start code including the 32 bits can be detected. Therefore,
Even if part of the start code has already been used for erroneous decoding, error recovery can be performed without losing the start code. Therefore, the amount of image data to be discarded when a decoding error occurs can be reduced as compared with the conventional case.

The timing at which the variable length / fixed length decoder 10 outputs the decoding result (run length code) is controlled by a write inhibit signal or the like input from the run length decoding / scan order converter. The details will be described later.

Next, the run-length decoding / scan order converter according to the present embodiment will be described. This run length decoding / scan order converter corresponds to the "buffer memory" of the second invention (claim 2).

FIG. 4 is a block diagram schematically showing the configuration of the run-length decoding / scan order converter 40.

In the figure, the bank memories 41a and 41b in the memory section 41 have a writing area corresponding to 8 × 8 pixels (that is, one block). Then, these write areas are all initialized to zero before data is written.

The write address generating section 42 includes an adder 4
2a and a register 42b. Here, the output of the register 42b is initialized to "0" before writing data. The adder 42a includes a register 42
b and the variable-length / fixed-length decoder 10 (FIG.
Input) and the zero run of the data string (run length code) input from (Ref.). Then, the result of adding this register output and zero run is sent to the memory unit 41 as the write address S _W. As a result, the "level" signal of the run length code can be sequentially written in the corresponding address of either the bank memory 41a or the bank memory 41b (designated by the bank selection signal R _SEL ). Then, as described above, since the addresses other than the address in which the "level" signal is written are initialized to "0", run length decoding can be performed by this writing.

The read address generator 43 comprises a counter 43a and an address converter 43b. Then, the read address S is read from the address converter 43b.
By outputting _R , the data string written in the bank memory 41a or the bank memory 41b (designated by the bank selection signal R _SEL ) can be read while the scan order is converted, and the quantized DCT coefficient ( FIG. 7A) can be obtained. Further, at the time of this reading, by sequentially writing "0" using the above-mentioned read address S _R as the write address S _R ′, initialization for the next write can be performed.

Controller (corresponds to "writing control means" and "reading control means" of the second invention) 44
As described above, the bank select signal R _SEL is used to select the bank memory for writing / reading data. In this embodiment, when the bank selection signal R _SEL is “0”, the writing of the bank memory 41a and the bank memory 41 are performed.
b read is selected, and the bank selection signal R
_{When SEL} is "1", reading of the bank memory 41a and writing of the bank memory 41b are selected. Further, the controller 44 outputs the write inhibit signal W _B to the variable-length / fixed-length decoder 10 in the preceding stage and the write end signal W _END from the variable-length / fixed-length decoder 10 to input the write timing. Control. Furthermore, in addition to this, the inverse quantizer 5 in the subsequent stage
Output of read prohibition signal R _B for 0 and read end signal R _END from the variable length / fixed length decoder 10
The read timing is controlled by inputting.

Next, the operation of the run length decoding / scan order converter 40 according to this embodiment will be described.

FIG. 5 is a state transition diagram for explaining the operation of the run length decoding / scan order converter 40.

First, in the initial state, since nothing is written in the bank memories 41a and 41b, the controller 44 sets the read inhibit signal R _B to "1" (read inhibit state), and the write inhibit signal W _B. "0"
(Writable state). In addition, the bank selection signal R
_SEL is set to “0”, and the bank memory 41 is set for writing.
It is assumed that a is selected.

Here, the variable length / fixed length decoder 1 in the preceding stage
When 0 finishes writing the run length code into the bank memory 41a, the write end signal W _END = 1 is input to the controller 44. As a result, as shown as state A in FIG. 5, the controller 44 sets the read inhibit signal R _B to “0” (readable state) and inverts the bank selection signal R _SEL (“R _SEL = in FIG. 5”). ^
R _SEL "). That is, here, the bank selection signal R _SEL becomes "1" (state in which the bank memory 41a is in the reading state and the bank memory 41b is in the writing state). At this point, nothing is written in the bank memory 41b, so that the write inhibit signal W _B is maintained at “0” (writable state).

Thereafter, the state is changed to the state B, and the write inhibit signal W _B = until the write end signal W _END becomes “1” or the read end signal R _END becomes “1”.
0, read inhibit signal R _B = 0, bank select signal R
A state in which the signal value of _SEL is maintained as it is (“R” in FIG. 5).
_SEL = R _SEL ”).

Here, when the write end signal W _END = 1 is input again in the state A or the state B, both the bank memories 41a and 41b are in the written state, so that the state transits to the state C. The write inhibit signal W _{B is set} to “1” to inhibit the write. At this time, the signal values of the read inhibit signal R _B and the bank selection signal R _SEL are kept at R _B = 0 and R _SEL = R _SEL . This state C is maintained until the read end signal R _END = 1 is input. Then, when the read end signal R _END = 1 is input, the state transits to the above state A.

On the other hand, in the state A or the state B, when the read end signal R _END = 1 is input, both the bank memories 41a and 41b are in a state in which the read cannot be performed, so the state transits to the state D and the read is performed. Prohibition signal R
Reading is prohibited by setting _B to "1". At this time, the write inhibit signal W _B and the bank selection signal R
The signal value of the _SEL is left _{W B = 0, R SEL =} R SEL. This state D is maintained until the write end signal W _END = 1 is input. Then, the write end signal W
_{When END} = 1 is input, the state A is transited to.

FIG. 6 is a timing chart showing the write / read switching timing of the bank memories 41a and 41b (see FIG. 5). As can be seen from FIG. 6, in the present embodiment, when the writing or reading is completed for any of the bank memories 41a and 41b, the writing / reading is switched immediately when the other bank memory is in the writable / readable state. In the case of the conventional run-length decoding / scan order converter, it is possible to switch between writing / reading after waiting until the state becomes writable / readable when writing / reading is not possible. Four
The processing time can be shortened as compared with

In this embodiment, the case where two bank memories are provided has been described, but it goes without saying that three or more bank memories may be provided. If three or more bank memories are provided, the processing time can be further shortened.

[0076]

As described above in detail, according to the present invention, the parallel delimiter code detection unit simultaneously detects delimiter codes for a plurality of leading bit positions, so that the processing time in the decryptor is increased. Can be shortened, and when writing or reading is completed for any of the bank memories, the write / read operation for the bank memory is completed.
Since the reading is switched immediately according to the states of the other bank memories, the processing time in the buffer memory can be shortened.

Therefore, according to the present invention, it is possible to provide an image processing apparatus capable of high speed processing.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a decoder according to an embodiment of the present invention.

2 is a block diagram showing an example of an internal configuration of a cue shift unit and a parallel delimiter code detection unit in the decoder shown in FIG.

FIG. 3 is a diagram for explaining the operation of the decoder shown in FIG.

FIG. 4 is a block diagram schematically showing the configuration of a buffer memory (run length decoding / scan order converter) according to an embodiment of the present invention.

5 is a state transition diagram for explaining the operation of the buffer memory shown in FIG.

6 is a timing chart for explaining the operation of the buffer memory shown in FIG.

7A and 7B are diagrams illustrating scan order conversion and run-length encoding, in which FIG. 7A is a conceptual diagram showing a block made up of pixel data after orthogonal transformation and quantization, and FIG. 2C is a conceptual diagram showing a data string after rearranging and reading the pixel data of FIG. 6C, and FIG. 9C is a conceptual diagram showing a run-length code obtained by converting the data string of FIG.

FIG. 8 is a block diagram schematically showing a configuration example of a conventional image processing apparatus.

9 is a block diagram schematically showing an internal configuration of the variable length / fixed length decoder shown in FIG. 8. FIG.

10A and 10B are diagrams for explaining the operation of the variable-length / fixed-length decoder shown in FIG. 9, where FIG. 10A is a diagram for explaining a decoding operation, and FIG. 10B is a diagram showing a start code. , (C)
FIG. 6 is a diagram showing a variable length code table.

11 is a flow chart for explaining a start code detecting operation of the variable length / fixed length decoder shown in FIG. 9. FIG.

12 is a block diagram schematically showing an internal configuration of the run-length decoding / scan order converter shown in FIG.

13 is a timing chart for explaining the operation of the run-length decoding / scan order converter shown in FIG.

FIG. 14 is a timing chart for explaining an operation of the run-length decoding / scan order converter shown in FIG.

[Explanation of symbols]

 10 variable-length / fixed-length decoder 11 cue shift unit 12 code decoder 13 parallel delimiter code detector 14 shift amount switching unit 21-1 to 21-3 switching unit 22-1 to 22-3 register 23 shift amount accumulation Adder 24 Shift amount cumulative adder 25 Shift circuit 26 Register 27-1 to 27-M Delimiter code detector 28 Control circuit 40 Run length decoding / scan order converter 41 Memory unit 41a, 41b Bank memory 42 Address generating unit 42a Adder 42b register 43 read address generator 43a counter 43b address converter 44 controller

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display area H04N 7/24

Claims (2)

[Claims] 1. An image processing apparatus comprising a decoder for decoding compressed image data having at least a variable length code and a delimiter code, wherein the decoder has the compressed image data and cue shift amount data. By inputting, the cue shift unit for generating the decoded data by shifting the compressed image data according to the cue shift amount data, and cutting out the decoded data fetched from the cue shift unit. , A code decoding unit that generates decoded data, and simultaneously detects the delimiter code from the data to be decoded fetched from the cue shift unit for a plurality of head bit positions, and based on the detection result, the shift amount data An image processing apparatus comprising: a parallel delimiter code detection unit that generates 2. An image processing apparatus having a buffer memory including a plurality of bank memories and a control circuit for controlling reading and writing of the bank memories, wherein the control circuit writes data to any one of the bank memories. At the time of completion, if there is another bank memory that has already been read, the next write is performed to the other bank memory, and if there is no other bank memory that has already been read. After waiting until the reading of one of the bank memories is completed, writing is performed to the bank memory for which the reading has been completed, and write control means for prohibiting writing during the waiting period, There is another bank memory that has already been written when the reading is completed. If the bank memory is already written, the next read is performed in the order of writing to the other bank memory, and if there is no bank memory that has already been written, the writing of one of the bank memories is finished. The image processing apparatus further comprises: a read control unit that causes the bank memory, in which the writing has been completed, to be read after waiting until, and prohibits reading during the waiting period.