JPH07235878A - Variable length decoder - Google Patents

Abstract

PURPOSE:To provide the variable length decoder in which the capacity of a lookup table is made small so as to reduce the hardware scale. CONSTITUTION:A prefix data generating section 17 compares plural bits from a head of a bit string having a prescribed bit number outputted from a barrel shifter 11 with a prescribed pattern and generates a bank address of a small bit number allocated to the prescribed pattern when the both are coincident. The lookup table 14 uses the bank address as a high-order address and uses plural remaining bits resulting from eliminating a prescribed pattern coincident among code bits for a low-order address so as to apply addressing to decoded data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improved variable length decoder, and more particularly to a large number of decoded data stored at a high storage density to reduce the capacity of a lookup table.

[0002]

2. Description of the Related Art Variable-length decoding is highly effective in reducing storage density, and is therefore often used in recent years to reproduce compressed image data using various algorithms. This variable-length decoding is to convert data having a high frequency of occurrence among various types of data into data having a small number of code digits to reduce the total bit generation amount of a large number of data (for example,
See “International Standards for Multimedia Coding”, edited by Hiroshi Yasuda, 1991, etc.).

A conventional variable length decoder will be described below.

FIG. 9 shows a block diagram of a conventional variable length decoder. Reference numeral 31 is a barrel shifter, 32 is a pointer of the barrel shifter, 33 is an external interface for inputting a bit string in which many code codes are continuous from the outside, 34
Is a lookup table, and 35 is a processing device for decoded data. As shown in the figure, the format of the data of the look-up table 34 is composed of the number of bits (code length) of the bit string forming the code and the decoded data.

The bit string input from the external interface 33 is input to the barrel shifter 31. The barrel shifter 31 outputs a bit string of a fixed number of bits (specifically, the code length of the variable-length code code having the maximum code length) from the input bit string. The output bit string becomes an address value of the lookup table 34, and the decoded data (decoded data) stored at the address value is retrieved from the lookup table 34. This decoded data is input to the data processing device 35, and the data processing device 35 performs processing of the decoded data, processing other than the decoded data, and the like. The lookup table 34 also outputs a signal indicating the code length of the code code to be decoded, using the bit string output from the barrel shifter 31 as an address, and this code length signal is added to the pointer 32. . Barrel shifter 31
In response to the instruction from the pointer 32, the bit string is shifted by the code length indicated by the code length signal. As a result, the decoded code code is excluded and the barrel shifter 32
The following code code is located at the beginning of the bit string of a certain number of bits output from the.

[0006]

By the way, in recent years,
It is desired to perform processing of image data and the like at a high frequency to speed up the processing. Therefore, in order to reduce the data read time from the look-up table, it is conceivable to arrange the look-up table in the chip without externally attaching the memory.

However, in the above-mentioned conventional configuration, the hardware scale of the lookup table is large, and therefore the memory becomes large, and it is not possible to arrange the memory in the chip for the purpose of speeding up the processing. was there.

The drawback of the conventional lookup table having a large hardware scale will be described in detail below.

For example, when the maximum code length of the variable length code code is 10 bits, a lookup table having a large capacity of 2 ¹⁰ words is required. However, as shown in FIG. 6, for example, since the barrel shifter always outputs a bit string of a fixed number of bits (for example, 10 bits) and inputs the bit string to the look-up table, a code code “4” is generated. For the code code "0011" and the code code "0011" which is similar to this, a 10-bit address "0010xxxxxxx on the look-up table.
x ”(“ xxxxxx ”is any 6 following“ 0010 ”
In the table area between the bit string of bits) and “0011000000”, it is necessary to store the decoded data for the code code “0010”. Therefore, conventionally, the storage density of a large number of decoded data in the look-up table is low. As a result, when there are many types of variable-length code codes and the code length of variable-length code codes increases,
There is a drawback that the storage capacity of the lookup table is further increased and the hardware scale of the lookup table is increased.

The present invention solves the above-mentioned conventional drawbacks, and an object thereof is to store a large number of decoded data similar to the conventional one while reducing the hardware scale of the look-up table to achieve a small capacity. It is to provide a variable length decoder having a look-up table.

[0011]

To achieve this object, according to the present invention, in each of a large number of variable-length code codes, the bit string forming each code code is divided into a plurality of groups, and the groups are grouped. Corresponding to this, a plurality of bits are converted into a bank address having a small number of bits set in advance, and the look-up table is addressed by this bank address and the remaining portion (other group) of the code code.

That is, a variable length decoder according to a first aspect of the present invention comprises a barrel shifter for shifting a continuous variable length code code by a predetermined bit, a plurality of predetermined patterns having a predetermined code length composed of a plurality of bits, and The number of bits is smaller than the code length of each predetermined pattern and a plurality of bank addresses assigned to each of the predetermined patterns are stored in advance in advance, and the variable length code code output from the barrel shifter is recorded from the beginning thereof. When a plurality of predetermined patterns are compared with each other and both of them match, a prefix data generation unit that generates a bank address of the matching predetermined pattern and a large number of decoded data obtained by decoding a large number of variable length code codes are internally stored in advance. Stores the bank address generated from the prefix data generation unit and the output from the barrel shifter. As an address and a remaining code code other than the predetermined pattern of the variable length code encoding,
And a lookup table for outputting decoded data corresponding to the variable length code output from the barrel shifter.

According to a second aspect of the present invention, the variable length decoder according to the first aspect further comprises a pointer for instructing the barrel shifter a predetermined number of bits to be shifted, and a code length selection circuit. The prefix data generation unit outputs a match signal when the portion from the beginning of the code code up to a predetermined number of bits and the predetermined pattern match, and also outputs a code length signal indicating the code length of the matched predetermined pattern. The look-up table outputs a code length signal obtained by subtracting the code length of the matched predetermined pattern from the code length of the variable length code code to be decoded, and the code length selection circuit is configured to output the prefix data. When the coincidence signal is output from the generator, the code length signal of the prefix data generator is selected and output. During non-output of the coincidence signal,
A code length signal from a lookup table is selected and output, and the pointer receives the code length signal output from the code length selection circuit and outputs a variable length code code for the code length indicated by the code length signal. It is characterized by controlling the barrel shifter so as to shift.

Further, in the invention according to claim 3, in the variable length decoder according to claim 1 or 2, the prefix data generating section stores a plurality of pattern memories for storing each of a plurality of predetermined patterns in advance. From the beginning of the circuit and the variable length code output from the barrel shifter,
Compared with a predetermined pattern of the plurality of pattern storage circuits,
When both match, a match detection circuit that outputs a pattern match signal corresponding to the matched predetermined pattern and each of a plurality of bank addresses are stored in advance, the pattern match signal of the match detection circuit is received, and the received match signal is received. And a bank address output means for outputting a bank address of a pattern corresponding to the pattern matching signal.

In addition, in the invention according to claim 4, in the variable length decoder according to claim 3, the number of match detection circuits is the same as that of a plurality of pattern storage circuits, and each match detection circuit is a barrel shifter. It is characterized in that the variable-length code code outputted from is compared with a predetermined pattern of a corresponding pattern storage circuit.

Further, in the invention of claim 5, in the variable length decoder according to claim 3 or 4, the prefix data generating section receives the pattern matching signal of the matching detecting circuit and receives it. And a code length signal output means for outputting a code length signal of a predetermined pattern corresponding to the pattern matching signal.

Further, in the invention according to claim 6, in the variable length decoder according to claim 3, claim 4 or claim 5, the prefix data generating section outputs the pattern match signal of the match detection circuit. A match signal output inhibit circuit that inhibits each time is provided, and the pattern match signal that has passed through the match signal output inhibit circuit is output to the code length selection circuit, and the pattern match signal before passing through the match signal output inhibit circuit It is output to the bank address output means.

Further, in the invention according to claim 7, in the variable length decoder according to claim 6, the coincidence signal output prohibition circuit is a frequency divider for dividing the clock signal by 2 and a pattern of the coincidence detection circuit. It is characterized by comprising a coincidence signal and an AND circuit having the output of the frequency divider as an input.

In addition, in the variable length decoder according to the present invention, a barrel shifter for shifting the continuous variable length code code by a predetermined bit and a plurality of code codes are grouped into a plurality of groups. A plurality of predetermined patterns of a predetermined code length consisting of a plurality of bits for each group of
A plurality of bank addresses each having a smaller number of bits than the code length of each of the predetermined patterns and allocated for each of the predetermined patterns are stored in advance in advance, and a variable length code code output from the barrel shifter is read from its head. Compared with the plurality of predetermined patterns, when both match, a plurality of prefix data generators that generate bank addresses of the matching predetermined patterns, and a large number of decoded data obtained by decoding a large number of variable-length code The plurality of bank addresses stored in advance inside each of the prefix data generators, and the variable code codes output from the barrel shifter, among the remaining code codes other than the plurality of matched predetermined patterns, are stored. As an address
And a look-up table for outputting decoded data corresponding to the variable length code output from the barrel shifter.

Further, in the invention described in claim 9, the variable length decoder according to claim 8 is provided with a pointer for instructing the barrel shifter a predetermined number of bits to be shifted, and a code length selection circuit. Each prefix data generation unit outputs a match signal when the portion from the beginning of the code code up to a predetermined number of bits and the predetermined pattern match, and also outputs a code length signal indicating the code length of the matched predetermined pattern. The lookup table is based on the code length of the variable length code to be decoded,
The code length selection circuit outputs a code length signal obtained by subtracting the total code length of the code lengths of a plurality of matched predetermined patterns, and the code length selection circuit outputs the prefix signal when the match signal is output from the prefix data generation unit. The code length signal of the data generator is selected and outputted, while the code length signal from the look-up table is selected and outputted when the coincidence signal is not outputted, and the pointer is the code length selection circuit. The barrel shifter is controlled so as to receive the code length signal output from the variable length code and shift the variable length code by the code length indicated by the code length signal.

Further, in the invention of claim 10, in the variable length decoder according to claim 8 or 9, each prefix data generating section stores in advance each of a plurality of predetermined patterns in the same group. The plurality of pattern storage circuits and the variable length code output from the barrel shifter are compared from the beginning with a predetermined pattern of the plurality of pattern storage circuits, and when the two match, they correspond to the matched predetermined pattern. A match detection circuit that outputs a pattern match signal and each of a plurality of bank addresses are stored in advance, and a pattern match signal of the match detection circuit is received,
Bank address output means for outputting a bank address of a pattern corresponding to the received pattern matching signal.

Further, in the invention according to claim 11, in the variable length decoder according to claim 10, the number of match detection circuits of each prefix data generation unit is the same as that of a plurality of pattern storage circuits, and each match detection circuit is provided. The circuit is characterized in that the variable length code output from the barrel shifter is compared with a predetermined pattern of a corresponding pattern storage circuit.

In addition, in the twelfth aspect of the invention, in the variable length decoder according to the tenth or eleventh aspect, each prefix data generating section receives the pattern matching signal of the matching detecting circuit and receives it. And a code length signal output means for outputting a code length signal of a predetermined pattern corresponding to the pattern matching signal.

In addition, according to the invention of claim 13,
13. The variable length decoder according to claim 10, 11 or 12, wherein each prefix data generator outputs the pattern match signal of the match detection circuit a number of times equal to the number of grouped code codes. A match signal output prohibiting circuit that allows the other one and prohibits the other is provided, and the pattern match signal that has passed through the match signal output prohibiting circuit is output to the code length selecting circuit, The pattern matching signal before passing is output to its own bank address output means.

According to a fourteenth aspect of the present invention, in the variable length decoder according to the thirteenth aspect, the coincidence signal output prohibiting circuit of each prefix data generating section sets the clock signal to the number of the prefix data generating sections. It is composed of a frequency divider that divides into an integer multiple by adding 1, and a logical product circuit that receives the pattern matching signal of the coincidence detection circuit and the output of the frequency divider as input. The outputs are characterized in that they deviate from each other by one cycle of the clock signal.

Further, in the invention according to claim 15, in the variable length decoder according to any one of claims 1 to 13 or 14, the lookup table is provided with a barrel shifter and a prefix data generating section. It is characterized in that it is arranged in one chip.

[0027]

With the above construction, in the variable length decoder according to each of the first, third and fourth aspects of the invention, when the barrel shifter outputs a bit string of a certain number of bits, it receives this bit string. The prefix data generation unit compares the received bit string with a plurality of predetermined patterns from the beginning, and when it matches any one of the predetermined patterns, a bank address having a number of bits smaller than the code length of the matching predetermined pattern is given. Output. In the look-up table, the bank address output from the prefix data generation unit and the remaining portion of the bit string output from the barrel shifter other than a plurality of bits replaced with the bank address (that is, a predetermined pattern) are stored. As the address, the corresponding decoded data is retrieved. Therefore, since the lookup table can be addressed with a bit string having a smaller number of bits than the code code, a large amount of decoded data can be stored in a smaller area than before, and the storage density of the decoded data can be increased. The hardware scale can be reduced and a small-capacity lookup table can be adopted.

Furthermore, since the bank address is output by comparing the bit string output from the barrel shifter with a predetermined pattern from the beginning, whether the bit string output from the barrel shifter is "1" or "0" bit by bit from the beginning. As compared with the case where the bank address is output after repeating the determination of, the time required until the bank address is output is shortened, and the addressing time of the decoded data is shortened.

Further, in the variable length decoder according to each of the second, fifth, sixth and seventh aspects of the present invention, as described above, at the time of outputting a bit string of a constant number of bits from the barrel shifter, the head thereof is output. When a plurality of bits from 1 and the predetermined pattern match, the prefix data generating section outputs a bank signal of the matching predetermined pattern and a match signal and a code length signal of the matched predetermined pattern. The code length selection circuit outputs the code length signal from the prefix data generator to the pointer when the coincidence signal is output. The pointer controls the barrel shifter so as to shift the bit string by the code length indicated by the received code length signal, and the barrel shifter shifts the bit string by the code length of the matched predetermined pattern under the control of the pointer.

After that, the barrel shifter again outputs a bit string of a fixed number of bits. Here, at the beginning of the output bit string, the remaining portion of the code code that was output last time except for a plurality of bits that match the predetermined pattern is located. Therefore, the lookup table addresses the decoded data using the bank address output from the prefix data generation unit and the remaining multiple bits output from the barrel shifter as addresses.

Further, claim 8, claim 10 and claim 1
In the variable length decoder according to the first aspect of the present invention, when each code code is grouped into a plurality, a prefix data generator is provided for each group, so that when the barrel shifter outputs a bit string of a certain number of bits. Has
A bank address is output from the prefix data generation unit for each group of code codes included in the bit string. Therefore, in the look-up table, the corresponding decoded data is addressed using each bank address and the remaining portion of the code code excluding a plurality of bits replaced by each bank address as an address. The lookup table can be addressed with a bit string having a smaller number of bits than that, the hardware scale can be further reduced, and a lookup table with a smaller capacity can be adopted.

In addition, claim 9, claim 12, claim 1
3 and the variable length decoder of each invention according to claim 14,
Each time the bank address is output from the prefix data generation unit, the code length selection circuit sends the code length of a predetermined pattern corresponding to the bank address to the pointer, and excludes a plurality of bits in which the parallel shifter matches the predetermined pattern. The beginning of the remaining portion is repeated for each group of code codes. Therefore, the lookup table addresses the decoded data using the bank address output from each prefix data generation unit and the remaining portion of the code code output from the barrel shifter except for the predetermined pattern as an address.

In addition, in the variable length decoder according to the fifteenth aspect of the present invention, since the capacity of the look-up table is reduced, this table can be arranged in the chip where the barrel shifter and the prefix data generator are arranged. So
The wiring length to the look-up table is shortened, the read time of the decoded data from the look-up table is shortened, and the read of the decoded data is speeded up.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 4 shows the overall structure of an image compression / expansion LSI (A). On one chip shown in FIG. 4, 1 ... Four vector pipelines mainly for motion compensation and quantization, and 2 are image compression / expansion LS.
First to control the entire I (A) according to microcode
The control circuits RISCCONT.A and 3 are mainly variable length coding (VL
C) and second control circuit RISCCONT.B for controlling variable length decoding (VLD), 4 is a circuit for performing discrete cosine transform (DCT) and inverse discrete cosine transform (IDCT), and 5 is variable length coding and variable A lookup table for storing codes for long decoding and the like, 6 is a circuit for performing logic operation of variable length coding and variable length decoding, and 7 is a DRAM controller for controlling an external DRAM.

In FIG. 4, the following operation is performed when the image signal is encoded. That is, after the DRAM controller 7 fetches the external image data therein, the four vector pipeline units 1 perform both motion compensation and quantization processing of the fetched image data, and then the DC vector
The T / IDCT circuit 4 outputs the DC of the image data after both the above processes.
T processing is performed. The above operation is performed by the first control circuit RISCCON
Controlled by TA (2). Then, the VLC / VLD logic circuit 6 and the look-up table 5 perform variable length coding on the image data after the DCT processing. The operation of this variable length coding is the second control circuit RISCCO.
Controlled by NT.B (3).

On the other hand, at the time of decoding the encoded image signal, the following operation is performed. That is, after the continuous encoded image signal is captured, the VLC / VLD logic circuit 6 and the look-up table 5 perform variable length decoding on the encoded image data. This variable length decoding operation is controlled by the second control circuit RISCCONT.B (3). Next, after the four vector pipelines 1 perform inverse quantization processing on the decoded image data, and then the DCT / IDCT circuit 4 performs IDCT processing on the image data after the inverse quantization processing. , DRAM
The controller 7 writes the image data after the IDCT processing in the external DRAM. The above three operations are controlled by the first control circuit RISCCONT.A (2).

FIG. 1 shows the image compression / expansion LSI.
A block diagram of a configuration as a variable length decoder for performing variable length decoding in the VLC / VLD logic circuit 6 of (A) is shown.

In the figure, reference numeral 11 designates a barrel shifter for shifting a continuous variable length code code by a predetermined number of bits (for example, 10 bits), and 12 designates a predetermined number of bits for shifting by the barrel shifter, for example, 10 bits. A barrel shifter pointer, 13 is an external interface for inputting a code code from the outside, 14 is a look-up table (hereinafter abbreviated as LUT) in which decoded data and the like are stored in advance, and 15 is a decoding extracted from the LUT 14. A data processing device for processing data.

Next, the characteristic part of the present invention will be described. 16
Is a code length selection circuit, and 17 is a prefix data generator.

The details of the prefix data generator 17 are shown in FIG.

In FIG. 2, 21-0, 21-1 to 21-N
Are pattern storage circuits, respectively. These pattern storage circuits 21-0 to 21-N are different from the code code of this embodiment shown in Table 1 as an example (note that the maximum code length of the code code is 10 bits). Prefix pattern (predetermined pattern) consisting of multiple bits shown in Table 2 below that matches multiple bits from the beginning of the
(In the table, the number N of prefix patterns is N = 7)
Memorize

[0043]

[Table 1]

[Table 2] In Table 1, the code number (type of code) is "1.
5 ”and the maximum code length is“ 10 bits ”. Specifically, in the MPEG2 standard for image processing, the code number is about 390 and the maximum code length is around“ 17 bits ”.

In Table 2, the predetermined patterns have different code lengths from each other. However, in practice, a plurality of predetermined patterns may have the same code length, and thus have the same code length. It is necessary to allocate different bank addresses between a plurality of predetermined patterns.

Further, in Table 1 above, as the code code,
As an example, a code code in which one or more "0" is followed by "1", followed by a 2-bit code "00", "01", "10" or "11" is described above. The prefix pattern in Table 2 is a pattern in which one or a plurality of "0" s and one "1" following the one are grouped together. That is, these code codes are the prefix pattern of Table 2 and the subsequent 2
It is composed of two groups in which bits are classified as other groups. Actual prefix patterns are various patterns in which "0" and "1" are complicatedly combined, as shown in Table 3.

[0046]

[Table 3] In FIG. 2, 20-0 and 20-1 to 20-N are coincidence detection circuits. These match detection circuits 20-0 to 20-N
Compares a bit string of a fixed number of bits output from the barrel shifter 11 of FIG. 1 from its head with the prefix pattern stored in the corresponding pattern storage circuits 21-0 to 21-N, and the two match. Detect whether or not
When matched, the matched prefix pattern k
Pattern matching signal k corresponding to (k = 1, 2, ... Or N)
Has the function of outputting.

Further, in FIG. 2, reference numeral 22 is a prefix pattern bank address selector (bank address output means). This bank address selector 22
Stores, in advance, bank addresses 0 to N (N = 7) assigned corresponding to each prefix pattern 0 to N (N = 7) as shown in Table 2 above. The bank address k of the prefix pattern k corresponding to the pattern matching signal k output from any of 20-0 to 20-N is selected and output. The bank addresses 0 to N have corresponding prefix patterns 0 to N.
The number of bits is set smaller than the code length of. The bank address output from the bank address selector 22 is input to the LUT 14 of FIG.

In addition, 23 is a prefix pattern length selector (code length signal output means). As shown in Table 2, the pattern length selector 23 stores the lengths (code lengths) 0 to N of the prefix patterns 0 to N and the match detection circuit 20.
When the pattern matching signal k is output from any of -0 to 20-N, the matching signal k is received, and the length (code length) k of the prefix pattern k corresponding to the matching signal k is selected, It has a function of outputting a code length signal.

In addition, 24 is the coincidence detection circuit 20-0.
.About.20-N pattern matching signals 0 to N are operated by a logical sum circuit, 25 is a pattern matching signal output prohibiting circuit, and the pattern matching signal output prohibiting circuit 25 passes through the logical sum circuit 24. A frequency divider that inhibits the external output of the pattern matching signal k every one time (every two times), and divides the system clock signal (clock signal) by two as shown in FIG. 25 a, and an AND circuit 25 b to which the output of the frequency divider 25 a and the output of the OR circuit 24 are input.

In FIG. 1, the LUT 14 internally stores in advance a large number of decoded data obtained by decoding a large number of variable length code codes. Decoded data of these is barrel shifter 1
The bank address k from the prefix pattern length selector 23 of the prefix data generation unit 17 and the bank of the code codes output from the barrel shifter 11 so as to output the decoded data corresponding to the code code output from 1 It is stored according to the remaining bits except the prefix pattern k corresponding to the address k. The bank address k from the prefix pattern length selector 23 of the prefix data generator 17 and the bit string from the barrel shifter 11 are input to the LUT 14, and the bank address k in the code code output from the barrel shifter 11 is When the remaining plural bits are input, the decoded data is addressed using these as an address, and as shown in FIG. 1, the code of the plural bits remaining excluding the bit string that matches the prefix pattern in the code code. It has a function of outputting a code length signal indicating the length.

The code length selection circuit 16 shown in FIG.
When the prefix pattern matching signal from the pattern matching signal output prohibiting circuit 25 of the prefix data generating unit 17 is received, the prefix length (code length of the matching prefix pattern k) from the prefix data generating unit 17 is selected. If the prefix pattern matching signal is not output, the code length signal indicating the code length of the remaining plural bits of the code output from the LUT 14 is selected and output.

Next, the operation of the variable length decoder of this embodiment will be described.

The bit string input from the external interface 13 to the barrel shifter 11 is the barrel shifter 11.
A fixed number of bits (10 bits) are output, and the output bit string is input to the prefix data generating unit 17 in FIG.

Now, for example, the output of the barrel shifter 11 is "00101xxxx"("xxxxxx" is "001".
01 ”and an arbitrary 5-bit bit string), the pattern 1 is matched with reference to Table 2. Therefore, the pattern match signal 1 is enabled from the match detection circuit 20-1 and the logical sum circuit is enabled. The pattern matching signal 1 is output via 24 and the pattern matching signal output inhibiting circuit 25.

Simultaneously with the output of the pattern matching signal 1, the prefix pattern length selector 23 outputs the prefix length 3 and the prefix pattern bank address selector 22 outputs the prefix pattern bank address 1.

Since the pattern matching signal 1 is enabled, the code length selection circuit 16 of FIG. 1 selects and outputs the prefix length 3. The outputted prefix length 3 is added to the pointer 12,
With this pointer 12, the barrel shifter 11 shifts the bits by the prefix length 3 from the beginning of the bit string. Therefore, next, at the beginning of the constant bit number (10 bits) bit string output from the barrel shifter 11, the part "01" remaining after removing the prefix pattern "001" from the code code "00101" is located. (That is, from the barrel shifter 11, "01
The bit string of “xxxxxxxxx” is output).

In the LUT 14, the prefix pattern bank address "001" is used as an upper address, and the first two bits "01" of the bit string output from the barrel shifter 11 is used as a lower address to address the decoded data. .

As a result, the LUT 14 outputs the decoded data, and this decoded data is input to the data processing device 15, and the data processing device 15 performs the processing of the image data and the processing other than the image data. .

Therefore, in this embodiment, since the maximum value of the bank address is 7 (that is, 3 bits) and the maximum code length of the code code excluding the prefix pattern is 2 bits, it is possible to perform addressing with a total of 5 bits. .

Output of the barrel shifter 11 "01xx
“Xxxxxxx” matches the pattern number 0 from Table 2, but the logical product circuit 25b of the pattern matching signal output inhibiting circuit 25 shown in FIG. 2 prevents the output of the pattern matching signal 0. As described above, the LUT 14 stores the decoded data obtained by variable-length decoding the code code and the code length of the remaining portion of the code code excluding the prefix pattern. A signal indicating the code length of the remaining portion excluding the prefix pattern is output. The code length selection circuit 16 selects and outputs the code length signal from the LUT 14 because the pattern matching signal is not output from the prefix data generation unit 17.

The code length signal output from the code length selection circuit 16 is supplied to the pointer 12 of the barrel shifter 11.
Is accumulated. As a result, the barrel shifter 11 shifts the first 2 bits of the bit string. Therefore, the next code code following the code code "00101" is located at the head of the bit string output next time by the barrel shifter 11.

As described above, in this embodiment, a part from the beginning of the code code is replaced with a bank address having a shorter number of bits, and this bank address and the remaining part excluding the part of the code code are replaced. The LUT 14 can be addressed as an address. Specifically, when the sign code length is 10 bits in the conventional example, while we needed a lookup table 2 ¹⁰ words as shown in FIG. 6, in this embodiment, by the 5-bit address Since the addressing can be performed, as shown in FIG. 5, the same amount of decoded data as in the conventional case can be stored in a state where the storage density is high, and the LU can be stored.
T can be composed of a small capacity of ²⁵ words and can be arranged on one chip of the image compression / expansion LSI (A).

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.

In the first embodiment, each code code is divided into two or more groups instead of being divided into two groups, and the decoded data is addressed. is there.

That is, the variable length decoder shown in FIG.
1 is different from the variable length decoder of the first embodiment shown in FIG. 1 in that it has a plurality of prefix data generators 17, and other configurations are similar to those of the variable length decoder of FIG. is there.

Each of the plurality of prefix data generators 17-1, 17-2 ... 17-N-1, 17-N shown in FIG. 7 uses the bank address generated by itself as an LU, as shown in FIG.
At the same time as outputting to T14, the prefix length and the prefix matching signal generated by itself are output to the code length selecting circuit 16.

The plurality of prefix data generators 17-1, 17-2 ... 17-N-1, 17-N divide the code code into three groups and use two code codes. When divided into groups, three are provided, and generally,
When the code code is divided into N groups, N-1 pieces are provided.

Each prefix data generator 17-
1, 17-2 ... 17-N-1, 17-N are each provided with a frequency divider (not shown), like the pattern matching signal output inhibiting circuit 25 shown in FIG. 2 of the first embodiment. Have. This frequency divider divides the system clock signal. When the number of prefix data generators is two, the system clock signal is divided by three as shown in FIG. When the number of generating units is three, the system clock signal is divided into four as shown in FIG. 7B, and in general, the number of prefix data generating units is N.
, It has a function of dividing the system clock signal by N + 1.

As can be seen from FIGS. 8 (a) and 8 (b), the outputs of the above frequency dividers are deviated from each other by one cycle of the system clock signal.

The LUT 14 of FIG. 7 receives the bank addresses from all the prefix data generators 17-1 to 17-N, and then receives the bank address for the final period (3 when the system clock signal is divided by 3 by the frequency divider). At the clock, at the 4th clock when the frequency is divided by 4, the bank addresses of these are
A plurality of bits of the code code to be decoded excluding a portion matching each prefix pattern is used as an address, and the decryption data of the code code is output.

Therefore, in this embodiment, since each code code is divided into N (N ≧ 3) groups, the LUT
14, the decoded data can be addressed by N-1 bank addresses and a plurality of bits forming the remaining one group, and the LUT 14 is different from the first embodiment in which the code code is divided into two groups. The circuit scale of can be further reduced.

[0072]

As described above, according to the variable length encoders of the first to seventh aspects of the present invention, when a plurality of bits from the head of the code code match a predetermined pattern, the predetermined code is determined. A bank address having a code length shorter than the code length of the pattern is output from the prefix data generation unit, and the bank address and a plurality of bits remaining in the code code except the matching predetermined pattern are used as an address from the lookup table. Since the corresponding decoded data is addressed, it is possible to store a large amount of decoded data in a small area of the table and increase the storage density of the decoded data while shortening the read time of the decoded data. The look-up table with a small capacity can be adopted by reducing the hardware scale of the look-up table.

According to the variable length encoder of each of the inventions described in claims 8 to 14, a plurality of the prefix data generators are provided, and a plurality of bank addresses and a plurality of coincident code codes are matched. Since the configuration is such that the decoded data is addressed from the lookup table using the remaining bits excluding the predetermined pattern as an address,
The storage density of the decoded data can be made extremely high to effectively reduce the hardware scale of the look-up table, and a look-up table having a smaller capacity can be adopted.

In addition, according to the variable length decoder of the invention as set forth in claim 15, the look-up table having the structure capable of reducing the capacity can be arranged in the chip provided with the barrel shifter and the prefix data generating section. , The length of the wiring to the lookup table can be effectively shortened, the time for reading the decoded data from the lookup table can be shortened, and the speed of reading the decoded data can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a variable length decoder according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a prefix data generation unit of the variable length decoder in the first exemplary embodiment of the present invention.

FIG. 3 is an explanatory diagram of an operation of the frequency divider in the embodiment.

FIG. 4 is a diagram showing an overall configuration of an image compression / expansion LSI.

FIG. 5 is a diagram showing a look-up table in the first embodiment of the present invention.

FIG. 6 is a diagram showing a lookup table in a conventional example.

FIG. 7 is a block diagram of a variable length decoder in the second exemplary embodiment of the present invention.

FIG. 8 is an explanatory diagram of the operation of each frequency divider in the embodiment.

FIG. 9 is a block diagram of a conventional variable length decoder.

[Explanation of symbols]

11 Barrel shifter 12 Barrel shifter pointer 14 Look-up table 16 Code length selection circuit 17 Prefix data generator 20-0 to 20-N Match detection circuit 21-0 to 21-N Pattern storage circuit 22 Prefix pattern bank Address selector (bank Address output means) 23 Prefix pattern length selector (code length signal output means) 25 Pattern match signal output prohibition circuit 25a Frequency divider 25b AND circuit

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Claims (15)

[Claims] 1. A barrel shifter for shifting a continuous variable length code code by a predetermined number of bits, a plurality of predetermined patterns having a predetermined code length composed of a plurality of bits, and a bit number smaller than the code length of each of the predetermined patterns. A plurality of bank addresses assigned to each of the predetermined patterns are stored in advance in advance, the variable length code code output from the barrel shifter is compared with the plurality of predetermined patterns from the beginning, and both match. At this time, a prefix data generator that generates a bank address of the matching predetermined pattern and a large number of decoded data obtained by decoding a large number of variable-length code codes are stored in advance, and the bank address generated from the prefix data generator is stored. And the predetermined pattern of the variable length code output from the barrel shifter. As addresses and codes code outside the remaining variable length decoder, characterized in that a look-up table for outputting decoded data corresponding to the variable length coding code output from the barrel shifter. 2. A pointer for instructing a barrel shifter a predetermined number of bits to be shifted, and a code length selection circuit are provided, and the prefix data generating section includes a portion from a head of the code code to a predetermined number of bits and a predetermined pattern. When the two match, the match signal is output, and the code length signal indicating the code length of the predetermined pattern that matched is output.The lookup table is based on the code length of the variable-length code code to be decoded. The code length signal is output by subtracting the code length of the pattern, and the code length selection circuit selects the code length signal of the prefix data generation unit at the time of outputting a match signal from the prefix data generation unit. While outputting
When the match signal is not output, the code length signal from the look-up table is selected and output, and the pointer receives the code length signal output from the code length selection circuit and indicates the code length signal. 2. The variable length decoder according to claim 1, wherein the barrel shifter is controlled so as to shift the variable length code code by the code length. 3. The prefix data generation unit includes a plurality of pattern storage circuits that store in advance each of a plurality of predetermined patterns, and a variable length code code output from a barrel shifter from the beginning of the plurality of pattern storage circuits. A match detection circuit that outputs a pattern match signal corresponding to the matched predetermined pattern when compared with a predetermined pattern, and a plurality of bank addresses are stored in advance, and the pattern match signal of the match detection circuit is stored. 3. The variable length decoder according to claim 1, further comprising: a bank address output unit that receives and outputs a bank address of a pattern corresponding to the received pattern matching signal. 4. The coincidence detection circuit is provided in the same number as a plurality of pattern storage circuits, and each coincidence detection circuit compares a variable length code code output from a barrel shifter with a predetermined pattern of a corresponding pattern storage circuit. 4. The variable length decoder according to claim 3, wherein 5. The prefix data generator includes a code length signal output means for receiving a pattern match signal of the match detection circuit and outputting a code length signal of a predetermined pattern corresponding to the received pattern match signal. The variable length decoder according to claim 3 or 4. 6. The prefix data generator includes a match signal output prohibition circuit for prohibiting the output of the pattern match signal of the match detection circuit every time, and the pattern match signal passed through the match signal output prohibition circuit has a code length. 6. The variable length decoding according to claim 3, 4 or 5, wherein the pattern match signal output to the selection circuit and before passing through the match signal output prohibition circuit is output to the bank address output means. Chemist. 7. The coincidence signal output inhibiting circuit comprises a frequency divider that divides the clock signal by two, a pattern coincidence signal of the coincidence detection circuit, and a logical product circuit that receives the output of the divider. 7. The variable length decoder according to claim 6, wherein. 8. A barrel shifter for shifting a continuous variable length code code by a predetermined number of bits, and a plurality of code codes each having a predetermined code length of a plurality of bits for each group when a plurality of code codes are grouped into a plurality of groups. A predetermined pattern and a plurality of bank addresses having a smaller number of bits than the code length of each of the predetermined patterns and allocated for each of the predetermined patterns are stored in advance in advance.
A variable length code code output from the barrel shifter is compared with the plurality of predetermined patterns from the beginning, and when the two match, a plurality of prefix data generating units that generate bank addresses of the matching predetermined patterns, A large number of decoded data obtained by decoding a large number of variable length code codes are stored in advance inside, and a plurality of bank addresses generated from each of the prefix data generation units, and a variable length code code output from the barrel shifter, A variable comprising a lookup table for outputting decoded data corresponding to the variable length code output from the barrel shifter, using the remaining code codes other than the plurality of matched predetermined patterns as addresses. Long decoder. 9. A pointer for instructing a barrel shifter of a predetermined number of bits to be shifted, and a code length selection circuit, wherein each prefix data generating section has a predetermined pattern and a portion from the head of the code code to the predetermined number of bits. When and match, the match signal is output, and the code length signal indicating the code length of the matched predetermined pattern is output. The lookup table matches the code length of the variable-length code code to be decoded. A code length signal that is obtained by subtracting the total code length of the code lengths of a plurality of predetermined patterns is output, and the code length selection circuit generates the prefix data when the match signal is output from the prefix data generation unit. While selecting and outputting the code length signal of the part,
When the match signal is not output, the code length signal from the look-up table is selected and output, and the pointer receives the code length signal output from the code length selection circuit and indicates the code length signal. 9. The variable length decoder according to claim 8, wherein the barrel shifter is controlled so as to shift the variable length code code by the code length. 10. Each of the prefix data generators includes a plurality of pattern storage circuits that store in advance each of a plurality of predetermined patterns in the same group, and a plurality of variable length code codes output from a barrel shifter from the top of the plurality of pattern storage circuits. Of the plurality of bank addresses are stored in advance, and a match detection circuit that outputs a pattern match signal corresponding to the matched predetermined pattern is stored in advance. 10. The variable length decoding according to claim 8 or 9, further comprising: a bank address output means for receiving a pattern matching signal of the circuit and outputting a bank address of a pattern corresponding to the received pattern matching signal. Chemist. 11. In each prefix data generation section, the match detection circuits are provided in the same number as the plurality of pattern storage circuits, and each match detection circuit outputs the variable length code output from the barrel shifter to the corresponding pattern storage circuit. 11. The predetermined pattern is compared with a predetermined pattern.
Variable length decoder as described. 12. Each of the prefix data generators comprises code length signal output means for receiving a pattern match signal of the match detection circuit and outputting a code length signal of a predetermined pattern corresponding to the received pattern match signal. The variable length decoder according to claim 10 or 11, characterized in that. 13. The prefix signal generator allows the output of the pattern match signal of the match detection circuit at a rate of once out of the number of times each code code is grouped, and prohibits the others. An output inhibit circuit is provided, the pattern match signal passing through the match signal output inhibit circuit is output to the code length selection circuit, and the pattern match signal before passing through the match signal output inhibit circuit is output to its own bank address output means. The method according to claim 1, wherein
0, the variable length decoder according to claim 11 or claim 12. 14. The match signal output prohibiting circuit of each prefix data generating section divides a clock signal by an integer multiple of 1 by adding the number of prefix data generating sections, and a pattern matching circuit of a match detecting circuit. 14. A signal and a logical product circuit having the output of the frequency divider as an input, and the outputs of the logical products of the respective prefix data generation units are mutually shifted by one cycle of the clock signal. Variable length decoder as described. 15. The variable length decoding according to claim 1, wherein the look-up table is arranged in one chip in which the barrel shifter and the prefix data generator are arranged. vessel.