JP2000209100A - Decoder and decoding method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decode VLC data including a lot of information at high speed. SOLUTION: A short code decoder 2 successively detects all VLCs to which a short code is allocated included in the VLC data inputted from a shift register 1 from a leading bit. A combination circuit 3 for decoding decodes one VLC included in the inputted VLC data and outputs the result and the number of decoded bits. In a judgement circuit 4, in the case that the VLC of the short code is not detected by the short code decoder 2, the decoded result and the number of the bit sent from the combination circuit 3 for decoding are outputted. In the case that one or more VLCs of the short code are detected, the decoded result of the detected VLCs is outputted and the total number of the bits of the one or more VLCs of the short code is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoder for decompressing (decoding) compressed data, and more particularly, to VL.
The present invention relates to a decoder and a decoding method for decoding data compressed according to C (Variable Length Code) coding.

[0002]

2. Description of the Related Art With the development of computerization, there is an increasing demand for storing an enormous amount of data such as image data and transmitting it to a request destination. Usually, such a huge amount of data is
If the data is stored as it is, a shortage of storage capacity occurs, and if the data is transmitted, a problem that the transmission time is increased occurs.

In order to avoid such problems, in recent years, encoding (decoding) for compressing such a huge amount of data when storing or transmitting the data and expanding the compressed data when reproducing the data has been performed. ) Technology is being developed. In particular,
Variable bit length (VLC: Variable) utilizing the fact that the distribution of data values can be changed from the characteristics of natural signals.
Length Code, or Huffman Code) coding is well known.

[0004] In the data encoded by the VLC, the length of data indicating one information, that is, the number of bits differs depending on each information. Therefore, when decoding data in which a number of pieces of information are encoded by VLC, it is necessary to sequentially decode (decode) from the first bit of the data to be decoded.

That is, decoding is performed from the first bit of encoded data, and when one piece of information is decoded, the first bit of data indicating the next information is determined.

Hereinafter, a conventional decoder for decoding data encoded by VLC (hereinafter referred to as VLC data) will be described with reference to FIGS. In the description of the conventional technology, MPEG (Motion Picture Expe
A description will be given of a process of decoding data encoded by VLC for describing a motion vector according to (rts Group) 1.

Here, an example of a VLC code table is shown below.

[0008]

[Table 1]

In the case of this VLC data, 1 bit to 1
A code from decimal -16 to +16 can be represented by a code ink of variable bit length up to 1 bit. In particular, regarding the properties of the image signal handled here, the appearance frequency of a small absolute value centered at 0 is high, and the appearance frequency of a large absolute value is low. Therefore, a VLC having a shorter bit length is assigned to a value near 0, and a VLC having a longer pit length is assigned to a value having a larger absolute value.

The conventional decoder 20, as shown in FIGS. 4 and 5, comprises a shift register 21, a decoding combination circuit 22, and a shift amount designating circuit 23.

The decoder 20 sequentially stores the input VLC data in the shift register 21. The decoding combination circuit 22 receives the first to eleventh bits from the first bit and performs decoding from the first bit in accordance with the combination shown in Table 1. The decoding combinational circuit 22 normally outputs V at one timing (one clock).
One VLC included in the LC data is decoded, and the decoding result and the number of VLC bits used for the decoding are generated.

The decoding combination circuit 22 outputs the decoding result and notifies the shift amount instruction circuit 23 of the number of bits of the decoded VLC. The shift amount instruction circuit 23 notifies the shift register 21 of the notified number of bits as a shift amount. The shift register 21
The VLC data is shifted by the notified shift amount.

Here, assuming that the following VLC data "0101011000001100100000001100010011" has been input to the decoder 20, a process of decoding them will be described.

As described above, in the conventional decoder 20, one VLC data included in VLC data in one clock
Is decoded, and the decoding result and the number of VLC bits used for this decoding are generated.

Therefore, according to the first clock, VL
C “010” is decoded (see FIG. 4). The decoding combination circuit 22 outputs the decoding result “+1” and notifies the shift amount instruction circuit 23 of the shift amount “3 bits”.

In the shift register 21, after the VLC data is shifted by 3 bits, VLC "1" is decoded according to the second clock (see FIG. 5). The decoding combination circuit 22 outputs the decoding result “0” and also outputs the shift amount “1 bit” to the shift amount instruction circuit 2.
Notify 3.

Thereafter, a similar decoding process is performed according to the clock. As a result of such processing, the VLC data “0101011000001100100000001100010011” includes eight VLCs, and it takes eight clocks to decode the entire VLC data.

[0018]

As described above, the conventional decoder can decode only one VLC in response to one clock. Because of this, a lot of information
When decoding VLC data including (VLC), a decoding time corresponding to the number of information included in the VLC data is required, and the time required for the decoding process by the decoder increases.

An object of the present invention is to provide a decoder and a decoding method for decoding VLC data containing a large amount of information at high speed.

[0020]

A decoder according to the present invention comprises: storage means for sequentially storing data including a plurality of encoded codes; and data stored in the storage means.
First decoding means for decoding only one code from the first bit, and second decoding means for decoding a code having a predetermined bit length or less, wherein a predetermined number of bits of data stored in the storage means are inputted from the first bit. , If there is one or less than or equal to the code having the predetermined bit length from the first bit of the input data,
Second decoding means for decoding all the codes from the first bit, and when the second decoding means decodes one or more codes having a predetermined bit length or less, the second decoding means decodes the codes. And outputting a decoded result decoded by the first decoding means when there is no code having a predetermined bit length or less from the first bit of the input data in the second decoding means. Means.

According to this decoder, when codes having a predetermined bit length or less continue from the first bit of data, a plurality of codes are decoded simultaneously by the second decoding means. This makes it possible to decode encoded data including a large amount of information at high speed.

The output means outputs the total number of bits of the decoded code in the output decoding result, and the decoder further outputs the data stored in the storage means by the total number of bits output by the output means. May be provided so as to include a shift unit that deletes from the first bit.

Preferably, the plurality of codes stored in the storage means are VLC.

It is desirable that the predetermined number of bits input by the second decoding means be equal to or less than the longest bit number of the code.

It is preferable that the code having a predetermined bit length or less is a code frequently used in the decoder.

A decoding method according to the present invention is a decoding method for decoding data including a plurality of encoded codes, wherein a first decoding step of decoding the data by one code from the first bit, A second code decoding step of decoding a code having a bit length equal to or less than the predetermined bit length, and when there is one or two or more codes having a predetermined bit length or less from the first bit, the code from the first bit is A second decoding step of decoding all, and, when one or more codes having a predetermined bit length or less are decoded by the second decoding step, a decoding result decoded by the second decoding step is output. , In the second decoding step, the predetermined bit length from the first bit of the data If there is no code below, the first
Outputting a decoding result decoded by the decoding step.

As described above, the decoder and the decoding method according to the present invention can be speeded up with a small amount of hardware by taking advantage of the characteristic of VLC that the higher the appearance frequency is, the smaller the pit length is encoded due to the nature of the signal.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a decoder according to the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing a configuration of the decoder 10.

The decoder 10 comprises a shift register 1, a short code decoder 2, a decoding combination circuit 3, a determination circuit 4, and a shift amount instruction circuit 5.

The shift register 1 stores a VL to be decoded.
The C data is stored sequentially from the first bit. The shift register 1 shifts the stored VLC data according to the shift amount sent from the shift amount instruction circuit 5, and sequentially stores the VLC data if there is subsequent VLC data.

The short code decoder 2 includes a shift register 1
A predetermined amount of bits is input from the first bit stored in the VLC, and the VLC, which is included in the input bit number and is assigned a short code (short number of bits) due to high appearance frequency, This is a circuit that sequentially detects all the signals. The VLC to which a short code is assigned is, for example, a VLC to which 1 to 4 bits are assigned when the longest bit number of the VLC is 11 bits.
However, when the short code decoder 2 detects a plurality of VLCs, the plurality of VLCs need to be all continuous from the first bit.

The short code decoder 2 outputs the detection result to the judgment circuit 4.

Unlike the conventional decoding combination circuit, the short code decoder 2 does not need to be configured to input the same number of bits from the shift register 1 as the longest bit number of the VLC. For example, if the longest bit number of VLC is 1
In the case of 1 bit, the decoding combination circuit 3 described later inputs 11 bits, which is the same bit number as the longest bit number, from the first bit stored in the shift register 1. However, since the short code decoder 2 is a circuit for detecting a VLC to which a short code is assigned because its appearance frequency is high, for example, the short code decoder 2 may input 5 or 6 bits from the head of the shift register. It is composed of However, short code decoder 2
Can be the same as the longest bit number of the VLC. However, in consideration of the overall device configuration of the decoder 10, it is easier to configure the device to input a smaller number of bits than the longest bit number. It is possible and suitable.

The VL detected by the short code decoder 2 is
It is appropriate to set the number of bits (code length) of C according to the amount of VLC data to be processed and the type of VLC to be applied (the shortest bit number and the longest bit number). Further, it is preferable to set the number of bits input from the shift register 1 according to the number of bits of the VLC to be detected.

The decoding combination circuit 3 has the same function as the conventional decoder combination circuit 3 described above. The decoding combinational circuit 3 normally outputs one Vc included in the VLC data at one timing (one clock).
The LC is decoded, and the decoding result and the number of VLC bits used for the decoding are generated.

The judgment circuit 4 inputs the detection result of the short code decoder 2, the decoding result generated by the decoding combination circuit 3, and the number of bits of the decoded VLC. When the detection result sent from the short code decoder 2 indicates that the VLC of the short code is not detected, the determination circuit 4 determines the decoding result sent from the decoding combination circuit 3 and the number of bits of the VLC. And outputs the decoding result and the number of bits to the shift amount instruction circuit 5 as a shift amount bit.

When one or more short code VLCs are detected by the short code decoder 2, the decision circuit 4 outputs a decoding result of the detected VLC and outputs the decoded result.
The total number of bits of VLCs of one or more short codes is output to the shift amount indicating circuit 5 as shift amount bits.

The shift amount instruction circuit 5 outputs the number of bits received from the determination circuit 4 to the shift register 1 as a shift amount bit.

Next, the operation of this embodiment will be described.

First, VLC data is sequentially stored in the shift register 1. VLC stored in shift register 1
Of the data, predetermined bits from the first bit are sent to the short code decoder 2 and the decoding combination circuit 3. In addition to the predetermined number of bits, the number of bits less than the longest code number of the VLC is further transmitted from the shift register 1 to the decoding combination circuit 3.

In the short code decoder 2, the input V
All VLCs included in the LC data (the predetermined number of bits) to which a short code (short number of bits) is assigned because of high appearance frequency are sequentially detected from the first bit.

On the other hand, the decoding combination circuit 3 also decodes one VLC included in the input VLC data, and generates a decoding result and the number of VLC bits used for the decoding.

The detection result of the short code decoder 2, the decoding result and the number of bits generated by the decoding combination circuit 3 are sent to the judgment circuit 4.

In the judgment circuit 4, the short code decoder 2
The detection result sent from the decoding combination circuit 3 indicates that the short code VLC has not been detected, the decoding result sent from the decoding combination circuit 3 is output, and the number of generated bits is determined by the shift amount indicating circuit. 5 is output.

When one or more short code VLCs are detected by the short code decoder 2, the detected VL
The decoding result of C is output, and the total number of bits of the VLC of the one or more short codes is output to the shift amount indicating circuit 5.

The shift amount instruction circuit 5 outputs the number of bits sent from the determination circuit 4 to the shift register 1 as a shift amount bit.

Such an operation is executed according to one operation clock of the decoder 10.

As a result of the operation described above, one or more VLCs are decoded by one operation clock of the decoder 10. That is, a plurality of V
If an LC has been detected, these multiple VLCs will be decoded simultaneously. As mentioned earlier, VLC
In, information with higher appearance frequency is encoded to a shorter pit length due to the nature of the signal. Therefore, the frequency at which a plurality of short code VLCs are simultaneously detected by the short code decoder 2 increases. For this reason, high-speed decoding can be performed as compared with the case where one VLC is decoded by one operation clock as in the related art.

[0049]

Next, an embodiment of a decoder according to the present invention will be described with reference to FIGS. In the description of this embodiment, a decoding process of data encoded by VLC for describing a motion vector according to MPEG (Motion Picture Experts Group) 1 used for compression / expansion of a digital video signal will be described. . VLC
Are the same as those shown in Table 1 above.

Of the components of the decoder 11 in this embodiment, the same components as those of the decoder 10 are denoted by the same reference numerals, and detailed description is omitted.

In the decoder 11, the detection circuit 6 has both the function of the short code decoder 2 shown in FIG. 1 and the function of the decode combination circuit 3, and incorporates the decode combination circuit 3. Below is the detection circuit 6
Will be described below (excluding the decoding combination circuit 3). The VLC data stored in the shift register 1 has the first bit as bit 0 and bits 0 to 11 are connected to the detection circuit 6.

The detection circuit 6a is connected to the bit 0 of the shift register 1 and detects that the bit 0 is "1".

The detection circuit 6b is connected to the bit 1 of the shift register 1 and detects that the bit 1 is "1".

The detection circuit 6c is connected to the bit 2 of the shift register 1 and detects that the bit 2 is "1".

The detection circuit 6d is connected to bit 3 of the shift register 1 and detects that this bit 3 is "1".

The detection circuit 6e is connected to bit 4 of the shift register 1 and detects that this bit 4 is "1". Note that these detection circuits 6a to 6e
If it is considered that the bit n (bits 0 to 4) is 1 as the detection result, the signal of the bit n itself can be used as the detection result.

The detection circuit 6f is connected to bits 0, 1, and 2, and the arrangement of these bits is "010" or "011".
Is a circuit for detecting that The detection circuit 6f
Outputs the last bit (bit 2) as a code output as another output.

The detection circuit 6g is connected to bits 0, 1, and 2, and the arrangement of these bits is "010" or "011".
Is a circuit for detecting that The detection circuit 6g
Outputs the last bit (bit 3) as a code output as another output.

The detection circuit 6h is connected to bits 2, 3 and 4, and the arrangement of these bits is "010" or "011".
Is a circuit for detecting that The detection circuit 6h
Outputs the last bit (bit 4) as a code output as another output.

The detection circuits 6f to 6h are circuits for detecting that the first two bits are "01",
You may comprise so that a bit may be set as a code output.

The detection circuit 6i is connected to bits 0, 1, 2, and 3, and detects that the arrangement of these bits is "0010" or "0011". The detection circuit 6i outputs the last bit as another output (bit 3) as a code output.

The detection circuit 6j is connected to bits 1, 2, 3, and 4, and detects whether the arrangement of these bits is "0010" or "0011". The detection circuit 6j outputs the last bit as another output (bit 4) as a code output.

The detection circuits 6i and 6h may be configured to detect that the first three bits are "001" and to output the next one bit as a code output.

The determination circuit 4 is a circuit for determining a decoding result and a shift amount from various detection results sent from the detection circuit 6. These determination operations are shown in Table 2 below.

[0065]

[Table 2]

In this table, the detection result of the detection circuit 6a is indicated by a ○ when it is true (hit) and ax when it is false (miss hit). In the decoding result, the portion indicated as "±" is the corresponding detection circuit 6f,
6g, 6h, 6i and 6j are determined according to the code output from each detection circuit. Thus, the determination circuit 4 is a circuit that identifies at most 15 states.

The decoding result output circuit 7 receives the decoding result determined by the determining circuit 4 and outputs the result to another component (not shown).

Next, the operation of this embodiment will be described.

Here, it is assumed that the decoder 11 has input "0101101110000011001000000001100010011" as VLC data.

The VLC data is sequentially stored in the shift register 1.

Thereafter, the VL of bit 0 to bit 11
The C data is sent to the detection circuit 6. In the detection circuit 6, according to the first operation clock, the detection circuit 6a
6j perform the detection processing, the decoding result and the shift amount (the number of bits) are obtained by the decoding combination detection circuit 3, and these are sent to the determination circuit.

Here, the detection circuit 6f and the detection circuit 6d
Hits. For this reason, the determination circuit determines the result “+1, 0” obtained by decoding the four bits of the VLC data “0101” with “010” and “1” as the decoded result. Furthermore, the shift amount instructing circuit 4 is notified of the four bits “0101” as the shift amount.

The shift amount instructing circuit 4 includes a shift register 1
Are shifted by 4 bits, and the shift register 1 shifts the VLC data by 4 bits according to this instruction. The decoding result output circuit 7 outputs “+1, 0” as the decoding result.

The above operation is shown in FIG. Thus, two VLCs are simultaneously decoded by one operation clock (first operation clock).

Thereafter, the VLC data of bit 0 to bit 11 is sent to the detection circuit 6 again. In the detection circuit 6, the second operation clock is used as in the case of the first operation clock.
In accordance with the operation clock, the above-described detection circuits 6a to 6j perform detection processing, and the decoding combination detection circuit 3 obtains a decoding result and a shift amount (the number of bits), which are sent to the determination circuit.

Here, the detection circuit 6f and the detection circuit 6d
Hits. For this reason, the determination circuit determines the result “−1, 0” obtained by decoding the four bits of the VLC data “0111” with “011” and “1” as the decoded result. Further, the shift amount instructing circuit 4 is notified of the four bits “0111” as the shift amount.

The shift amount indicating circuit 4 is provided with a shift register 1
Are shifted by 4 bits, and the shift register 1 shifts the VLC data by 4 bits according to this instruction. The decoding result output circuit 7 outputs the decoding result "-1, 0".

The above operation is shown in FIG. As a result, two VLCs are decoded simultaneously by one operation clock (second operation clock).

Thereafter, the same operation is performed from the third operation clock to the third operation clock.
This is repeated until the fifth operation clock.

As a result, although not shown, in the third operation clock, the detection circuits 6a, 6f, and 6i become mishits, and "-16", which is the decoding result of the decoding combination circuit 3, is obtained. At this time, the decoded VLC is one, and the shift amount is 11 bits.

In the fourth operation clock, the detection circuit 6
“a”, “6f” and “6i” are mishits, and “+16”, which is the decoding result of the decoding combination circuit 3, is obtained. At this time, the decoded VLC is one, and the shift amount is 11 bits.

In the fifth operation clock, the detection circuit 6
a, 6j are hit, and the decoding result "0, -2" is obtained. At this time, two VLCs are decoded.

According to the above-described operation, when decoding the VLC data "010110111000001100100000001100010011", the decoding process has conventionally required a time of only eight operation clocks. In this embodiment, the decoding process is completed with five operation clocks. I do.

In particular, in this embodiment, up to five VLCs can be decoded simultaneously, and at least one VL can be decoded.
Decoding processing can be realized with a throughput of C. The speed varies to some extent depending on the characteristics of the information (data) to be applied,
Although there is data dependence, the VLC of the shorter code is set to be more frequent, so that the throughput is greatly improved as compared with the related art.

As described above, according to the present invention, the decoding process can be obviously performed at a higher speed than in the prior art.

In the above-described embodiment, the MPEG (Motion Pict) used for compression / expansion of a digital video signal is used.
ure Experts Group 1), the decoding process of data encoded by VLC for describing a motion vector has been described, but the present invention is not limited to this. That is, MPE
Other VLC used in G1 format, eg DCT
The present invention is applicable to general decoding of VLC used in other formats, such as run-length coding of coefficients.

[0087]

As is apparent from the above description, according to the present invention, it is possible to decode VLC data containing a large amount of information at a high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a decoder according to the present invention.

FIG. 2 is a diagram for explaining an embodiment of a decoder according to the present invention.

FIG. 3 is a diagram for explaining an embodiment of a decoder according to the present invention.

FIG. 4 is a diagram for explaining a conventional decoder.

FIG. 5 is a diagram for explaining a conventional decoder.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register 2 Short code decoder 3 Combination circuit for decoding 4 Judgment circuit 5 Shift amount instruction circuit 6 Detection circuit 7 Decoding result output circuit 10 Decoder 11 Decoder

Claims (6)

[Claims] A storage unit for sequentially storing data including a plurality of encoded codes; and storing data stored in the storage unit as 1 bit from a first bit.
A first decoding means for decoding only one code, and a second decoding means for decoding a code having a predetermined bit length or less, wherein a predetermined number of bits of data stored in the storage means are inputted from a first bit, and A second decoding unit that decodes all the codes from the first bit when there is one or two or more codes having the predetermined bit length or less from the first bit of the data; When one or more codes having the predetermined bit length or less are decoded, a decoding result decoded by the second decoding means is output, and the second decoding means outputs the first bit of the input data. If there is no code shorter than the predetermined bit length, the decoding result decoded by the first decoding means Decoder and an outputting means for outputting. 2. The output means outputs the total number of bits of a code decoded in a decoding result to be output, and the decoder further stores the total number of bits output by the output means in the storage means. 2. The decoder according to claim 1, further comprising a shift means for deleting the data from the first bit. 3. The decoder according to claim 1, wherein the plurality of codes stored in the storage unit are VLC. 4. The decoder according to claim 1, wherein the predetermined number of bits input by the second decoding unit is equal to or less than the longest bit number of the code. 5. The decoder according to claim 1, wherein the code having a predetermined bit length or less is a code frequently used in the decoder. 6. A decoding method for decoding data including a plurality of encoded codes, a first decoding step of decoding the data by one code from a first bit, and decoding a code having a predetermined bit length or less. A second decoding step of decoding all the codes from the first bit if there is one or less than two codes having a predetermined bit length or less from the first bit. When one or more codes having the predetermined bit length or less are decoded by the second decoding step, a decoding result decoded by the second decoding step is output, and in the second decoding step, If there is no code less than the predetermined bit length from the first bit of the data, Outputting a decoding result decoded by the first decoding step.