CN100433157C - Information replying method and device - Google Patents
Information replying method and device Download PDFInfo
- Publication number
- CN100433157C CN100433157C CNB2003101180431A CN200310118043A CN100433157C CN 100433157 C CN100433157 C CN 100433157C CN B2003101180431 A CNB2003101180431 A CN B2003101180431A CN 200310118043 A CN200310118043 A CN 200310118043A CN 100433157 C CN100433157 C CN 100433157C
- Authority
- CN
- China
- Prior art keywords
- continuous length
- restriction
- information
- data
- reply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention relates to an information reply method and a device thereof. The device is used for executing the method which comprises the following steps: A) comparing an input signal with m step reference signals to generate m groups of digital data, with m not smaller than 2; B) performing a logic calculation on the m groups of digital data in a detection range of length w to generate a calculation result; C) synthesizing the calculation result of B) and the m groups of digital data of A) to generate reply information within the limit of a coding continuous length.
Description
Technical field
The present invention relates to a kind of information-reply method and device thereof, particularly relate to a kind of information-reply method and device thereof that is applicable to high data density more and can effectively reduces data error rate.
Background technology
Transmit and data are recorded in one for example on the recording mediums such as disk, CD, magneto-optic disk the time in data, can earlier these data be become another kind of coded data kenel via suitable coding rule modulation usually, so that transmit or record.And for coded data can smoothly and correctly being received and by reading on the recording medium, coded data must meet continuous length restriction (run length limit is called for short RLL).With general dvd system is example, the continuous length restriction (RLL) of coded data need meet (d=2, k=10) restriction, wherein d represents minimum continuous length restriction, k represents the restriction of maximum continuous length, that is when coded data be with NRZI (non-return zeroinverse, non-return-to-zero counter-rotating) when mode is represented, in two-phase ortho position unit " 1 " between bit " 0 " minimum number need have d, can not surpass k at most.And when coded data be when representing in the NRZ mode, then wherein continuous bit " 1 " or " 0 " and number minimumly be required to be d '=d+1, it is individual to surpass k '=k+1 at most.Can guarantee that so, just coded data can be received smoothly and understand.But, when the burning technology of register system improves constantly, and can on discs, carry out more high density recording the time, but cause the amplitude of high-frequency signal to descend, cause signal to noise ratio (snr) to reduce, make continuous length just for the coded data of d or d ' and k or k ' easily because of the low-frequency noise influence changes so that coded data makes a mistake in (reading back) process of deciphering and can't correctly be understood.
With Fig. 1 is example, and under desirable noise-free case, the RLL that supposes the input signal EQRF that represents in the NRZ mode is for (d=1 k=7), when then input signal EQRF is understood according to an a cutting accurate position signal SL1, can produce the digital signal SLRF1 that meets d '=d+1.But as shown in Figure 2, when noise NOISE produced, the amplitude of input signal EQRF was affected by noise and change, so that produced and do not meet the error number signal SLRF2 of d '=d+1, and can't correctly be understood.Therefore, in order to address the above problem, one United States Patent (USP) No. 6111833 " data decodingapparatus " discloses a kind of wrong bit detecting and reaches more correction method, its utilize continuous length be (d '-1), (k '-1), (d-1), (k '+1), (k+1), (d '-2), (d-2), (k '+2) and (k+2) etc. error character (pattern) come the position of wrong bit in the detecting data, and the wrong bit of errors present is corrected.But this patent must use the higher analog/digital converter of a bit number to realize, need pay higher cost, and in addition, this patent also can't detect the bit mistake of d '-1.
Summary of the invention
The object of the present invention is to provide a kind of information-reply method and device thereof that is applicable to high data density more and can effectively reduces data error rate.
So information-reply method of the present invention comprises the following steps: (A): an input signal and m component level standard are compared, to produce m group digital data, wherein m 〉=2.(B): in a reconnaissance range, this m group digital data is carried out logical operation, produce an operation result, (C): from the synthetic return information that produces the continuous length restriction that meets coding of this operation result of (B) and this m group digital data (A).Whereby, reach the effect of effective reduction data error rate.
In addition, the present invention comprises the accurate comparing unit of a multidigit in order to realize the information-reply device of said method, a detecting arithmetic element and a synthesis unit.The accurate comparing unit of this multidigit is in order to compare an input signal respectively, to produce m group digital data, wherein m 〉=2 with m component level standard.This detecting arithmetic element is carried out logical operation to this m group digital data, to produce an operation result in a reconnaissance range.This synthesis unit is synthetic in order to this m group digital data of this operation result that will detect arithmetic element and the accurate comparing unit of this multidigit, meets a return information of the continuous length restriction of coding with generation.Whereby, reach the effect of effective reduction data error rate.
Description of drawings
Be elaborated below by most preferred embodiment and accompanying drawing network equipment and How It Works thereof to plug and play of the present invention, in the accompanying drawing:
Fig. 1 is an example, in order to the deciphering result of signal under desirable noiseless production who is read by dvd system to be described.
Fig. 2 is another example, in order to illustrate that a signal that is read by dvd system is in the deciphering result who has under the noise production.
Fig. 3 is the circuit block diagram of information-reply device of the present invention.
Fig. 4 is first embodiment of information-reply device of the present invention, and it shows the detailed circuit diagram of this information-reply device.
Fig. 5 is the case illustrated of first embodiment, and wherein coordination calibration signal L1～L3 does not produce different data sequence D1～D3.
Fig. 6 is another case illustrated of first embodiment, and wherein coordination calibration signal L1～L3 does not produce the data sequence D1～D3 different with Fig. 5.
Fig. 7 is the another case illustrated of first embodiment, wherein coordination calibration signal L1～L3 generation data sequence D1～D3 different with Fig. 5 and Fig. 6 not.
Fig. 8 illustrates that the accurate L1～L3 in comparison position among first embodiment can be produced according to input signal EQRF by an accurate adjuster 14.
Fig. 9 illustrates that the accurate L1～L3 in comparison position among first embodiment can be produced by an accurate setting apparatus, and this input signal EQRF eliminates the Dc bias composition through a slide-back device earlier, and after suitably adjusting gain through a variable gain amplifier, just import in this detecting computing circuit.
Figure 10 is second embodiment of information-reply device of the present invention, and it shows the detailed circuit diagram of this information-reply device.
Figure 11 is the case illustrated of second embodiment, and wherein coordination calibration signal L1～L3 does not produce different data sequence D1～D3.
Figure 12 is another case illustrated of second embodiment, and wherein coordination calibration signal L1～L3 does not produce the data sequence D1～D3 different with Figure 11.
Figure 13 is the 3rd embodiment of information-reply device of the present invention, and it shows the detailed circuit diagram of this information-reply device.
Seven rank that Figure 14 illustrates the 3rd embodiment relatively accurate L1～L7 in position can be carried out analog/digital conversion to an input signal EQRF who eliminates the Dc bias composition through a slide-back device and produced by one or seven rank analog/digital converters.
Figure 15 is the 4th embodiment of information-reply device of the present invention, and it shows the detailed circuit diagram of this information-reply device.
Figure 16 is the case illustrated of the 4th embodiment, and wherein coordination calibration signal L1～L3 does not produce different data sequence D1～D3.
Embodiment
About aforementioned and other technology contents, characteristics and effect of the present invention, in the following detailed description that cooperates with reference to four graphic embodiment, can clearly understand.In addition, what illustrate earlier is that circuit identical in following all embodiment will use identical label.
At first consulting Fig. 3, is the circuit block diagram in order to the information-reply device 1 of realizing information-reply method of the present invention, and it comprises the accurate comparing unit 11 of a multidigit, a detecting arithmetic element 12 and a data synthesis unit 13.And information-reply device 1 is in order to carry out the following step:
Step (A): as shown in Figure 5 an input signal EQRF and m component level standard are compared, to produce the m group digital data.
Wherein, input signal EQRF one is recorded in the nrz encoding signal on the disc in the high density recording mode, and its RLL is set at (d=1, k=7), that is continuous position " 1 " or " 0 " and number, at least need d '=d+1 to be no more than k '=k+1 at the most, and the first embodiment of the present invention is the data segment that just equals d ' (promptly 2) in order to minimum continuous length among the detecting input signal EQRF, and carries out the correction of coded data according to this d '=2 data segments.
Therefore, as shown in Figure 4, in the first embodiment of the present invention, the accurate comparing unit 11 of multidigit comprises 110, three comparers 111,112,113 that are connected with multidigit calibration signal generator 110 output terminals respectively of a multidigit calibration signal generator.And in the present embodiment, multidigit calibration signal generator 110 is in order to producing three of basic, normal, high grades not coordination calibration signal L 1, L2 and L3, and exports the respectively negative input end of this comparer 111,112,113 respectively to.Simultaneously, input signal EQRF is imported respectively respectively, and the positive input terminal of this comparer 111,112,113 compares to carry out the position standard with this equipotential calibration signal L1, L2, L3, and take a sample respectively according to a sampling clock pulse CLK as shown in Figure 5, and produce three group digital data sequence D 1, D2, D3 import respectively in detecting arithmetic element 12 and the data synthesis unit 13.
Then carry out step (B): in a reconnaissance range, these data sequences D1, D2, D3 are carried out logical operation, to produce an operation result.
As shown in Figure 4, detecting arithmetic element 12 comprises one first circuit for detecting 121 and one second circuit for detecting 122, and it is the data sequence (1 that equals minimum continuous length restriction d ' (=2) in order to detecting
001 and 0
110), its detecting length equals the reconnaissance range of d '+2, wherein first to detect circuit 121 be one by four in succession D type flip-flops in regular turn, be connected the not gate (NOT) of second and third D type flip-flop output terminal and the logical circuit that a Sheffer stroke gate (NAND) is constituted respectively with two, this Sheffer stroke gate has four input ends to be connected with this two non-gate output terminal with first and the 4th D type flip-flop output terminal respectively.And second circuit for detecting 122 is one by four in succession D type flip-flops in regular turn, be connected the not gate of second and third D type flip-flop output terminal and the logical circuit that a rejection gate (NOR) is constituted respectively with two, this rejection gate has four input ends to be connected with this two non-gate output terminal with first and the 4th D type flip-flop output terminal respectively.
As shown in Figure 4, data synthesis unit 13 is that linked to each other by four D type flip-flops and two groups and a door (AND) and or (OR) logical circuit of being constituted.First group link to each other first with door and first or door place between second and third D type flip-flop, second group link to each other second with and second or place between the 3rd and the 4th D type flip-flop.As Fig. 5～shown in Figure 7 and cooperate Fig. 4, detect circuit 122 and detect the data segment that meets d '=2 among the data sequence D3 when second " 0110 " time, i.e. output logic " 1 " to synthesis unit 13 this first and second or door, make output logic " 1 ".Similarly, when first circuit for detecting 121 detects the data segment that meets d '=2 among the data sequence D1 " 1001 " time, i.e. output logic " 0 " to first and second and door of synthesis unit 13, make output logic " 0 ".
Step (C): from the operation result of step (B) and the synthetic answer data that produce the continuous length restriction that meets coding of this m group digital data of step (A).
Therefore, when second circuit for detecting 122 detects the data segment that meets d '=2 among the data sequence D3 " 0110 " time, i.e. output logic " 1 " to first and second or door of synthesis unit 13, make with among the data sequence D2 with the data segment of data sequence D3 " 0
11The position of 0 " second and third correspondence becomes " 1 ", also be about to the data segment of the data sequence D2 of Fig. 5 " and 0
000 ", and the data segment of the D2 data sequence of Fig. 6 and Fig. 7 " 0
100 " become " 0
110 " back output.Whereby, revise the data segment that is not inconsistent minimum continuous length restriction d '=2 among the data sequence D2, make and correctly to be understood by the return information of input signal EQRF decoding output.
In addition, as shown in Figure 8, the position calibration signal L1～L3 in the accurate comparing unit 11 of multidigit can be produced according to input signal EQRF by an accurate adjuster 14.
In addition, as shown in Figure 9, position calibration signal L1 '～L3 ' in the accurate comparing unit 11 of multidigit also can be produced by an accurate setting apparatus 15, but input signal EQRF needs to eliminate the Dc bias composition through a slide-back device 16 earlier, again after a variable gain amplifier 17 gains adjustment, just input respectively compares with this calibration signal L1 '～L3 ' respectively in this comparer 111～113, and to produce digit data sequence D1～D3, wherein the position standard of L2 ' is 0.
Then, consulting shown in Figure 10ly, is second embodiment of information-reply device of the present invention, and different with first embodiment is, this information-reply device 2 except the data segment that can detect d ' (promptly
0110Or
1001), the data segment that more can detect d '-1 is (promptly
0100 or
1011).So, first circuit for detecting 221 of the detecting computing circuit 22 of information-reply device 2 is one by four in succession D type flip-flops in regular turn, with the logical circuit that the not gate that is connected in the 2nd D type flip-flop output terminal and a Sheffer stroke gate are constituted, this Sheffer stroke gate has three input ends to be connected with this non-gate output terminal with first and the 4th D type flip-flop output terminal respectively.And its second circuit for detecting 222 is one by four in succession D type flip-flops in regular turn, with the logical circuit that the not gate that is connected in the 2nd D type flip-flop output terminal and a rejection gate are constituted, this rejection gate has three input ends to be connected with this non-gate output terminal with first and the 4th D type flip-flop output terminal respectively.And 231,232,233,234 and two serial connections of D type flip-flop that 23 of its combiner circuits have comprised four polyphones are located at first and second multiplexer (2 * 1) 235,236 between the second and the 3rd D type flip-flop 232,233, and two serial connections are located at the 3rd and the 4th multiplexer (2 * 1) 237,238 between the 3rd and the 4th D type flip-flop 233,234.And the input end of its first and the 3rd multiplexer 235,237 connects the 2nd D type flip-flop of first circuit for detecting 221 and the output terminal of the 3rd D type flip-flop respectively, with and the output terminal of second and third D type flip-flop 232,233, and the output terminal of the first and the 3rd multiplexer 235,237 is to be subjected to controlling with the door output signal of first circuit for detecting 221; And the input end of its second and the 4th multiplexer 236,238 is to connect the output terminal of its first and the 3rd multiplexer 235,237 and second and third D type flip-flop output terminal of second circuit for detecting 222 respectively, and the output terminal of the second and the 4th multiplexer 236,238 is controlled by the rejection gate of second circuit for detecting 222 respectively.
Therefore, data sequence with Fig. 7 is an example again, when second circuit for detecting 222 detects " 0110 " during data segment, be output logic " 1 " the second and the 4th multiplexer 235,237 of control combiner circuit 23 selects data segment " 0110 " second and third position " 11 " (being the output of second and third D type flip-flop) export in the combiner circuit 23, and will originally import combiner circuit 23 " 0
100 " data segment changes to " 0
110 " data segment output enables to meet minimum continuous length d ' restriction.Then, be example with data sequence D1～D3 of Figure 11 and Figure 12, when the data sequence D2 that enters data synthesis unit 23 occurs " 0
100 " or " 0
000 " data segment, and second circuit for detecting 222 detects data sequence D3 appearance simultaneously " 0
100 " during data segment; its rejection gate is with output logic " 1 " data segment selected data sequence D3 of the second and the 4th multiplexer 236,238 of control combiner circuit 23 " 0100 " second and third position " 10 " (i.e. the output of first and second D type flip-flop of second circuit for detecting 222) export in the combiner circuit 23, and force data segment with data sequence D2 " 0
100 " or " 0
00The position location change of drawing bottom line 0 " is "
10", with output " 0100 " data segment, and this data segment " 0100 " in "
10" will be regarded as a label symbol, it is can be when deciphering identified to be an errors present and further being corrected.
Moreover, as shown in figure 13, be the 3rd embodiment of information-reply device of the present invention, be that with aforementioned two embodiment differences the accurate comparing unit 31 of the multidigit of this information-reply device 3 is to understand input signal EQRF with seven comparison position calibration signal L1～L7.Wherein, last three comparison position calibration signal L1～L3 and input signal EQRF relatively produce three numerical data sequence D 1～D3 through a comparer 311 respectively, import respectively again in its first～the 3rd circuit for detecting 321,322,323 of detecting computing circuit 32 and detect, wherein circuit for detecting 321,322,323 is identical with the circuit for detecting 121 of first embodiment among Fig. 4, then first～the 3rd circuit for detecting 321～323 export to jointly one with the door.Combiner circuit 33 is identical with the combiner circuit 13 of first embodiment among Fig. 4.Following three position calibration signal L5～L6 then relatively produce three data sequence D 5～D6 with input signal EQRF through a comparer 311 respectively, import respectively in the 4th of circuit for detecting 32～the 6th circuit for detecting 324,325,326 again and detect, wherein circuit for detecting 321,322,323 is identical with the circuit for detecting 122 of first embodiment among Fig. 4.Then the 4th～the 6th circuit for detecting 324～326 export to jointly one or the door.
In addition, as shown in figure 14, in aforementioned the 3rd embodiment, data sequence D1～D7 that the accurate comparing unit 31 of multidigit produces also can be by input signal EQRF after a slide-back device 313 be eliminated the Dc bias composition, deliver to one or seven rank analog/digital converters 314 and seven relatively the accurate L1～L7 in position compare, to produce seven numerical data sequence D 1～D7, data sequence D1～D7 is represented in from top to bottom seven lines respectively among Figure 14, and wherein digital signal vertically is seven heat sign indicating numbers (thermal code) of the seven rank analog/digital converters 314 in the corresponding a certain moment.
Then, consult shown in Figure 15, be the 4th embodiment of information-reply method of the present invention and device thereof, it is to equal maximum continuous length restriction k ' in order to detecting (=k+1=8) data segment (1000000001 and 0111111110), first circuit for detecting 421 of the detecting computing circuit 42 of information-reply device 4 and the detecting length of second circuit for detecting 422 equal the reconnaissance range of a position, k '+1.First circuit for detecting 421 needs to use ten D type flip-flops of polyphone mutually, and the output terminal of second～the 9th D type flip-flop is connected to one or door via a not gate.And second circuit for detecting 422 be to use ten mutually the polyphone D type flip-flops, and the output terminal of its second～the 9th D type flip-flop via a not gate be connected to one with the door.Its combiner circuit 43 then comprises the D type flip-flop of ten polyphones, and between first and second D type flip-flop, connect one first with door and first or, and in the end the output terminal of a D type flip-flop connect in regular turn one second with door and second or door, and data sequence D2 (general data) imports a D type flip-flop of combiner circuit 43.
First circuit for detecting 421 or gate output terminal connect respectively combiner circuit 43 first with the door with second with the door input end, and second circuit for detecting 422 with door be connected respectively combiner circuit 43 first or the door and second or input end.Therefore, data sequence D1～D3 with Figure 16 is an example, when second circuit for detecting 422 detects " 1000000001 " during data segment, its with the door be output logic " 1 " and control combiner circuit 43 first or the door and second or the door, force data sequence D2's " 1000000000 " in (be not inconsistent the longest continuous length restriction k '=8) data segment first and the tenth force and change to " 1 " back output, make combiner circuit 43 output data sections " 1000000001 " (being return information) meet the longest continuous length k '=8 restrictions
Similarly, occur when first circuit for detecting 421 detects among the data sequence D1 " 0111111110 " during data segment (the longest continuous length restriction K '=8), itself or goalkeeper's output logic " 0 " control combiner circuit 43 first with door with second with door, with the data segment among the data sequence D2 " X11111111X " (X can be 0 or 1) first and the tenth " X " force change to " 0 ", make the data segment of combiner circuit 43 outputs " 0111111110 " meet the longest continuous length restriction k '=8.
Though the digit data sequence that above-mentioned explanation is represented in the NRZ mode is the example explanation, but above-mentioned explanation also can just can be applied to the digit data sequence that the NRZI mode is represented through simple the modification, detect the data segment that just equals d '=d+1 (NRZ) or d (NRZI) in these data sequences with circuit for detecting then, the data segment of d '-1, and the data segment that just equals k '=k+1 (NRZ) or k (NRZI), and with the bit of appropriate location in these data segments corrigendum general data sequence (position of relative position in (promptly importing the data sequence of combiner circuit), make the general data sequence of combiner circuit output can meet (d, k) restriction, and reach the effect that in higher data recording density system, effectively reduces data error rate.
Claims (18)
1, a kind of information-reply method is characterized in that:
This method comprises the following steps:
(A) incoming coded signal and m component level calibration signal are compared, to produce m group digital data, wherein m 〉=3;
(B) in a reconnaissance range, this m group digital data is carried out logical operation, judge whether each group digital data the continuous length restriction that continuous length just equals to encode takes place, and to produce an operation result, wherein this reconnaissance range is at least+2 of continuous length restrictions; And
(C) the wherein one group of data in this m group digital data that is produced with step (A) are a general data, and the numerical data of utilizing the Rule of judgment meet step (B) the part position of revising this general data in this reconnaissance range, meet a return information of the continuous length restriction of coding with generation.
2, information-reply method as claimed in claim 1, it is characterized in that: the continuous length restriction of coding is a minimum continuous length restriction, and should the restriction of minimum continuous length have the expression mode of NRZ and NRZI, when the expression mode of NRZI is adopted in minimum continuous length restriction, minimum continuous length is restricted to the d restriction, represent to have at least between ' 1 ', 2 adjacent positions d ' 0 ', continuous position, in addition, when the expression mode of NR Z is adopted in minimum continuous length restriction, minimum continuous length is restricted to d '=d+1 restriction, and expression has d ' individual continuous ' 1 ', position or ' 0 ' at least.
3, information-reply method as claimed in claim 2 is characterized in that: this reconnaissance range is at least d '+2.
4, information-reply method as claimed in claim 1, it is characterized in that: the continuous length restriction of coding is a maximum continuous length restriction, and should the restriction of maximum continuous length have the expression mode of NRZ and NRZI, when this maximum continuous length is restricted to the expression mode of NRZI, this maximum continuous length is restricted to the k restriction, represent to have at most between ' 1 ', 2 adjacent positions k ' 0 ', continuous position, and when this maximum continuous length is restricted to the expression mode of NR Z, this maximum continuous length is restricted to k '=k+1 restriction, and expression has k ' individual continuous ' 1 ', position or ' 0 ' at most.
5, information-reply method as claimed in claim 4 is characterized in that: this reconnaissance range is at least k '+2.
6, information-reply method as claimed in claim 1 is characterized in that: the m component level calibration signal of step (A) is a fixed position calibration signal.
7, information-reply method as claimed in claim 1 is characterized in that: the m component level calibration signal of step (A) is an adjustable position calibration signal.
8, information-reply method as claimed in claim 2, it is characterized in that: when the minimum continuous length restriction of coding adopted NRZ to represent mode, the logical operation of step (B) judged whether the data sequence that minimum continuous length is d '-1 takes place in each group digital data.
9, a kind of information-reply device is characterized in that:
This device comprises:
The accurate comparing unit of one multidigit is in order to compare an incoming coded signal respectively, to produce m group digital data, wherein m 〉=3 with m component level calibration signal;
One detecting arithmetic element, in order in a reconnaissance range, this m group digital data is carried out logical operation, judge whether each group digital data the continuous length restriction that continuous length just equals to encode takes place, to produce an operation result, wherein this reconnaissance range is at least+2 of continuous length restrictions; And
One synthesis unit, with the wherein one group of data in this m group digital data of the accurate comparing unit generation of this multidigit is a general data, and utilize the numerical data meet the Rule of judgment of detect arithmetic element to be modified in the part position of this general data in this reconnaissance range, meet the return information that the continuous length of coding limits with generation.
10, information-reply device as claimed in claim 9, it is characterized in that: the continuous length restriction of coding is a minimum continuous length restriction, and should the restriction of minimum continuous length have the expression mode of NRZ and NRZI, when the expression mode of NRZI is adopted in minimum continuous length restriction, minimum continuous length is restricted to the d restriction, represent to have at least between ' 1 ', 2 adjacent positions d ' 0 ', continuous position, in addition, when the expression mode of NR Z is adopted in this minimum continuous length restriction, minimum continuous length is restricted to d '=d+1 restriction, and expression has d ' individual continuous ' 1 ', position or ' 0 ' at least.
11, information-reply device as claimed in claim 10 is characterized in that: this reconnaissance range is at least d '+2.
12, information-reply device as claimed in claim 9 is characterized in that: the accurate comparing unit of this multidigit comprises a multidigit calibration signal generator, and this m component level calibration signal is produced by this multidigit calibration signal generator.
13, information-reply device as claimed in claim 9 is characterized in that: the accurate comparing unit of this multidigit comprises an accurate adjuster, and it produces this m component level calibration signal according to this input signal.
14, information-reply device as claimed in claim 9, it is characterized in that: the accurate comparing unit of this multidigit comprises an accurate setting apparatus, a slide-back device and a variable gain amplifier, this accurate setting apparatus is in order to produce fixing m component level calibration signal, and this input signal compares with this m component level calibration signal respectively after being elder generation's this slide-back device of process and this variable gain amplifier elimination Dc bias composition and the adjustment that gains again.
15, information-reply device as claimed in claim 9 is characterized in that: the accurate comparing unit of this multidigit comprises a m rank analog-digital converter, and this m rank analog-digital converter produces this m group digital data according to this input signal.
16, information-reply device as claimed in claim 9, it is characterized in that: the continuous length restriction of coding is a maximum continuous length restriction, and should the restriction of maximum continuous length have the expression mode of NRZ and NRZI, when this maximum continuous length is restricted to the expression mode of NRZI, this maximum continuous length is restricted to the k restriction, represent to have at most between ' 1 ', 2 adjacent positions k ' 0 ', continuous position, and when this maximum continuous length is restricted to the expression mode of NRZ, this maximum continuous length is restricted to k '=k+1 restriction, and expression has k ' individual continuous ' 1 ', position or ' 0 ' at most.
17, information-reply device as claimed in claim 16 is characterized in that: this reconnaissance range is at least k '+2.
18, information-reply device as claimed in claim 10, it is characterized in that: when the minimum continuous length restriction of coding adopted NRZ to represent mode, the logical operation of this detecting arithmetic element judged whether the data sequence that minimum continuous length is d '-1 takes place in each group digital data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101180431A CN100433157C (en) | 2003-11-24 | 2003-11-24 | Information replying method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101180431A CN100433157C (en) | 2003-11-24 | 2003-11-24 | Information replying method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1622210A CN1622210A (en) | 2005-06-01 |
| CN100433157C true CN100433157C (en) | 2008-11-12 |
Family
ID=34761048
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101180431A Expired - Fee Related CN100433157C (en) | 2003-11-24 | 2003-11-24 | Information replying method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100433157C (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10163880A (en) * | 1996-10-02 | 1998-06-19 | Kawasaki Steel Corp | Data decoder |
| US6111833A (en) * | 1996-02-08 | 2000-08-29 | Sony Corporation | Data decoder |
-
2003
- 2003-11-24 CN CNB2003101180431A patent/CN100433157C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6111833A (en) * | 1996-02-08 | 2000-08-29 | Sony Corporation | Data decoder |
| JPH10163880A (en) * | 1996-10-02 | 1998-06-19 | Kawasaki Steel Corp | Data decoder |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1622210A (en) | 2005-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5430768A (en) | Maximum likelihood detector for a disc drive PRML read channel | |
| US5196849A (en) | Method and apparatus for implementing PRML codes with maximum ones | |
| US7573794B2 (en) | Data defect detection using soft decision result | |
| EP0122027A1 (en) | Variable-length encoding-decoding system | |
| JPH0519332B2 (en) | ||
| US3639900A (en) | Enhanced error detection and correction for data systems | |
| CN1701517B (en) | Decoding device and method | |
| JP2002533974A (en) | Apparatus for encoding an n-bit source word into a corresponding m-bit channel word and decoding the m-bit channel word into a corresponding n-bit source word | |
| US5646966A (en) | Method and apparatus for detecting synchronizing signals by latching successived count values that represent time between received sync pulses for comparison to a predetermined sync pattern of count values | |
| KR860001257B1 (en) | Data reading apparatus for data transmission | |
| CN100483530C (en) | Overall error multiplier optimizing read/write channel | |
| JP3722331B2 (en) | Modulation apparatus and method, and recording medium | |
| JP3935217B2 (en) | Conversion from a sequence of m-bit information words to a modulated signal | |
| US7392463B2 (en) | Data reproducing apparatus avoiding selection of incorrect path | |
| JPH11134819A (en) | Magnetic digital recording and reproducing device | |
| US7330137B2 (en) | Method and apparatus for RLL code encoding and decoding | |
| CN100433157C (en) | Information replying method and device | |
| JP2003123400A (en) | Data recording device, data reproducing device and data recording and reproducing device | |
| US6172622B1 (en) | Demodulating device, demodulating method and supply medium | |
| US6393598B1 (en) | Branch metric compensation for digital sequence detection | |
| USRE38719E1 (en) | Adjust bit determining circuit | |
| US7006019B2 (en) | Rate-7/8 maximum transition run code encoding and decoding method and apparatus | |
| JPH0233770A (en) | Decoding method | |
| JP2001217716A (en) | Efficient analog/digital converter for digital system and method therefor | |
| US5367535A (en) | Method and circuit for regenerating a binary bit stream from a ternary signal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160525 Address after: Hefei City, Anhui province 230000 Wangjiang Road No. 800 building 10 layer A3 Innovation Industrial Park Patentee after: Smart technology (Hefei) Co., Ltd. Address before: Taiwan, China Patentee before: MediaTek.Inc |
|
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Hefei City, Anhui province 230000 Wangjiang Road No. 800 building 10 layer A3 Innovation Industrial Park Patentee after: Hefei Jie FA Technology Co., Ltd. Address before: Hefei City, Anhui province 230000 Wangjiang Road No. 800 building 10 layer A3 Innovation Industrial Park Patentee before: Smart technology (Hefei) Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20081112 Termination date: 20201124 |