JPH02184172A - Bit plane encoding system - Google Patents

Abstract

PURPOSE:To reduce picture quality deterioration when the encoding is interrupted on its way without using much encoded bit number on the high order bit plane by encoding bipolar code data together with zero run length as to only a data which is first in non-null on the bit plane encoded from the high- order bit plane. CONSTITUTION:The amplitude information is classified into bit information of data having one non-null bit or over in the high-order digit as to each encoded bit plane from the most significant bit and bit information of a data whose high-order bit data is all null. Then as to the bit data of null, the data is encoded by using information of number of zeros up to a non-null bit and bipolar information and as to bit information of the non-null bit data, the bit data itself is encoded and the information having larger absolute value is encoded. Then the information is reproduced in a hierarchical way and even if the information is missing due to a limit in the total coded bit number, the deterioration in the picture quality is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for efficiently encoding quantized image data in a hierarchical manner starting from visually important upper bits.

(Prior art) Conventionally, differential bit-plane encoding (IEICE Technical Report IE8) has been used as a bit-plane encoding method for image information distributed in positive and negative directions.
0-9) are known.

This method expresses the difference information between adjacent pixels using a special binary code, and performs run-length encoding of the binary information for each bit plane starting from the upper bit.

(Problem to be Solved by the Invention) However, the most significant bit of the binary code used here is mostly positive/negative information, and before encoding the visually important difference information with large amplitude values, Too many bits were wasted on information that had little effect on understanding the whole picture. Understanding the entire image required information from many more bit planes, which was extremely time consuming.

Furthermore, in systems where the total number of encoded bits is limited by memory capacity or the like, this conventional method has the problem that encoding ends before visually important information can be encoded.

The present invention has been made in view of the above circumstances, and its purpose is to minimize the deterioration of image quality even when information is missing in a system that can perform hierarchical reproduction and where the total number of encoded bits is limited. The object of the present invention is to provide a bit-plane encoding method that can reduce the number of bit planes to a minimum.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention separates image information distributed in positive and negative directions into positive and negative information and amplitude information represented by a natural binary code, and starts from the most significant bit of the amplitude information. For each encoded bit plane, bit information of data in which there is one or more non-zero bits higher than the encoded bit plane, and bit information of data in which all bit data higher than the encoded bit plane are zero. For bit data in which all bit data higher than the encoding bit plane are zero, the information on the number of zeros up to non-zero bits and the sign information of the data are encoded. For bit information of data in which at least one non-zero bit exists in bit data higher than the bit plane, it is possible to encode bit information with a large absolute value by encoding only the number of consecutive pieces of the same binary information or the bit data itself. This is a bit-plane encoding method that encodes information.

Furthermore, in order to achieve the above object, the present invention stores information on the number of non-zero coefficients for each block when performing bit-plane encoding of an AC component of cosine-transformed coefficients with a certain block size, In the encoded bit plane, blocks are classified into blocks in which there is one or more non-zero coefficients and blocks in which there is no non-zero coefficient at all.

Then, in the next encoded bit plane, encoding starts from a block that already has one or more coefficients that are non-zero, and for blocks that do not have a coefficient that is non-zero in the encoded bit plane, A bit plane that detects and encodes the consecutive number of blocks that do not have non-zero coefficients, excluding encoded blocks, in a predetermined order, and then encodes blocks that have non-zero coefficients. Coding method Furthermore, in order to achieve the above object, the present invention quantizes and codes the DC components of coefficients cosine-transformed with a certain block size for all blocks, and calculates the difference between the quantized DC components and adjacent blocks. The sum of absolute values is calculated for each block, and the AC components are coded in the order of the blocks with the largest sum of absolute values.

(Operation) Since non-zero bit data exists on the L-order bit plane when amplitude data has a large absolute value, information with a large absolute value is encoded first by bit plane encoding.

Further, since the plus/minus sign is encoded only for data that becomes non-zero for the first time on the encoded bit plane, the plus/minus sign of data with small amplitude is encoded on the lower bit plane. Furthermore, by separating the bit information of data in which non-zero bits exist in bit data higher than the encoded bit plane, and the bit information of data in which all bit data higher than the encoded bit plane are zero, the run length can be reduced. By encoding, the data is classified into parts where the data compression rate cannot be increased and parts where the data compression rate can be increased, and the optimal encoding can be performed for each.

Also, when performing bit plane encoding of the AC component of coefficients that have been cosine transformed and quantized with a certain block size, the presence or absence of non-zero coefficients in the encoded bit plane is stored for each block. By doing so, in the next encoding bit plane, information on the order of the blocks to be encoded is not encoded, and for blocks where non-zero coefficients exist, block address information is also not encoded. Only blocks that can be encoded and have a coefficient that becomes non-zero for the first time on the encoded bit plane need to be encoded with the address information of the block. As this address information, information about the number of consecutive blocks in which all bit data above the encoded bit plane is zero, excluding blocks that have been encoded on the encoded bit plane, is encoded.

Furthermore, in the AC components of coefficients cosine-transformed with a certain block size, there is a high possibility that data with large absolute values will exist in blocks where the sum of the absolute values of the differences in DC components with adjacent blocks is large. , quantize and encode the DC components of the cosine-transformed coefficients for all blocks, calculate the sum of absolute values of the differences between the quantized DC components and adjacent blocks for each block, and calculate the sum of absolute values. By performing bit-plane encoding of the AC component in order from the largest block, the blocks in which non-zero bits are encoded become consecutive, and the address information of the block to be encoded can be encoded with a code with a small number of bits. be.

(Example) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

Image data is input in blocks from an input terminal 40, and this input image data becomes discrete cosine transform (DCT) coefficient data 41 via a discrete cosine transformer 1. This coefficient data 41 becomes amplitude data via the absolute value conversion circuit 2. Furthermore, this amplitude data is stored in the buffer memory 4 as quantized data 41b via the quantizer 3. Further, the buffer memory 4 stores positive/negative sign data 41a and quantized data 41b of the coefficient data 41.

During encoding, one block of data is read out twice from the buffer memory 4, and among the output data 42 of the buffer memory 4, the positive and negative sign data 42a are
The quantized data 42b is input as is to the multiplexer 7C, and is input to the zero run counter 7a of the corresponding bit plane and the upper bit non-zero detector 5 used for the lower bit plane.

The upper bit non-zero detector 5 (58 to 5c) is for checking the presence or absence of non-zero data in the upper bit. In this example, the upper bit non-zero detector 5a is configured to output the input data as is. Also, the upper bit non-zero detector 5
b and 5c can be constructed by two-man OR circuits.

On the other hand, input terminal 43 receives data indicating whether one block of data is being read out from buffer memory 4 for the first time or for the second time.

During the first reading from the memory 4, the zero run counter 7a continuously counts zeros only where there is a non-zero in the upper bits, and when a non-zero is detected, this number of zeros is encoded by the code table 7b, It is output from multiplexer 7c. However, at this time, since the upper bit of the zero run counter 7al corresponds to zero, the zero run counter 7al
al does not operate and the multiplexer 7cI does not output encoded data. And 2 from buffer memory 4
In the second reading, the number of zeros is counted continuously only where the upper bit is zero, and when a non-zero is detected, this number is encoded using the code table 7b, and this encoded data and this plus/minus sign data 42a are successively added. multiplexer 7
Output from c.

An example of encoding at this time will be shown using actual data. FIG. 2 shows actual quantized data and the encoding order at that time, and only the data with circled numbers in FIG. 2(b) are encoded with positive and negative signs. Then, the encoded data at this time has a zero run length
If the encoded data is ZX, the positive sign data is So, and the negative sign data is E, the encoded data when the remaining data in the 81st block is all zero, the result will be as shown in FIG. ZX enclosed in parentheses in FIG. 3 is coded data of zero run length when the coded data E mentioned above is not used. Here, even if the zero run length for the square number data shown in FIG. 2(b) is encoded bit-pi-bit, the encoding efficiency hardly deteriorates.

FIG. 4 shows another example of encoding using this method. This is the case when each bit plane is encoded in the same order as the most significant bit plane.

FIG. 5 shows an encoding example in which the plus and minus signs are also run-length encoded. Here, Zx is the length of the zero run
In the run length code, 0x indicates the run length code of the length of one run. In addition, since there are cases where only the first zero run code of each block is zero, encoding efficiency is improved by separating the first zero run code of each block from the second and subsequent zero run codes. can.

FIG. 6 shows an example in which the hardware scale is smaller than that of the embodiment shown in FIG. Here, the bit plane selection circuit 6 sequentially selects and encodes encoding bit planes from the upper bit plane to the lower bit plane according to data inputted from the input terminal 44. Therefore, only one zero run counter 7h, one code table 7b, and one multiplexer 7c are required.
The number of times data is read from the memory 4 increases by the number of bit planes.

FIG. 7 shows an example of a decoding method for the encoding methods shown in FIGS. 1 and 2. Again, from the buffer memory 4, one block of data is stored for each decoded bit plane.
The data is read out in succession from the terminal 43 for each decoded bit plane, indicating whether this one block of data is being read out for the first time or the second time. Data indicating whether the data is for data whose upper bits are all zero is input. Further, from the terminal 44, data for sequentially selecting the bit plane to be decoded from the upper bits to the lower bits is input. The variable length code data is inputted to the terminal 45 after being divided by a certain number of bits.

The demultiplexer 37 connects the divided variable length code data and outputs it to the decoding table 38. Then, the decoding table 38 outputs the code length of the input variable length code data to the demultiplexer 37.

When encoded data for data with non-zero bits in the upper bits is input, the demultiplexer 37 shifts the lower data by the number of bits of this code length to the upper bits as the next manual data. input into the decoding table 38;

Then, when encoded data for data whose upper bits are all zero is input, the data with 1 bit more than the number of bits of this code length shifted to the upper bits is decoded as the next input data. table 3
8 and the bit data immediately above the most significant bit that is input to the decoding table (plus/minus sign data)
is output to the selector 34.

The decoding table 38 converts the variable length code data manually input by the demultiplexer 37 into zero run length data and outputs the data to the zero run generator 39 .

The zero run generator 39 sets a down counter equal to the number of zero run lengths inputted from the decoding table 38, and decrements the data of this down counter by 1 each time one bit of zero data is output, until this counter reaches zero. Outputs non-zero data when . However, the down counter used in this zero run generator 39 has non-zero bits in its upper bits when one block of data is read from the buffer memory 4 for the first time for each decoded bit plane. It operates only on data, and when reading one block of data from the buffer memory 4 for the second time, it operates only on data whose upper bits do not have non-zero data. In this way, the zero run generator 39 outputs non-zero bit data to the selector 34 and the selector 35 only where it becomes non-zero bit data.

When the data to be decoded has no non-zero bits in its upper bits (that is, when reading one block of data from the buffer memory 4 for each decoding bit plane for the second time), and When new non-zero/soto data is input from the zero run generator 39, the plus/minus sign data input from the demultiplexer 37 is output to the buffer memory 4; otherwise, the plus/minus sign data from the buffer memory 4 is buffered as is. Return to memory 4.

The selector 35 is manually operated by the bit plane selector 6 for data whose upper bits have non-zero bit data when one block of data is read out from the bus sofa memory 4 for each decoded bit plane for the second time. Bit data from the buffer memory 4 is output to the bit plane selector 36, and otherwise data from the three zero run generators is output to the bit plane selector 36.

The bit plane selector 36 inputs the data input from the selector 35 to the same bit position of the buffer memory 4 selected by the bit plane selector 6, and inputs the data from the buffer memory 4 to bits higher than this bit position. As is, zero data is outputted to the lower bits from this bit position and stored in the buffer memory 4.

In this way, the decoded absolute value data in the buffer memory 4 is restored to a representative value by the inverse quantizer 33 and input to the complementer 32 .

The complementer 32 outputs the positive and negative sign data from the buffer memory 4 and the amplitude data from the inverse quantizer 33 to the inverse discrete cosine transformer 31 as positive and negative data. The image data is then reproduced by the inverse discrete cosine transformer 31.

Further, as another embodiment of the present invention, a case will be shown in which the run-length encoder 7 shown in FIG. 6 is configured as shown in FIG. 8.

Here, when the upper bit zero block detector 7d detects that there is no non-zero bit data in the bits above the encoded bit plane of the block reading data from the buffer memory 4, the upper bit zero block detector 7d detects the zero run counter 7f and Zero data is output to the multiplexer 7h, and when it is detected that there is one or more non-zero bit data, the non-zero data is output.

The zero block detector 7e outputs zero data to the zero run counter 7f and the multiplexer 7h when it detects that there is no non-zero data in bits above the encoded bit plane of the block reading data from the buffer memory 4. do.

The zero run counter 7f receives zero data from the zero block detector 7e every time one block of data is read twice for each encoded bit plane, except when non-zero data is input from the upper bit zero block detector 7d. The number of consecutive inputs is counted and the data of these consecutive numbers is output to the code table 7g.

The code table 7g encodes this number and outputs it to the multiplexer 7h.

The multiplexer 7h then connects the zero block detector 7e.
When zero data is input from , Gobo encoded data is not output on the encoded bit plane for the input block, and zero data is input from the upper bit zero block detector 7d and the zero block detector When non-zero data is manually input from code table 7e, the encoded data input from code table 7g is output before outputting the encoded data for the first non-zero bit data of the block.

FIG. 9 shows an example in which the quantized data of FIG. 2 is encoded using this encoding method. Here, BX indicates that there are X consecutive blocks with no non-zero bit data above the encoded bit plane, and is encoded data output from the code table 7g.

FIG. 10 shows another embodiment of the invention.

Here, among the cosine transform coefficients quantized by the quantizer 3, the DC component is converted into difference data with the DC component of the previous block by the differential PCM calculator 10, and encoded by the variable length encoder 11. and input to the multiplexer 12. The alternating current component of the data output from the quantizer 3 is input to the most significant bit detector 8 and is stored in the buffer memory 4.

The most significant bit detector 8 detects the most significant bit plane in which non-zero bit data exists in one screen, and when the encoding of the DC component is completed, the position information of this most significant bit plane is sent to the multiplexer 12, the bit plane. It is output to the plane controller 9 and address controller 13.

Using the position information of the most significant bit plane, the bit plane controller 9 first selects the most significant bit plane in which non-zero bit data exists in the AC component, and sequentially selects the most significant bit plane in which - bit planes are encoded. Data is output to the bit plane selector 6 so as to select the lower bit plane.

The address controller 13 determines the maximum number of times bit plane encoding is repeated based on the position information of the most significant bit plane. Further, this address controller 13 is -
One block of data is encoded in two bit planes.
The address of the buffer memory 4 is controlled so that data is read out once at a time, and data indicating whether this one block of data is being read out for each encoded bit plane is outputted to the run length encoder 7 for the first or second time.

The run-length encoder 7 performs bit-plane encoding of the AC component as described in the first invention, and outputs encoded data to the multiplexer 12. The multiplexer 12 sequentially connects the input variable length codes, divides them into fixed bit lengths, and outputs them. As a result, the upper bit plane without non-zero bit data is encoded using only the starting bit plane information, increasing the encoding efficiency.

FIG. 11 is a configuration diagram showing another embodiment of the present invention.

In the figure, a non-zero block detector 14 is a block reading data from the buffer memory 4, and if there is one or more non-zero data above the encoded bit plane, it outputs non-zero data.

The address controller 13 stores the data output from the non-zero block detector 14 at the address of the buffer memory 15 corresponding to the block from which data is being read from the buffer memory 4. But buffer memory 4
When data is being stored in the buffer memory 15, that is, when DPCM encoding is being performed, all data in the buffer memory 15 is set to zero.

Then, for each encoded bit plane, the address controller 13 first reads only the block corresponding to the address where non-zero data is stored in the buffer memory 15 from the buffer memory 4 and performs bit plane encoding. Next, the data in the sentence buffer memory 15 is transferred to the inverter 16.
Then, only the block corresponding to the address which is non-zero data is read out from the buffer memory 4 and subjected to bit plane encoding.

FIG. 12 is a configuration diagram of still another embodiment of the present invention.

Here, the differential PCM calculator 10 is a variable length encoder 1
1, the difference value between the quantized value of the DC component and the quantized value of the DC component of the previous block is output to the variable length encoder 11 as output data 51, and the difference value between the quantized value of the DC component of the previous block is outputted to the variable length encoder 11, and the difference value between the quantized value of the DC component of the previous block is outputted to the variable length encoder 11, and the difference value is The sum of the absolute values of the differences in DC components between the block adjacent above and the blocks adjacent above, below, left and right is output to the changeover switch 19 as data 52.

The block circuit diagram of the differential PCM calculator 10 in this case is as follows:
It will look like Figure 13. However, here, in order not to require a large number of bits for later processing, the maximum value limiter 1
0f! Then, a limit is placed so that the sum of absolute values does not exceed a certain value before outputting.

Every time the address controller 13 performs DPCM encoding of the DC component, the address controller 13 transfers the data output from the differential PCM calculator 10 to the buffer memory 21 through the changeover switch 19.
Let me remember it.

When the DPCM encoding is completed, the ordering unit 22 stores the data in the buffer memory 21 in the address memory 23 in order of block address data starting from the largest value, and also sets all the data in the buffer memory 21 to zero.

The address controller 13 reads each encoded bit plane in the order in which it is stored in the address memory 23, and reads the data of the block corresponding to the address data from the buffer memory 4 and encodes it.

Also, in each encoded bit plane, the address controller 1
3 stores the output data from the non-zero block detector 14 via the changeover switch 19 at an address corresponding to the encoded block. Further, in each encoded bit plane, the address controller 13 detects non-zero data in the buffer memory 21 in the order stored in the address memory 23, and encodes the block corresponding to the address, The second time, zero data in the buffer memory 21 is detected in the order stored in the address memory 23, and the block corresponding to that address is encoded.

This allows blocks with a high probability of having non-zero bit data to be contiguous in each encoded bit plane,
Since short encoded data can be used as address information for a block that encodes non-zero bit data, the number of encoded bits is reduced. In addition, when there are few bits to be encoded, the blocks with a high possibility of block distortion are encoded first, so even if encoding is stopped midway, image quality deterioration due to block distortion can be further reduced. .

FIG. 14 is a configuration diagram showing still another embodiment of the present invention.

Here, the second quantizer 24 quantizes only the DC component with a larger quantization value than the quantizer 3.

The second inverse quantizer 25 expands the value quantized by the second quantizer 24 so that it has approximately the same size as when it was quantized by the quantizer 3.

The gate circuit 26 transfers this expanded data to the quantizer 3.
It outputs data to the subtracter 27 only when DC component data is output from the quantizer 3, and zero data is output when an AC component is output from the quantizer 3. Then, the subtracter 27 outputs the quantization error between the quantizer 24 and the quantizer 3 for the DC component, and outputs the output data of the quantizer 3 as is for the AC component.

The absolute value converter 28 converts the output data of the subtracter 27 into an absolute value, and the OR circuit 29 ORs the positive/negative sign from the discrete cosine transformer 1 and the positive/negative sign from the subtracter 27 and outputs the result.

That is, the positive and negative signs from the subtracter 27 are output for DC components, and the positive and negative signs from the discrete cosine transformer 1 are output for AC components. The output data of the absolute value encoder 28 and the two OR circuits is stored in the buffer memory 4 for one screen, and after the DPCM encoding is completed, this data is encoded by the bit plane encoder 30.

According to this, any image can be encoded without using a particularly large number of gradations for the DC component, and images with small changes can be encoded without reducing the number of gradations for the DC component.

〔Effect of the invention〕

As explained above, according to the present invention, data distributed in positive and negative directions is converted into absolute values and encoded from the upper bit plane, and the positive and negative sign data is set to zero only for data that becomes non-zero for the first time on the bit plane to be encoded. By encoding with the run length of , it is possible to reduce image quality deterioration without using a large number of encoding bits on the upper bit plane, and even if encoding is aborted midway.

Furthermore, for blocks containing non-zero data, it is not necessary to encode the address information of the block, thereby improving the encoding efficiency.

Furthermore, a block with a large difference in DC component from surrounding blocks is likely to have non-zero bit data on the upper bit plane, so by performing bit plane encoding from a block with a large difference in DC component, Blocks containing non-zero bit data are sequentially encoded, which has the effect of suppressing the use of long encoding codes for block address information.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of claim (1) of the present invention,
FIG. 2 is an explanatory diagram showing an example of quantized data and an example of the encoding order in the same embodiment, FIGS. 3 to 5 are explanatory diagrams showing an example of encoding in the same embodiment, and FIG. FIG. 7 is a block diagram showing an example of the decoding method applied to the embodiment shown in FIG. 1 or FIG. 6, and FIG. 8 is a block diagram showing an example of the decoding method applied to the embodiment shown in FIG. FIG. 9 is an explanatory diagram showing an encoding example of the embodiment. FIGS. 10 to 12 are block diagrams showing still other embodiments of the present invention. FIG.
FIG. 2 is a block diagram of a differential PCM calculator applied to the embodiment of claim (3) of the present invention, and FIG. 14 is a block diagram showing still another embodiment of the present invention. 1... Orthogonal transformer (discrete cosine transformer) 2.28.
...Absolute value generator 3.24...Quantizer 4.15.1? , 21.23...Buffer memory 5.
...High order bit non-zero detector 6.36...Bit plane selector 7...Run length encoder 8...Most significant bit detector 10...Difference PCM calculator 13...Address controller 14...Non-zero block detector 22...Ordered device

Claims (3)

[Claims] (1) Convert one screen's worth of image data into positive/negative distributed data, separate the quantized converted data into positive/negative signs and amplitude data, and convert the entire one screen's worth of amplitude data from upper bits to lower bits. In a method that performs run-length encoding of binary information for each plane, for data whose amplitude is encoded for the first time as non-zero on the encoding bit plane, a run-length code and a plus/minus sign for that data are used. A bit plane encoding method characterized by: encoding data whose amplitude is non-zero in the upper bit plane, and encoding only a run length code for encoded data whose amplitude is non-zero. (2) When encoding each bit plane of coefficients that have been orthogonally transformed and quantized in block units, blocks containing coefficients encoded as non-zero in the encoded bit plane are first encoded. For blocks that encode non-zero coefficients in the encoded bit plane for the first time, in a predetermined order, blocks that have no coefficients that become non-zero in the encoded bit plane, excluding encoded blocks, are A bit-plane encoding method characterized by encoding consecutive numbers and then encoding non-zero coefficients. (3) When the DC components of coefficients cosine-transformed with a certain block size are encoded for all blocks prior to bit-plane encoding of the AC components, the sum of the absolute values of the differences between the DC components of adjacent blocks. Claim (2) characterized in that the encoding is performed in order from the largest block.
) bit-plane encoding method.