KR20100057345A - Multi-bit nonvolatile memory device - Google Patents

Abstract

PURPOSE: In order to etch a part of the control insulating layer or the tunneling insulation layer and it has the mutually different thickness the multi-bit non-volatile memory device forms. According to the thickness, the multi-bit is embodied with the differently applied electric field. CONSTITUTION: The tunneling insulation layer(120) is formed on the substrate(110). The charge trapping layer(130) is formed on the tunneling insulation layer. The control insulating layer(140) is formed on the charge trapping layer. The gate electrode(150) is formed on the control insulating layer. One part of the insulating layer is formed in order to have rest and mutually different thickness.

Description

Multi-bit nonvolatile memory device

The present invention relates to a nonvolatile memory device, and more particularly, to a multi-bit nonvolatile memory device.

Recently, due to the remarkable development of the information and communication industry, the demand of various memory devices is increasing. In particular, memory devices required for portable terminals, MP3 players, and the like are required to be nonvolatile, in which recorded data is not erased even when the power is turned off. Nonvolatile memory devices can be electrically stored and erased, and data can be stored even when power is not supplied. Therefore, their applications are increasing in various fields. However, the conventional dynamic random access memory (DRAM) constructed using semiconductors has a volatile characteristic that loses all stored information when power is not supplied. Is being performed.

A representative nonvolatile memory device is a flash memory device having electrically isolated floating gates, and a flash memory device having a polysilicon floating gate has grown rapidly. However, as the demand for large-capacity memory increases, the flash memory device of the conventional polysilicon floating gate structure has shown a limit to increase in capacity as it scales down. This is due to the deterioration in reliability of the tunneling oxide film due to scale down. In order to improve this problem, studies on existing flash memory devices have been actively conducted, but until now, only 2-bit flash memory devices have not been satisfactory.

As a result, development of a multi-bit nonvolatile memory device is required to dramatically increase the capacity without reducing the size of the device.

The technical problem to be solved by the present invention is to provide a multi-bit non-volatile memory device that can be fabricated in a simple process, the multi-bit is clearly implemented.

The multi-bit nonvolatile memory device according to the present invention for solving the above technical problem is provided with an insulating layer, so that the electric field applied to a portion of the insulating layer is different from the rest, the insulating layer is part of the remaining portion It is formed to have different thicknesses.

In order to solve the above technical problem, a multi-bit nonvolatile memory device according to the present invention comprises a substrate; A tunneling insulating layer formed on the substrate; A charge trap layer formed on the tunneling insulating layer; A control insulating layer formed on the charge trap layer; And a gate electrode formed on the control insulating layer, wherein at least one insulating layer of the tunneling insulating layer and the control insulating layer has a thickness different from that of the remaining portion.

According to the present invention, even through a simple process of etching a part of the control insulating layer or the tunneling insulating layer, even if the same voltage is applied, the strength of the applied electric field varies depending on the thickness, thereby realizing a multi-bit.

The multi-bit nonvolatile memory device according to the present invention includes an insulating layer having a portion having a thickness different from that of the remaining portion. If a part of the insulating layer has a different thickness from the other part, the electric field is different depending on the thickness of the insulating layer is possible to implement a multi-bit. Such multi-bit nonvolatile memory devices include flash memory devices, ferroelectric memory devices, organic bistable memory devices, magnetic memory devices, and resistance change memories. The present invention can be applied to all nonvolatile memory devices having an insulating layer, such as a resistive memory device, a phase change memory device, and the like.

Hereinafter, exemplary embodiments of a multi-bit nonvolatile memory device according to the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you.

1 is a view showing a schematic configuration of a preferred embodiment of a multi-bit nonvolatile memory device according to the present invention.

Referring to FIG. 1, the multi-bit nonvolatile memory device 100 according to the present invention may include a substrate 110, a tunneling insulating layer 120, a charge trap layer 130, a control insulating layer 140, and a gate electrode 150. ).

The substrate 110 may be a silicon substrate on which a source region and a drain region are formed.

The tunneling insulating layer 120 is formed on the substrate 110 and may be made of an insulating material such as silicon oxide (SiO ₂ ). Silicon oxide may be formed by thermally oxidizing a silicon substrate when using a silicon substrate.

The charge trap layer 130 is formed on the tunneling insulating layer 120, and is a region in which charge is trapped and de-trapped and exhibits memory characteristics due to trap and detrap of charge. The charge trap layer 130 may be made of polysilicon, an insulating material, nanoparticles, or the like. Insulation materials such as hafnium oxide (HfO ₂ ), ruthenium oxide (RuO ₂ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), zinc oxide (ZrO ₂ ), and lanthanum oxide (La ₂ O ₃ ) Transition metal oxide, perovskite, or the like may be used. The nanoparticles may be metal nanodots, metal oxide nanodots, or compound semiconductor nanodots having a large work function. The metal nanopoints may be formed of metals such as gold (Au), tungsten (W), and platinum (Pt), and the metal oxide nanopoints may be formed of metal oxides such as iron oxide (Fe ₂ O ₃ ) and zinc oxide (ZnO). The compound semiconductor nano dot may be formed of a compound semiconductor such as mercury telluride (HgTe) or cadmium telluride (CdTe).

Control dielectric layer 140 than a charge trap layer 130 is formed on a first insulating section (141) having a first thickness (t _1), as shown in Figure 1 and the first thickness (t ₁₎ It is formed to have a second insulating portion 142 having a large second thickness (t ₂ , t ₁ <t ₂ ). The control insulating layer 140 may be formed by forming an insulating layer having a second thickness t ₂ on the charge trap layer 130 and then etching a portion of the region 141. The etching used to form the control insulation layer 140 does not have an ultra fine line width, but the process window is wide, so that the control insulation layer 140 is easily formed using conventional lithography and etching techniques. can do. The control insulating layer 140 may be formed of a material having a higher dielectric constant than silicon oxide (SiO ₂ ) such as hafnium oxide (HfO ₂ ).

The gate electrode 150 is formed on the control insulating layer 140 and is made of a conductive material such as platinum (Pt).

Hereinafter, the multi-bit nonvolatile memory device 100 shown in FIG. 1 will be described in that multi-bits can be implemented.

A state in which the charge is empty in the charge trap layer 130 is called an initial state, and a state in which the multi-bit nonvolatile memory device 100 is in an initial state is defined as "0".

In addition, a voltage is applied to the gate electrode 150 while the substrate 110 is grounded to trap the charge in the charge trap layer 130. In this case, since the thickness t ₁ of the first insulation portion 141 of the control insulation layer 140 is smaller than the thickness t ₂ of the second insulation portion 142, the first insulation portion 141 is second-insulated. A large electric field is applied compared to the portion 142. This also affects the tunneling insulation layer 120, whereby an electric field having a larger portion of the tunneling insulation layer disposed under the first insulation portion 141 than the tunneling insulation layer portion disposed under the second insulation portion 142 is applied. . Therefore, when the magnitude of the voltage applied to the gate electrode 150 is properly adjusted, charge is tunneled through the tunneling insulating layer portion disposed below the first insulating portion 141, but is lower than the second insulating portion 142. Charges are not tunneled through the portion of the tunneling insulation layer located.

That is, when the first voltage V ₁ is applied to the gate electrode 150, the voltage that allows charge to be tunneled only through a portion of the tunneling insulating layer positioned below the first insulating portion 141, the nanoparticle indicated by reference numeral 131. Only charges are trapped, and charges are not trapped in the nanoparticles indicated by reference numeral 132. As such, the state in which the charge is trapped in only some of the nanoparticles 131 is defined as "1".

When a voltage greater than the first voltage V ₁ is applied to the gate electrode 150, the portion of the tunneling insulating layer located below the first insulating portion 141 and the lower portion of the second insulating portion 142 may be disposed. Charge is also tunneled through the tunneling insulating layer portion. That is, when the second voltage V ₂ , which is a voltage for allowing charge to tunnel through all parts of the tunneling insulating layer 120, is applied to the gate electrode, not only the nanoparticles indicated by reference numeral 131 but also the nanoparticles indicated by reference numeral 132. The charge is trapped. As such, the state in which the charge is trapped in all the nanoparticles 131 and 132 existing in the charge trap layer 130 is defined as "2".

As a result, the multi-bit nonvolatile memory device 100 according to the present invention applies the first voltage V ₁ to the gate electrode 150 in the initial state to program “1” or to apply the second voltage V ₂ . It is possible to program "2". In addition, the "0", "1", and "2" states have different amounts of charge trapped in the charge trap layer 130, and thus, the programmed information can be read. Therefore, since only a simple process of etching part of the control insulating layer 140 using conventional lithography technology can realize multi-bits, it is possible to implement a large-capacity memory device without reducing the size of the device. do.

<Production Example>

First, the p-type silicon substrate is washed with acetone, methanol, JTB-111 and deionized water (DI water), and then a native oxide film (native) is used with diluted hydrofluoric acid (HF: DI water = 1: 100) solution. oxide) is removed. The silicon substrate is thermally oxidized (900 ° C., 1 minute) to form a silicon oxide (SiO ₂ ) film having a thickness of 5 nm on the silicon substrate to be used as a tunneling insulating film.

And gold nanoparticles are formed on a silicon oxide film. Gold nanoparticles are formed using polystyrene-block-poly (4-vinyl pyridine). At this time, the average size of the gold nanoparticles is 5nm, the density is 2.2 × 10 ¹¹ cm ^-2 .

A hafnium oxide (HfO ₂ ) film is formed on the gold nanoparticles to be used as a control insulating layer. The hafnium oxide film is formed to a thickness of about 120 nm by using atomic layer deposition (ALD). A portion of the hafnium oxide film is patterned and etched. At this time, the thickness of the etched portion is about 60nm. In order to remove defects of the hafnium oxide film, rapid thermal annealing (RTA) (800 ° C., 5 seconds) is performed in a nitrogen (N ₂ ) atmosphere.

After depositing about 100 nm of platinum (Pt) to be used as a gate electrode, heat treatment is performed at 400 ° C. for 30 minutes in a reducing atmosphere to remove interface defects and trapped charges.

Capacitance-voltage graph obtained by grounding the substrate 110 of the multi-bit nonvolatile memory device 100 manufactured by the above method and applying a forward and reverse sweep voltage to the gate electrode 150. A graph of the flatband voltage (V _FB ) according to the sweep voltage is shown in FIG. 2. A graph denoted by reference numeral 210 is a graph showing a flat band voltage according to a forward sweep voltage, and a graph denoted by reference numeral 220 is a graph showing a flat band voltage according to a reverse sweep voltage.

Referring to Figure 2, below 10V has a similar flatband voltage regardless of the forward and reverse sweep voltage. However, when the sweep voltage increases above 10V, a difference between the flat band voltage according to the forward sweep voltage and the flat band according to the reverse sweep voltage occurs. When a voltage of 10 V or more is applied to the gate electrode 150, the charge is tunneled through the tunneling insulating layer portion positioned below the first insulating portion 141 of the control insulating layer 140, and the nanoparticles indicated by reference numeral 131. This is because charge is trapped in the.

When the sweep voltage is increased to 17 V or more, the amount of charge trapped in the accumulation region in the inversion region increases rapidly, and the flat band voltage different from the forward sweep voltage increases rapidly. When a voltage of 17V or more is applied to the gate electrode 150, charge is also tunneled through a portion of the tunneling insulating layer positioned below the second insulating portion 142 of the control insulating layer 140, that is, all tunneling insulating layers ( This is because the charge is tunneled through the 120 so that the charge is trapped in all the nanoparticles 131 and 132.

As a result, from the graph shown in FIG. 2, the amount of charge trapped in the charge trap layer 140 varies according to the voltage of the gate electrode 150 in the multi-bit nonvolatile memory device 100 according to the present invention. It can be seen that the bits become implementable.

Meanwhile, FIG. 3 shows a graph of change in capacitance-voltage hysteresis according to the sweep voltage. Capacitance-voltage hysteresis refers to a memory window. As shown in Fig. 3, the maximum hysteresis value is about 4.5V, which corresponds to a memory window value of sufficient size when fabricating a multi-bit device.

In the above description, 3-bits are formed through the control insulating layer 140 including the first insulating portion 141 having the first thickness t ₁ and the second insulating portion 142 having the second thickness t ₂ . The device 100 to be implemented has been described. However, if the thickness of the control insulating layer 140 is changed in various ways, it is of course possible to realize multi-bits of 3 bits or more.

In addition, in FIG. 1, the control insulating layer 140 including the first insulating portion 141 having the first thickness t ₁ and the second insulating portion 142 having the second thickness t ₂ is provided. The bit nonvolatile memory device 100 is illustrated, but is not limited thereto. If the tunneling insulation layer 120 also has a different thickness, the strength of the electric field applied to the tunneling insulation layer 120 is changed according to the thickness, so that the multi-bits can be implemented in the same manner as the control insulation layer 140 has a different thickness. Will be. In addition, the multi-bit may be implemented even when the thicknesses of the control insulating layer 140 and the tunneling insulating layer 120 are changed. However, since the thickness of the tunneling insulating layer 120 is generally not thick as a few nm, it is easy to control the thickness of the control insulating layer 140 that can be formed to a relatively thick thickness.

In FIG. 1, a flash memory device using nanoparticles as a floating gate among the nonvolatile memory devices is illustrated and described. However, as described above, another nonvolatile memory device including an insulating layer is a ferroelectric memory device or an organic bistable memory. It is possible to implement a multi-bit by applying to devices, magnetic memory devices, resistance change memory devices, phase change memory devices, and the like.

Although the preferred embodiments of the present invention have been shown and described above, the present invention is not limited to the specific preferred embodiments described above, and the present invention belongs to the present invention without departing from the gist of the present invention as claimed in the claims. Various modifications can be made by those skilled in the art, and such changes are within the scope of the claims.

1 is a view showing a schematic configuration of a preferred embodiment of a multi-bit nonvolatile memory device according to the present invention.

FIG. 2 is a graph illustrating a flatband voltage (V _FB ) according to a sweep voltage of a multi-bit nonvolatile memory device according to the present invention.

FIG. 3 is a diagram illustrating a change graph of capacitance-voltage hysteresis according to a sweep voltage of a multi-bit nonvolatile memory device according to the present invention.

Claims (6)

In a multi-bit nonvolatile memory device having an insulating layer, And the insulating layer is formed such that the portion has a different thickness from the remaining portion so that the electric field applied to the portion of the insulating layer is different from the remaining portion. Board; A tunneling insulating layer formed on the substrate; A charge trap layer formed on the tunneling insulating layer; A control insulating layer formed on the charge trap layer; And A gate electrode formed on the control insulating layer; And at least one insulating layer of the tunneling insulating layer and the control insulating layer is formed such that a portion has a thickness different from that of the remaining portion. The method of claim 2, And the charge trap layer comprises nanoparticles. The method of claim 3, The nanoparticles multi-bit nonvolatile memory device, characterized in that made of at least one selected from metal nano dots, metal oxide nano dots and compound semiconductor nano dots. The method according to claim 2 or 3, The control insulating layer is a multi-bit nonvolatile memory device, characterized in that made of a material having a higher dielectric constant than silicon oxide (SiO ₂ ). The method of claim 5, And the control insulating layer is made of hafnium oxide (HfO ₂ ).

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