KR19980055963A - Floating gate manufacturing method of semiconductor device - Google Patents
Floating gate manufacturing method of semiconductor device Download PDFInfo
- Publication number
- KR19980055963A KR19980055963A KR1019960075200A KR19960075200A KR19980055963A KR 19980055963 A KR19980055963 A KR 19980055963A KR 1019960075200 A KR1019960075200 A KR 1019960075200A KR 19960075200 A KR19960075200 A KR 19960075200A KR 19980055963 A KR19980055963 A KR 19980055963A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- undoped
- floating gate
- polysilicon
- polysilicon film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 56
- 229920005591 polysilicon Polymers 0.000 claims abstract description 55
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000011065 in-situ storage Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 9
- 230000001590 oxidative effect Effects 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 239000002019 doping agent Substances 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000006911 nucleation Effects 0.000 claims description 2
- 238000010899 nucleation Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- 238000009751 slip forming Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 50
- 239000010409 thin film Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- CHNUOJQWGUIOLD-NFZZJPOKSA-N epalrestat Chemical compound C=1C=CC=CC=1\C=C(/C)\C=C1/SC(=S)N(CC(O)=O)C1=O CHNUOJQWGUIOLD-NFZZJPOKSA-N 0.000 description 2
- -1 ONO 2 nitride Chemical class 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 비휘발성 메모리 소자의 플로팅 게이트 폴리 실리콘막을 도우프되지 않은 폴리 실리콘막/인-시투 도우프된 폴리 실리콘막/도우프되지 않은 격리 그레인 구조의 HSG의 조합으로 제조하고 ONO 1 산화시 산화막의 두께 증가로 HSG에 의한 표면적 증가분을 보상함으로써 플로팅 게이트 및 프로그래밍 게이트의 특성을 향상시킬 수 있는 반도체 소자의 플로팅 게이트 제조 방법이 제시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, wherein the floating gate polysilicon film of a nonvolatile memory device is formed of an undoped polysilicon film / in-situ doped polysilicon film / an undoped isolation grain structure. A method of manufacturing a floating gate of a semiconductor device, which can be manufactured in combination and improves the characteristics of a floating gate and a programming gate by compensating an increase in surface area by HSG due to an increase in the thickness of an oxide film upon oxidation of ONO 1.
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로, 특히 이피롬(이하 EPROM이라 함), 이이피롬(이하 EEPROM이라 함), 플래쉬 이피롬(이하 Flash EPROM이라 함)과 같은 반도체 소자에서 플로팅 게이트 폴리 실리콘 박막(floating gate poly silicon thin film) 및 폴리간 절연막(inter-poly dielectric film) 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to floating gate polysilicon thin films in semiconductor devices such as EPyrom (hereinafter referred to as EPROM), EPyrom (hereinafter referred to as EEPROM) and Flash EPyrome (hereinafter referred to as Flash EPROM). The present invention relates to a method of manufacturing a floating gate poly silicon thin film and an inter-poly dielectric film.
Flash EPROM 등의 스택 게이트(stacked gate) 구조를 가지는 비휘발성 반도체 소자는 제조시 폴리 실리콘막 간의 절연 물질로 ONO(산화막/질화막/산화막) 다중층(multi layer)을 사용하고 있으며, 이 ONO 절연층(dielectric layer)의 특성이 소자의 동작 특성에 중요한 역할을 한다. ONO의 하부 산화막(ONO 1)은 폴리 실리콘층 위에 형성되는데 이 ONO 1 막의 특성(quality)과 전체 ONO 다중층의 절연 두께가 플래쉬 메모리 소자의 특성을 결정짓는 요인이 된다. 프로그래밍 후 데이터 기억(data retention)시 낮은 전계 지역(electric field region)에 있어서 낮은 누설(leakage) 특성을 가지는 절연층을 제조하기 위해서는 ONO 1의 특성이 좋아야 하는데 스택 게이트(stacked gate) 구조에서는 이 하부 산화막의 형성이 플로팅 게이트 폴리 실리콘막 위에서 이루어지기 때문에 ONO 1의 특성과 플로팅 게이트 폴리 실리콘의 특성은 서로 밀접한 관련을 갖게 된다.Non-volatile semiconductor devices having a stacked gate structure such as Flash EPROM use an ONO (oxide / nitride / oxide) multilayer as an insulating material between polysilicon films during manufacturing. The nature of the dielectric layer plays an important role in the device's operating characteristics. The lower oxide film (ONO 1) of ONO is formed on the polysilicon layer. The quality of the ONO 1 film and the insulation thickness of the entire ONO multilayer are factors that determine the characteristics of the flash memory device. In order to fabricate an insulating layer with low leakage in low electric field regions during data retention after programming, the characteristics of ONO 1 should be good. Since the oxide film is formed on the floating gate polysilicon film, the characteristics of ONO 1 and the floating gate polysilicon are closely related to each other.
종래의 플로팅 게이트는 게이트 산화막을 형성하고 게이트 폴리 실리콘막을 도우프되지 않은 상태로 증착한 후 POCl3를 도판트 소오스로하여 800℃ 이상의 고온에서 확산 방법을 이용하여 도우핑함으로써 형성한다. 그런데 POCl3를 이용하여 도우핑할 때 과도하게 도우핑하면 게이트 산화막 계면의 특성을 저하시켜 플로팅 게이트의 동작에 악영향을 미치게 되며 이를 개선하기 위하여 중간(medium) 도우핑을 하게 되면 도판트 농도의 웨이퍼 내에서의 균일성(within wafer uniformity)이 나빠지게 되고 도판트 후속 공정인 ONO 1층 형성시 플로팅 게이트 폴리 실리콘의 산화 속도에 영향을 주므로 절연층의 균일성 및 소자의 전기적 특성의 열화를 초래하게 된다. 또한 ONO 1의 두께가 두꺼워짐에 따라 소자의 누설 특성은 향상되나 산화시의 열공정에 의해 플로팅 게이트 폴리 실리콘에서 도판트의 외부 확산(out-diffusion)에 의한 게이트 산화막의 열화를 초래한다.Conventional floating gates are formed by forming a gate oxide film and depositing a gate polysilicon film in an undoped state, and then doping with a POCl 3 as a dopant source using a diffusion method at a high temperature of 800 ° C. or higher. However, when doping with POCl 3 , excessive doping decreases the characteristics of the gate oxide interface, which adversely affects the operation of the floating gate. Within wafer uniformity is deteriorated and affects the oxidation rate of floating gate polysilicon during the formation of ONO 1 layer, which is a subsequent dopant process, resulting in deterioration of the uniformity of the insulating layer and the electrical characteristics of the device. do. In addition, as the thickness of ONO 1 increases, the leakage characteristic of the device is improved, but the thermal process during oxidation causes deterioration of the gate oxide film due to out-diffusion of the dopant in the floating gate polysilicon.
따라서, 본 발명은 상기한 문제점을 해결하기 위한 반도체 소자의 플로팅 게이트 제조 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a floating gate manufacturing method of a semiconductor device for solving the above problems.
상술한 목적을 달성하기 위한 본 발명은 반도체 기판 상부에 필드 산화막, 플로팅 게이트 산화막 및 도우프되지 않은 폴리 실리콘막을 순차적으로 형성하는 단계와, 상기 도우프되지 않은 폴리 실리콘막 상부에 인-시투 도우프된 폴리 실리콘막을 형성하는 단계와, 상기 인-시투 도우프된 폴리 실리콘막 상부의 선택된 영역에 도우프되지 않은 반구형 폴리 실리콘을 증착하는 단계와, 상기 도우프되지 않은 반구형 폴리 실리콘막을 산화시켜 열산화막을 형성하는 단계와, 상기 열산화막 상부에 질화막을 증착하는 단계와, 상기 질화막 상부에 감광막을 도포하고 마스크 및 식각 공정을 실시하여 플로팅 게이트 패터닝 공정을 실시한 후 질화막을 산화시켜 캐패시터 절연 다중층을 형성하는 단계와, 상기 절연 다중층 상부에 프로그래밍 게이트 전극막을 형성하는 단계로 이루어진 것을 특징으로 한다.According to an aspect of the present invention, a field oxide film, a floating gate oxide film, and an undoped polysilicon film are sequentially formed on a semiconductor substrate, and an in-situ dope is formed on the undoped polysilicon film. Forming a doped polysilicon film, depositing undoped hemispherical polysilicon on a selected region over the in-situ doped polysilicon film, and oxidizing the undoped hemispherical polysilicon film to form a thermal oxide film. Forming a capacitor; depositing a nitride film on the thermal oxide film; applying a photoresist film on the nitride film; performing a mask and etching process; and performing a floating gate patterning process to oxidize the nitride film to form a capacitor insulation multilayer. And a programming gate electrode layer on the insulating multilayer. It characterized by comprising the steps of sex.
도 1a 내지 도 1e 는 본 발명에 따른 반도체 소자의 플로팅 게이트 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1A to 1E are cross-sectional views of devices sequentially shown to explain a method of manufacturing a floating gate of a semiconductor device according to the present invention.
*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
1 : 반도체 기판1: semiconductor substrate
2 : 필드 산화막2: field oxide film
3 : 플로팅 게이트 게이트 산화막3: floating gate gate oxide film
4 : 도우프되지 않은 폴리 실리콘막4: undoped polysilicon film
5 : 인-시투 n+도우프된 폴리 실리콘막5: in-situ n + doped polysilicon film
6 : 도우프되지 않은 HSG6: undoped HSG
7 : ONO 1 열산화막7: ONO 1 thermal oxide film
8 : ONO 2 질화막8: ONO 2 nitride film
9 : ONO 3 산화막을 포함한 절연 다중층9: Insulation multilayer including ONO 3 oxide
10 : 프로그래밍 게이트 전극막10: programming gate electrode film
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1e 는 본 발명에 따른 반도체 소자의 플로팅 게이트 폴리 실리콘막을 제조하는 단계를 순서적으로 도시한 단면도이다.1A to 1E are cross-sectional views sequentially illustrating steps of manufacturing a floating gate polysilicon film of a semiconductor device according to the present invention.
도 1a 는 반도체 기판(1) 상부에 소자 격리를 위한 필드 산화막(2), 플로팅 게이트 산화막(3) 및 플로팅 게이트 산화막을 보호하기 위한 도우프되지 않은 폴리실리콘막(undoped poly-Si film)(4)을 순차적으로 형성한 단면도이다. 이때 도우프되지 않은 실리콘막을 형성하기 위한 실리콘 소오스 가스(source gas)는 SiH4또는 Si2H6로 하고 450~650℃의 온도에서 0.1~1 Torr의 증착 조건하에서 전체 플로팅 게이트 폴리 실리콘막 두께의 약 10% 이하의 두께로 증착한다.FIG. 1A shows an undoped poly-Si film 4 for protecting a field oxide film 2, a floating gate oxide film 3, and a floating gate oxide film for device isolation on top of a semiconductor substrate 1; ) Is a cross-sectional view formed sequentially. At this time, the silicon source gas for forming the undoped silicon film is SiH 4 or Si 2 H 6 and the thickness of the entire floating gate polysilicon film under the deposition conditions of 0.1 to 1 Torr at a temperature of 450 to 650 ° C. Deposit at a thickness of about 10% or less.
도 1b 는 도우프되지 않은 폴리 실리콘 박막(4) 상부에 LPCVD 장비에서 연속적으로 인-시투(in-situ) n+로 도우프된 폴리 실리콘막(5)을 전체 플로팅 게이트 폴리 실리콘막 두께의 약 2/3 정도의 두께로 증착한 단면도이다. 이때 도판트의 농도는 5×1020atoms/㎤ 이상이 되도록 한다.FIG. 1B shows a polysilicon film 5 doped continuously in-situ n + in LPCVD equipment on top of an undoped polysilicon thin film 4 approximately the thickness of the entire floating gate polysilicon film thickness. It is sectional drawing deposited to about 2/3 thickness. At this time, the concentration of the dopant is 5 × 10 20 atoms / cm 3 or more.
도 1c 는 같은 공정 장비에서 550~600℃의 온도 범위, 0.2~1 Torr의 압력 범위에서 가스 흐름율(gas flow rate)을 100~500sccm의 범위로 하여 폴리 실리콘 핵형성 자리(nucleation site)를 중심으로 성장된 격리된(isolated) 반구형 폴리실리콘(Hemispherical Silicon Grain; HSG)들이 형성되도록 도우프되지 않은 HSG(6)를 증착한 단면도이다.Figure 1c centers the polysilicon nucleation site with a gas flow rate in the range of 100-500 sccm in the temperature range of 550-600 ° C. and the pressure range of 0.2-1 Torr in the same process equipment. A cross-sectional view of depositing undoped HSG 6 so as to form isolated hemispherical silicon grains (HSG) grown as is.
도 1d 는 플로팅 게이트 폴리 실리콘의 상위 층인 도우프되지 않은 HSG 박막을 600℃ 이상의 온도의 산화 분위기에서 산화시켜 ONO 1 열산화막(7)을 형성한 후 질화막(Si3N4)를 증착하여 ONO 2층(8)을 형성한 단면도이다. HSG에 의한 표면적 증가가 1.5배 이상이므로 ONO 1 형성시 열산화막의 두께를 종래의 방법으로 ONO 1 을 형성할 때의 두께보다 1.5배 정도 두껍게 하여도 종래 기술에 의한 캐패시턴스 이상을 확보할 수 있으므로 누설 특성이 우수한 절연막을 형성할 수 있다.FIG. 1D illustrates that an undoped HSG thin film, which is an upper layer of floating gate polysilicon, is oxidized in an oxidizing atmosphere at a temperature of 600 ° C. or higher to form an ONO 1 thermal oxide film 7, and then a nitride film (Si 3 N 4 ) is deposited to form ONO 2. It is sectional drawing which formed the layer 8. Since the surface area increase by HSG is 1.5 times or more, leakage of the thermal oxide film when forming ONO 1 is about 1.5 times thicker than the thickness when forming ONO 1 by the conventional method. An insulating film excellent in characteristics can be formed.
도 1e 에 도시된 바와 같이 상기 공정 다음으로 마스크 및 식각 공정을 실시하여 플로팅 게이트 패터닝 공정을 실시한 후 반응로를 이용하여 질화막(ONO 2)을 산화시켜 캐패시터 절연 다중층(9)을 형성한다. 그리고 전도층으로 프로그래밍 게이트 전극막(10)을 형성한다.As shown in FIG. 1E, after the above process, a mask and an etching process are performed to perform a floating gate patterning process, and the nitride film ONO 2 is oxidized using a reactor to form a capacitor insulation multilayer 9. The programming gate electrode film 10 is formed of a conductive layer.
상기 언급한 증착 방법에 의한 MPS 증착으로 부분적인 도우프되지 않은 폴리실리콘막을 증착하는 것 이외에 550℃ 이하에서 SiH4또는 Si2H6를 Si 소오스 가스로 하여 비정질 상태의 실리콘을 증착한 후 650℃ 이하의 온도에서 1시간 이상 진공 상태 또는 순수한 N2가스 분위기에서 어닐링하여 실리콘 핵 주위의 실리콘 원자들의 표면 이동을 통하여 형성할 수 있다.In addition to depositing a partially undoped polysilicon film by MPS deposition by the above-mentioned deposition method, after depositing amorphous silicon using SiH 4 or Si 2 H 6 as a Si source gas at 550 ° C. or below, 650 ° C. Annealing in a vacuum or pure N 2 gas atmosphere for at least 1 hour at the following temperature may be formed through surface movement of silicon atoms around the silicon nucleus.
상술한 바와 같이 본 발명에 의하여 플로팅 게이트 폴리 실리콘 전극 및 절연층을 형성하면 도우프되지 않은 HSG막을 산화시킴으로써 ONO 1 막의 특성은 개선되어 소자의 특성을 향상시킬 수 있으며 HSG 막에 의한 표면적 증가로 인하여 충분한 캐패시턴스를 확보할 수 있으므로 공정 진행시의 프로세스 마진(process margin)을 충분히 확보할 수 있다. 또한 플로팅 게이트 폴리 실리콘막을 도우프되지 않은 폴리 실리콘과 도우프된 폴리 실리콘의 두층으로 증착함으로써 후속 열공정 진행시의 게이트 산화막의 열화를 막을 수 있다. 그리고 분리된 그레인 구조를 갖는 HSG를 증착함으로써 ONO 1을 산화하여 균일한 ONO 1의 두께를 얻을 수 있으며 우수한 누설 특성 및 균일성을 확보할 수 있다. 기존의 POCl3도우핑 방법에 의해 플로팅 게이트 폴리 실리콘을 형성하는 것에 비해 인-시투 도우핑을 실시함으로써 웨이퍼내의 균일성을 개선할 수 있다.As described above, when the floating gate polysilicon electrode and the insulating layer are formed according to the present invention, the characteristics of the ONO 1 film can be improved by oxidizing the undoped HSG film, thereby improving the characteristics of the device and increasing the surface area of the HSG film. Sufficient capacitance can be secured so that a sufficient process margin can be secured during the process. In addition, by depositing the floating gate polysilicon film into two layers of undoped polysilicon and doped polysilicon, deterioration of the gate oxide film during the subsequent thermal process can be prevented. In addition, by depositing HSG having a separate grain structure, it is possible to oxidize ONO 1 to obtain a uniform thickness of ONO 1 and to secure excellent leakage characteristics and uniformity. The uniformity in the wafer can be improved by performing in-situ doping as compared to forming floating gate polysilicon by the conventional POCl 3 doping method.
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960075200A KR19980055963A (en) | 1996-12-28 | 1996-12-28 | Floating gate manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960075200A KR19980055963A (en) | 1996-12-28 | 1996-12-28 | Floating gate manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR19980055963A true KR19980055963A (en) | 1998-09-25 |
Family
ID=66395617
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019960075200A KR19980055963A (en) | 1996-12-28 | 1996-12-28 | Floating gate manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR19980055963A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101006868B1 (en) * | 2008-11-21 | 2011-01-12 | 한양대학교 산학협력단 | Multi-bit nonvolatile memory device |
-
1996
- 1996-12-28 KR KR1019960075200A patent/KR19980055963A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101006868B1 (en) * | 2008-11-21 | 2011-01-12 | 한양대학교 산학협력단 | Multi-bit nonvolatile memory device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6455372B1 (en) | Nucleation for improved flash erase characteristics | |
| KR100207444B1 (en) | Capacitor fabrication method and its device having high dielectronic layer and electrode | |
| US5840607A (en) | Method of forming undoped/in-situ doped/undoped polysilicon sandwich for floating gate application | |
| KR100697353B1 (en) | Method for providing a dopant level for polysilicon for flash memory devices | |
| US5364813A (en) | Stacked DRAM poly plate capacitor | |
| KR20050070529A (en) | Method of manufacturing a flash memory device | |
| US4697330A (en) | Floating gate memory process with improved dielectric | |
| KR100192017B1 (en) | Fabrication process of semiconductor device | |
| JP3847683B2 (en) | Manufacturing method of semiconductor device | |
| KR100596832B1 (en) | Method and apparatus for minimizing diffusion in stacked capacitors formed on silicon plugs | |
| US6015984A (en) | Capacitor with oxide/nitride/oxide composite dielectric suitable for embedded nonvolatile memory in analog applications | |
| US5893980A (en) | Semiconductor device capacitor fabrication method | |
| US6777764B2 (en) | ONO interpoly dielectric for flash memory cells and method for fabricating the same using a single wafer low temperature deposition process | |
| KR20020002266A (en) | Semiconductor device and manufacturing method thereof | |
| KR19980055963A (en) | Floating gate manufacturing method of semiconductor device | |
| KR100390956B1 (en) | Method of manufacturing a flash memory device | |
| KR100416816B1 (en) | Method for forming floating gate of semiconductor device | |
| JP2632839B2 (en) | Manufacturing method of integrated circuit | |
| KR100193893B1 (en) | Manufacturing method of semiconductor device | |
| KR0183820B1 (en) | Method of manufacturing semiconductor device having ono structure insulating film | |
| KR100510526B1 (en) | Capacitor of semiconductor device and method for fabricating the same | |
| KR100274352B1 (en) | Method of manufacturing a flash memory cell | |
| KR100314739B1 (en) | Method for forming floating gate in semiconductor memory device | |
| KR930008875B1 (en) | Manufacturing method of semicondcutor device | |
| KR100505452B1 (en) | Capacitor Formation Method of Semiconductor Device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |