JPH11284087A - Nonvolatile semiconductor memory and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a long write/erase life and enable the reduction of the erase voltage, by forming many columnar protrusions on a floating gate, and flowing a tunnel current from the top end of the protrusion to erase information. SOLUTION: A plurality of columnar protrusions 3b are formed on the top face of a floating gate 5, and protrusions 3c are formed on the columnar protrusions 3b tops. The tops of the protrusions 3c locate near a control gate 8 and hence an electric field concentration occurs to flow a Fowler- Nordheim(FN) tunnel current, thereby erasing information. Since the many columnar protrusions 3b are formed on the top face of the floating gate 5, the write and erase of information are repeated and the FN tunnel current flows from other columnar protrusion 3b, if a tunnel insulation film 6 covering one columnar protrusion 3b deteriorates to make the FN tunnel current hard to flow.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to an improvement in erasing characteristics of a split gate flash memory.
It aims to improve the number of times of information rewriting and to reduce the reverse tunneling voltage.

[0002]

2. Description of the Related Art In recent years, with the expansion of application fields such as portable telephones and digital still cameras, nonvolatile semiconductor memory devices (EEPROMs;
llyErasable and Programmable Read Only Memory) is attracting attention. EEPROM records binary or more information depending on whether or not electric charge is accumulated in the floating gate, and reads information by changing the conduction between the source and drain regions depending on the presence or absence of electric charge in the floating gate. A semiconductor memory device, which is roughly classified into a stack gate type and a split gate type.
Among them, the split gate type flash EEPROM is disclosed in, for example, US Pat. Nos. 5,029,130, 5,045,488 and 50.
No. 67108. As shown in FIG. 5, the split gate type flash EEPROM has a semiconductor substrate 1
01 formed at a predetermined interval on drain region 11
A channel region 115 is formed between the source region 3 and the source region 114. A floating gate 109 extending from a part of the channel region 115 to a part of the source region 114 via the gate insulating film 105 is formed, and the upper part and the side part of the floating gate 109 are connected via the tunnel insulating film 110. A control gate 112 that covers and extends over part of the drain region 113 is formed.

[0003] A split gate type flash EEPROM will be described below.
The operation of the OM cell will be described. First, when writing data, a voltage is applied to the control gate 112 and the source region 114 (for example, 2 V to the control gate 112 and 12 V to the source region 114), and a current is caused to flow through the channel region 115 so that thermal electrons are applied to the floating gate 109. Inject and allow to accumulate. When erasing data, the drain region 113 and the source region 114 are grounded, and a high voltage (for example, 15V) is applied to the control gate 112.
Is applied, electrons accumulated in the floating gate 109 are converted into Fowler-Nordheim tunneling current (hereinafter, referred to as FN).
Control gate 112 as tunnel current).
Pull out to. At this time, since the protrusion 109a is formed in the peripheral portion above the floating gate 109,
Since the electric field is concentrated here, the FN tunnel current can flow at a lower voltage.

[0004] By the way, HSG (Hemi-Spherical Grain)
A technique for forming hemispherical grains called amorphous silicon on amorphous silicon is disclosed in, for example, Japanese Patent Application Laid-Open No. 3-272165.

[0005]

The conventional split gate type flash EEPROM erases information by utilizing the fact that an electric field is concentrated on the projection 109a of the floating gate 109. In recent years, in order to satisfy the demands such as extension of the use time of portable devices, further lowering of information erasing voltage is required, and it is necessary to emit electrons to the control gate at lower voltage. However, for this purpose, the sharpness of the protrusion 109a cannot be said to be sufficient, and it is necessary to sharpen it further.

Further, since the electric field is concentrated on the protrusion 109a, only a part of the tunnel insulating film 110 around the protrusion 109a is intensively and rapidly deteriorated. This makes it difficult for the FN tunnel current to flow, thereby shortening the life of the cell. In other words, the number of times that the flash EEPROM can be written and erased is small, and it is desired that the cell has a long life and the number of times of writing and erasing is increased.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has a large number of columnar projections formed on a control gate. This is a nonvolatile semiconductor memory device that performs erasing.

[0008]

FIG. 1 shows a split-gate flash EEPROM according to a first embodiment of the present invention. p
A channel region 11 is formed between a drain region 9 and a source region 10 formed at a predetermined interval on type single crystal semiconductor substrate 1. A floating gate 5 extending from a portion of the channel region 11 to a portion of the source region 10 via the gate insulating film 2 is formed, and an upper portion and a side portion of the floating gate 5 are connected via the tunnel insulating film 6. A control gate 8 that covers and extends over part of the drain region 9 is formed. A plurality of columnar projections 3b are formed on the upper surface of the floating gate 5, and a projection 3c is formed at the tip of the columnar projection 3b.
Since the apex of the projection 3c is close to the control gate 8, electric field concentration occurs here, an FN tunnel current flows, and information is erased. Which of the plurality of columnar protrusions 3b receives the FN tunnel current depends on a delicate difference in size at the time of formation.

According to the flash EEPROM of this embodiment,
Since a large number of columnar projections 3b are formed on the upper surface of the floating gate 5, writing and erasing of information are repeatedly performed, the tunnel insulating film 6 covering one columnar projection 3b is deteriorated, and it becomes difficult for the FN tunnel current to flow. However, the FN tunnel current flows from another columnar projection 3b. Further, since the projection 3c is formed at the tip of the columnar projection 3b, the electric field is more concentrated, and the erasing voltage can be reduced. Further, the columnar projections 3b
Since the space between them is filled with the insulating film, capacitive coupling between the control gate 8 and the floating gate 5 can be reduced. The higher the height from the base to the top of the columnar projection 3b, the lower the capacitive coupling can be. Therefore, it is desirable to form the columnar projection 3b high enough to prevent the columnar projection 3b from breaking.

Hereinafter, a method of manufacturing a flash EEPROM according to the first embodiment of the present invention will be described. Step 1: As shown in FIG. 2A, a gate insulating film 2 made of SiO2 is formed on a p-type single crystal semiconductor substrate 1 to a thickness of 100.degree. Next, at a temperature of 500 using SiH4 gas
An amorphous silicon film 3 having a thickness of 1500 ° C. is formed by using an LPCVD method at a temperature of 580 ° C. to 580 ° C. Step 2: As shown in FIG. 2B, annealing is performed for about 1 hour in an N2 atmosphere at 600 ° C. to crystallize the amorphous silicon of the first conductive film 3 into polysilicon and to form hemispherical grains on the surface. (HSG) 3a is formed. Next, phosphorus (P) ions are implanted into the entire surface to form an amorphous silicon film 3.
Is the first conductive film 3. Next, SOG (Spin On Gla
ss) and annealed in a nitrogen atmosphere at 800 ° C.
An iO2 film 4 is formed. Step 3: As shown in FIG. 2 (c), the entire surface is etched back to expose only the tops of the hemispherical grains 3a, and the SiO2 film 4 remaining at the base of the hemispherical grains 3a is finely masked.
And In order to expose only the top portion, if the CO emission intensity is monitored using plasma etching, it is known that the hemispherical grains 3a have been exposed, and the etching may be terminated at this point. Step 4: As shown in FIG. 3A, anisotropic etching of Si of the first conductive film 3 is performed using the fine mask 4 as a mask.
The columnar projections 3b and the projections 3c are formed. Step 5: As shown in FIG. 3B, the space between the columnar projections 3b is filled with an insulating film. As this method, for example, SOG
(Spin On Glass) may be applied and annealed. Next, the floating gate 5 is formed by etching a predetermined region of the gate insulating film 2 and the first conductive film 3 using a mask made of a photoresist (not shown). Step 6: As shown in FIG. 2D, a part of the tunnel insulating film 6 and a part of the gate insulating film 2 made of SiO2 are formed to a thickness of 300 ° by thermal oxidation or CVD. Next, a polysilicon film is formed by using the LPCVD method, and phosphorus is doped to form a second conductive film 6 having a thickness of 1000. Step 7: As shown in FIG. 1, the second conductive film 6 is etched using a mask (not shown) made of a photoresist so that the second conductive film 6 remains on the floating gate 5 and on the side and part of the channel region. And control gate 8
To form Next, using the floating gate 5 and the control gate 8 as a mask, an n-type impurity (such as arsenic or phosphorus) is ion-implanted into the semiconductor substrate 1 to form an n-type drain region 9 and an n-type source region 10. Next, an annealing process is performed to activate the ions implanted into each layer.
As described above, the nonvolatile semiconductor memory device of the present embodiment is formed.

Hereinafter, a second manufacturing method of the flash EEPROM according to the first embodiment of the present invention will be described. In this manufacturing process, the cross-sectional view of each process is exactly the same as in the first manufacturing method. Step 1: As shown in FIG. 2A, a gate insulating film 2 made of SiO2 is formed on a p-type single crystal semiconductor substrate 1 to a thickness of 100.degree. Next, at a temperature of 550 using SiH4 gas.
Amorphous silicon film with a thickness of 150
The first conductive film 3 is formed by implanting phosphorus ions over the entire surface. Step 2: As shown in FIG. 2B, annealing is performed in an N2 atmosphere at 600 ° C. for 10 to 20 minutes to crystallize the amorphous silicon of the first conductive film 3 into polysilicon and to form a hemisphere on the surface. The shape of grains (HSG) 3a is formed. Next, SOG is applied to the entire surface, and the SiO2 film 4 is formed at 800 ° C. in a nitrogen atmosphere. Steps 3 to 7: Steps 3 to 7 of the first manufacturing process
Is the same as As described above, the nonvolatile semiconductor memory device of the present embodiment is formed. According to this manufacturing process, annealing is performed after injecting impurities into amorphous silicon in advance, so that crystal nuclei for forming HSGs are easily formed, and thus annealing is completed in a short time.

Hereinafter, a split gate flash EEPROM according to a second embodiment of the present invention will be described. FIG.
(C) shows the flash EEPROM of the present embodiment. A side wall 13 is formed on the side of the floating gate 5. Other configurations are the same as those of the split gate flash EEPROM of the first embodiment. The side wall 13 makes the corner of the lower end of the control gate 8 obtuse and separates from the floating gate, so that unselected EEPROM cells can prevent a so-called reverse tunneling phenomenon in which electrons flow from the control gate to the floating gate. . Further, the capacitance between the control gate and the floating gate can be reduced.

Hereinafter, a method of manufacturing a flash EEPROM according to a second embodiment of the present invention will be described. Step 1: The same as Steps 1 to 4 of any of the first and second manufacturing steps of the first embodiment. Step 2: As shown in FIG. 4A, a predetermined region of the gate insulating film 2 and the first conductive film 3 is etched using a mask made of a photoresist (not shown) to form a floating gate 5. Next, an SiO2 film 12 is formed on the entire surface by CVD. Step 3: As shown in FIG. 4B, the entire surface of the SiO2 film 12 is etched back to form the sidewalls 13. At this time, the SiO2 film remains between the columnar projections 3b. Step 4: As shown in FIG. 4C, it is the same as Steps 6 and 7 of the manufacturing method of the first embodiment. From the above,
The nonvolatile semiconductor memory device according to the present embodiment is formed.

The atmosphere gas for annealing is not limited to N2, but may be an inert gas such as He or Ar.

[0015]

According to the flash EEPROM of the present invention, since a large number of columnar projections 3b are formed on the upper surface of the floating gate 5, information is erased by the FN tunnel current flowing from the top of the columnar projections 3b. By repeatedly writing and erasing information, one columnar projection 3 is formed.
Even if the tunnel insulating film 6 covering the b deteriorates and the FN tunnel current hardly flows, the FN tunnel current flows from another columnar projection 3b, so that a long write / erase life is provided.
In addition, since the projection 3c is formed on the top of the columnar projection 3b, the electric field is more concentrated, so that the erase voltage can be reduced.
Further, since the space between the columnar protrusions 3b is filled with the insulating film, the capacitive coupling between the control gate 8 and the floating gate 5 can be suppressed to a small value.

The sidewall 13 prevents the reverse tunneling phenomenon and reduces the capacitance between the control gate and the floating gate.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a split gate flash EEPROM according to an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram of a split gate flash EEPROM according to the embodiment of the present invention.

FIG. 3 is a manufacturing process diagram of the split gate flash EEPROM according to the embodiment of the present invention.

FIG. 4 is a manufacturing process diagram of the split gate flash EEPROM according to the embodiment of the present invention.

FIG. 5 is a sectional view of a conventional split gate flash EEPROM.

Claims (5)

[Claims] A source region and a drain region of a second conductivity type formed at predetermined intervals on a semiconductor substrate of a first conductivity type; and the source region and the drain region on the semiconductor substrate. A floating gate extending from a part of the channel region to a part of the drain region through a gate insulating film, and a tunnel insulating part of the floating gate from a part of the floating gate In a nonvolatile semiconductor memory device having a control gate that is covered with a film and extends over a part of the source region, the floating gate has a plurality of columnar protrusions on its upper surface,
A non-volatile semiconductor memory device characterized in that the space between the columnar projections is filled with a part of a tunnel insulating film. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said columnar projection has a projection at a top portion thereof. A step of forming a gate insulating film on the semiconductor substrate; a step of forming a first conductive film made of polysilicon having a plurality of hemispherical grains on the surface of the gate insulating film; Forming a film having etching selectivity with polysilicon on the conductive film of Step 1; and etching back the entire surface of the film having etching selectivity with polysilicon to expose the tops of the hemispherical grains. A step of using a film having an etching selectivity with the polysilicon remaining at the base of the crystal grains as a fine mask, and etching the first conductive film by anisotropic etching using the fine mask as a mask to form a columnar protrusion and Forming a projection on the top of the columnar projection, filling the gap between the columnar projections with an insulating film, and etching a predetermined region of the first conductive film to form a projection. A method for manufacturing a nonvolatile semiconductor memory device, comprising: a step of forming a loading gate; and a step of forming a control gate extending at least over a part of the floating gate via an insulating film. 4. The nonvolatile semiconductor memory device according to claim 1, further comprising a sidewall made of an insulating film on a side portion of said floating gate. 5. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a first conductive film made of polysilicon having a plurality of hemispherical grains on a surface of the gate insulating film, Forming a film having etching selectivity with polysilicon on the conductive film of Step 1; and etching back the entire surface of the film having etching selectivity with polysilicon to expose the tops of the hemispherical grains. A step of using a film having an etching selectivity with the polysilicon remaining at the base of the crystal grains as a fine mask, and etching the first conductive film by anisotropic etching using the fine mask as a mask to form a columnar protrusion and Forming a protrusion on the top of the columnar protrusion, forming a floating gate by etching a predetermined region of the first conductive film, and insulating the entire surface. Depositing a film, filling the space between the columnar protrusions with an insulating film, etching back the entire surface of the insulating film to form a sidewall, and extending at least over a part of the floating gate via the insulating film. Forming a control gate existing in the nonvolatile semiconductor memory device.