KR20100053393A - Method for fabricating nonvolatile memory device and nonvolatile memory device fabricated by the method - Google Patents

Abstract

PURPOSE: A method for fabricating a nonvolatile memory device and the nonvolatile memory device fabricated thereby are provided to improve the reliability of the device by preventing the loss of electrical charges. CONSTITUTION: A plurality of layers which is based on materials with different etching selectivity is alternately stacked on a semiconductor substrate(100). An opening passes through the layers. Expansion parts which are expanded from the opening are formed in a horizontal direction to the semiconductor substrate. An electrical charge trapping layer is conformally formed along the surface of the opening and the expanding parts. Patterns(142) of the electrical charge trapping layer are locally formed in the expansion parts.

Description

Method for fabricating nonvolatile memory device and nonvolatile memory device fabricated by the method

The present invention relates to a method of manufacturing a nonvolatile memory device and a nonvolatile memory device manufactured according to the present invention, and more particularly, to a method of manufacturing a nonvolatile memory device having a three-dimensional structure capable of improving reliability and a non-volatile memory device manufactured accordingly. A volatile memory device.

Generally, a nonvolatile memory device is an element capable of electrically erasing and storing data and preserving data even when a power supply is cut off. Accordingly, the use of nonvolatile memory devices has recently increased in various fields.

Nonvolatile memory devices constitute various types of memory cell transistors, and are classified into NAND type and NOR type according to a cell array structure. NAND type nonvolatile memory devices and NOR type nonvolatile memory devices each have advantages and disadvantages that are classified into high integration and high speed.

In particular, NAND type nonvolatile memory devices are advantageous for high integration due to a cell string structure in which a plurality of memory cell transistors are connected in series. In addition, since the NAND type nonvolatile memory device adopts an operation method of simultaneously changing the information stored in the plurality of memory cell transistors, the information update rate is much faster than that of the NOR type nonvolatile memory device. Due to this high density and fast update rate, NAND type nonvolatile memory devices are mainly used in portable electronic products requiring mass storage such as digital cameras or MP3 players. Researches and developments continue to promote and highlight the advantages of such NAND nonvolatile memory devices. Accordingly, a NAND nonvolatile memory device having a three-dimensional structure has been developed.

In addition, the nonvolatile memory devices may be classified into a floating gate type nonvolatile memory device and a charge trap type nonvolatile memory device according to the type of the memory storage layer constituting the unit cell. Among these, development of charge trap type nonvolatile memory devices has been increased in that low power, low voltage, and high integration can be realized.

An object of the present invention is to provide a method of manufacturing a non-volatile memory device having a three-dimensional structure that can improve the reliability.

In addition, another object of the present invention is to provide a non-volatile memory device having a three-dimensional structure that can improve the reliability.

The problem to be solved by the present invention is not limited to the above-mentioned problem, and other tasks not mentioned will be clearly understood by those skilled in the art from the following description.

In order to achieve the above object, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention alternately stacks a plurality of first and second material films having different etching selectivity on a semiconductor substrate. Forming an opening penetrating the plurality of first and second material films, removing the first material films exposed by the opening to form extensions extending in a direction parallel to the semiconductor substrate from the opening, and Conformally forming a charge storage film along the surface of the extensions, and removing the charge storage film formed on the sidewall of the second material film, thereby locally forming the charge storage film patterns in the extension.

In order to achieve the above object, a nonvolatile memory device according to an embodiment of the present invention includes a conductive layer stacked on a semiconductor substrate through an insulating layer and a body part connected to the semiconductor substrate through the conductive layers. And active side pillars including a plurality of protrusions protruding from the body portion toward sidewalls of the conductive layers, sidewalls of the conductive layers, and charge storage layer patterns formed between the protrusions of the active pillars.

According to another aspect of the present invention, there is provided a nonvolatile memory device including conductive patterns three-dimensionally arranged on a semiconductor substrate, and a semiconductor extending from the semiconductor substrate and passing between the conductive patterns. And a charge storage film pattern interposed between the patterns and the semiconductor pattern and the conductive pattern, wherein the charge storage pattern is separated from the charge storage film pattern in contact with another conductive pattern.

Specific details of other embodiments are included in the detailed description and the drawings.

According to the method of manufacturing a nonvolatile memory device of the present invention, when word lines are stacked in a direction perpendicular to a semiconductor substrate, charge storage layer patterns corresponding to one side walls of each word line may be formed. The charge storage layer patterns positioned on the upper and lower portions may be separated from each other.

Therefore, the charges trapped in the charge storage film can be diffused in a direction perpendicular to the semiconductor substrate to prevent the charges from being lost. Therefore, the reliability of the three-dimensional nonvolatile memory device can be improved.

In addition, since the word storage lines are formed and then the charge storage layers are separated to form charge storage layer patterns, a gate conductive material remains on the charge storage layer, thereby preventing electrical short circuits between adjacent word lines in the vertical direction.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. Also, in the present specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional and / or plan views, which are ideal exemplary views of the present invention. In the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical content. Accordingly, shapes of the exemplary views may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. For example, the etched regions shown at right angles may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device and not to limit the scope of the invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. A nonvolatile memory device according to embodiments of the present invention has a three-dimensional structure.

1 is a circuit diagram illustrating a nonvolatile memory device according to example embodiments.

Referring to FIG. 1, a nonvolatile memory device according to an embodiment of the present invention includes a cell array including a plurality of strings STRs. The cell array includes a plurality of bit lines BL1 to BL3, word lines WL1 to WL4, upper and lower select lines USL1 to USL3 and LSL, and a common source line CSL. In addition, a plurality of strings STR may be included between the bit lines BL1 to BL3 and the common source line CSL.

Each string STR includes upper and lower select transistors UST and LST and a plurality of memory cell transistors MC connected in series between upper and lower select transistors UST and LST. The drains of the upper select transistors UST are connected to the bit lines BL1 to BL3, and the sources of the lower select transistors LST are connected to the common source line CSL. The common source line CSL is a line to which the sources of the lower selection transistors LST are commonly connected.

In addition, the upper select transistors UST are connected to the upper select lines USL1 to USL3, and the lower select transistors LST are respectively connected to the lower select line LSL. In addition, each of the memory cells MC is connected to word lines WL1 to WL4.

Since the cell array is arranged in a three-dimensional structure, the strings STR have a structure in which the memory cells MC are connected in series in the z-axis direction perpendicular to the xy plane parallel to the upper surface of the substrate. Accordingly, channels of the selection transistors UST and LST and the memory cell transistors MC may be formed perpendicular to the xy plane.

In the nonvolatile memory device having a three-dimensional structure, m memory cells may be formed in each xy plane, and an xy plane having m memory cells may be stacked in n layers. (Where m and n are natural numbers)

Hereinafter, a nonvolatile memory device and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 to 9.

2 is a perspective view of a nonvolatile memory device according to an embodiment of the present invention. 3 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention. 3 is a cross-sectional view of a memory cell region of a nonvolatile memory device according to an exemplary embodiment of the present invention.

2 and 3, the interlayer insulating layer 110 and the conductive layers LSL, WL, and USL are alternately and repeatedly stacked on the semiconductor substrate 100.

Specifically, an impurity region (or well) 102 provided in the common source line (CSL of FIG. 1) is formed in the semiconductor substrate 100, and the interlayer insulating layer 110 and the conductive layer are formed on the impurity region 102. The films LSL, WL, USL are stacked in order. In the stacked conductive films LSL, WL, and USL, the top and bottom conductive films LSL and USL are used as selection lines, and the remaining conductive films WL are used as word lines.

The lower selection line LSL positioned at the lowermost layer may be formed in a plate form or in a line form separated from each other. The upper selection line USL positioned on the uppermost layer may be formed in a line shape separated from each other. The word lines WL positioned between the lower select line LSL and the upper select line USL may each have a flat plate shape. Since the word lines of each layer are formed in a flat plate shape, the same voltage may be applied to word lines of memory cells formed on the same layer.

In addition, the area of the word lines WL may gradually decrease toward an upper portion thereof, and edge portions of the stacked interlayer insulating layer 110 and the conductive layers LSL, WL, and USL may be stacked in a step shape.

A plurality of active pillars PL penetrate the stacked interlayer insulating layer 110 and the conductive layers LSL, WL, and USL. The active pillars PL are formed of a semiconductor material and correspond to each string of the nonvolatile memory device. That is, the channel of the selection transistors and the memory cell transistors of each string may be electrically connected through the active pillars PL.

The active pillars PL are spaced apart from each other and may be arranged in a matrix form on a plane. In addition, the active pillars PL may be electrically connected to the impurity region 102 in the semiconductor substrate 100 through the conductive layers LSL, WL, and USL. Each of the active pillars PL may protrude in the direction of the conductive layers LSL, WL, and USL in each of the layers on which the conductive layers LSL, WL, and USL are formed.

More specifically, the active pillars PL extend from the body portion 170 in a direction perpendicular to the upper surface of the substrate, and extend from the body portion 170 to protrude toward the conductive layers LSL, WL, and USL. , And a plurality of protrusions 172 spaced apart from each other. Each of the protrusions 172 may have a shape surrounding the body portion 170 while facing the corresponding conductive layers LSL, WL, and USL. Accordingly, the conductive layers LSL, WL, and USL of each layer may be spaced apart from the body 170 by the protrusions 172. According to an embodiment, the protrusions 172 may protrude at least the thickness of the charge storage layer pattern 142, and channels may be formed in the protrusions 172 when the nonvolatile memory device is operated.

On the other hand, according to another embodiment of the present invention, in the active pillars including the body portion and the protrusions, the protrusions in contact with the top and bottom conductive films (USL, LSL) may be omitted.

The charge storage layer patterns 142 are interposed between the protrusion 172 of the active pillar PL and the sidewalls of the conductive layers LSL, WL, and USL. That is, the charge storage layer pattern 142 contacts the conductive layers LSL, WL, and USL, and covers the surface of the protrusion 172 of the active pillar PL. The charge storage layer patterns 142 may be removed from the sidewalls of the body unit 170 so that the charge storage layer patterns 142 positioned on the upper and lower portions thereof may be electrically separated from each other. That is, the charge storage layer patterns 142 may be in contact with sidewalls of the conductive layers LSL, WL, and USL, and may be isolated between the upper and lower interlayer insulating layers 110.

Meanwhile, according to another exemplary embodiment of the present disclosure, the charge storage layer patterns locally formed on one sidewalls of the uppermost and lowermost conductive layers USL and LSL may be omitted.

Bit lines BL electrically connected to the active pillars PL may be formed on the active pillars PL. The bit lines BL may cross the upper selection lines USL and may be electrically connected to the active columns PL positioned in the same row or column among the active columns PL arranged in a matrix.

As described above, when the charge storage layer patterns 142 are separated for each layer, the charges trapped in the charge storage layer pattern 142 may be prevented from being diffused in a direction perpendicular to the word line WL, that is, the upper and lower portions. have. That is, after the charges are trapped, it is possible to prevent external or internal stress and data disturbance due to diffusion of charges over time, thereby improving reliability of the nonvolatile memory device having a three-dimensional structure.

Next, a method of manufacturing a nonvolatile memory device according to an embodiment will be described in detail with reference to FIGS. 4 to 9.

4 through 9 are diagrams sequentially illustrating a method of manufacturing a nonvolatile memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 4, the interlayer insulating film 110 and the conductive film 120 are repeatedly stacked in this order on the semiconductor substrate 100. The semiconductor substrate 100 may include an impurity region (or well) 102. The interlayer insulating layer 110 may be formed of a silicon oxide layer or a silicon nitride layer, and the conductive layer 120 may be formed of a polysilicon layer or a metal layer. The number of conductive films stacked may vary depending on the capacity of the nonvolatile memory device.

The interlayer insulating layer 110 and the conductive layer 120 may be stacked in a flat form on the memory cell region of the semiconductor substrate 100, and the area may gradually decrease toward the upper portion. That is, as shown in FIG. 3, edge portions of the interlayer insulating layer 110 and the conductive layer 120 may be stacked to form a step shape. In order to stack in a step shape, the conductive layers 120 may be stacked while repeating the deposition and patterning of the conductive layer 120. Alternatively, after laminating both the interlayer insulating layer 110 and the conductive layers 120, The conductive layers 120 may be formed by patterning edge portions layer by layer. In addition, the conductive layer 120 positioned on the uppermost layer may be patterned in a line shape.

Subsequently, a plurality of first holes 132 penetrating through the stacked interlayer insulating layer 110 and the conductive layer 120 are formed. In detail, a mask pattern (not shown) is formed on the interlayer insulating layer 110, and the first interlayer insulating layer 110 and the conductive layers 120 are selectively anisotropically etched using the mask pattern to form a first hole 132. ) Can be formed. The first holes 132 formed as described above may expose the impurity region 102 of the semiconductor substrate 100. Due to the characteristics of the anisotropic etching process, the first holes 132 may decrease in diameter downward. In this case, the diameters of the first holes 132 may be smaller than the distance between the adjacent first holes 132. In addition, the plurality of first holes 132 that pass through the stacked interlayer insulating layer 110 and the conductive layer 120 may be formed in a planar matrix form.

Referring to FIG. 5, sidewalls of the conductive layers 120 exposed by the first holes 132 are selectively etched to form second holes 136 in which the extensions 134 are formed. Specifically, by supplying an etching solution capable of selectively etching the conductive layers 120 into the first holes 132, a portion of the conductive layers 120 exposed by the first holes 132 is isotropic. It can be etched. When the etching solution is supplied through the first holes 132, the etching rate of the conductive layers 120 is higher than that of the interlayer insulating layers 110, so that the conductive layers 120 may be larger than the diameter of the holes formed in the interlayer insulating layers 110. The diameter of the hole formed in the can be increased. Therefore, in each of the layers on which the conductive films 120 are formed, extension portions 134 extending in a direction parallel to the conductive films 120 may be formed. That is, second holes 136 vertically penetrating the interlayer insulating layer 110 and the conductive layer 120 may be formed with the extension parts 134 spaced apart from each other over the stacked layers.

Referring to FIG. 6, the charge storage layer 140 is conformally deposited along the surfaces of the second holes 136. That is, the charge storage layer 140 may be formed on the sidewalls of the interlayer insulating layer 110 and the conductive layers 120 exposed by the second hole 136 and the impurity region 102. In this case, the charge storage layer 140 may be conformally formed along the surfaces of the extension portions 134. Therefore, the charge storage layer 140 may be deposited on sidewalls of the conductive layers 120 exposed by the extension 134 and portions of the upper and lower surfaces of the interlayer insulating layers 110. The charge storage layer 140 may be formed by depositing a charge blocking layer, a charge trapping layer, and a charge tunneling layer in order. That is, the oxide film, the nitride film, and the oxide film may be sequentially formed on the surface of the second hole 136.

Referring to FIG. 7, the sacrificial layer 150 is filled in the second hole 136 in which the charge storage layer 140 is formed. In this case, the sacrificial layer 150 may be sufficiently thick to the upper portion of the charge storage layer 140. Here, the sacrificial layer 150 may be formed of a material having an etch selectivity with respect to the charge storage layer 140, and may be formed of a material having excellent gap filling properties. For example, the sacrificial film 150 may include borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), tetraethically ortho silicate (TEOS), tonen sililazene (TOSZ), undoped silicate glass (USG), or SOG. It may be formed of (Spin On Glass).

After the sacrificial layer 150 is formed, the top surface of the sacrificial layer 150 may be planarized, and the planarization process may be performed until the interlayer insulating layer 110 is exposed. Subsequently, a mask pattern 165 for removing the charge storage layer 140 formed on the sidewalls of the interlayer insulating layers 110 is formed on the planarized sacrificial layer 150. In this case, the width W ₂ of the sacrificial layer exposed by the mask pattern 165 may be greater than the width W ₁ of the holes formed in the interlayer insulating layers 110. Alternatively, the mask pattern 165 may use a mask pattern used when forming the first holes 132 of FIG. 4.

Referring to FIG. 8, by anisotropically etching a portion of the charge storage layer 140 and the sacrificial layer 150 using the mask pattern 165, the interlayer insulating layer 110 and the conductive layer 120 may be penetrated. Third holes 132 ′ may be formed. The third holes 132 ′ may expose the impurity region 102, and expose sidewalls of the stacked interlayer insulating layers 110. The diameters of the third holes 132 ′ may be larger than the diameters of the first holes 132 and smaller than the diameters of the extension parts 134. When the third holes 132 ′ are formed, the charge storage layer 140 on the sidewalls of the interlayer insulating layer 110 and a portion of the charge storage layer 140 formed on the upper and lower surfaces of the interlayer insulating layer 110 may be removed. The charge storage layer 140 and a portion 152 of the sacrificial layers remain between the stacked interlayer insulating layers 110.

As such, as the third holes 132 ′ are formed, the charge storage layers 140 formed on the sidewalls of the interlayer insulating layers 110 are removed, and thus the charge storage layers of the type inserted into the extension part 134 of FIG. 6 are removed. Patterns 142 may be formed. That is, the charge storage layer pattern and the sacrificial layer may be formed between the third hole 132 ′ and the sidewalls of the conductive layers 120, and the charge storage layer pattern 142 may include the interlayer insulating layer 110 and the conductive layer 120. Conformally formed on the surface.

Meanwhile, without using the mask pattern, the charge storage layer 140 and the sacrificial layer 150 are anisotropically etched using the interlayer insulating layers 110 as an etch mask, thereby locally forming the charge storage layer pattern in the extensions 134. 142 may be formed.

9, the sacrificial layers 152 remaining between the interlayer insulating layers 110 are removed. Removing the sacrificial layer 152 may use a wet etching solution having an etch selectivity with respect to the charge storage layer pattern 142 and the interlayer insulating layers 110. That is, the sacrificial layer 152 remaining on the charge storage layer pattern 142 may be removed by supplying the wet etching solution to the third holes 132 ′. Accordingly, fourth holes 136 ′ having extensions 134 ′ may be formed between the interlayer insulating layers 110, and surfaces of the charge storage layer pattern 142 may be formed by the extensions 134 ′. Is exposed.

Referring to FIG. 10, in the fourth holes 136 ′ having the extensions 134 ′, semiconductor materials are filled to form active pillars 170 and 172. In this case, the semiconductor material may be filled in the extension portions 134 ′ formed between the interlayer insulating layers 110. Here, the semiconductor material may be a polycrystalline or single crystal semiconductor. Thereafter, the semiconductor material filled in the fourth holes 136 ′ may be planarized to expose the top surface of the uppermost interlayer insulating layer 100.

As such, as the active pillars are filled by filling the semiconductor material in the fourth holes 136 ′ having the extensions 134 ′, the active pillars penetrate through the stacked interlayer insulating layer 110 and the conductive layer 120. The body unit 170 and the protrusions 172 protruding into the conductive layer may be formed. In addition, since the charge storage layer patterns 142 are formed in the extension parts 134, the upper and lower charge storage layer patterns 142 may be separated from each other.

Hereinafter, a nonvolatile memory device and a manufacturing method thereof according to another embodiment of the present invention will be described in detail.

11 is a perspective view of a nonvolatile memory device according to another embodiment of the present invention.

Referring to FIG. 11, an impurity region (or well) 202 provided as a common source line may be formed in the semiconductor substrate 200, and an insulating layer and a conductive layer are alternately formed on the impurity region 202. It is repeatedly stacked. In detail, the insulating layer and the conductive layer may be patterned in a line shape, and word lines 282 separated from each other may be formed in the respective conductive layers. In other words, structures in which the word line 282 and the insulating line 210 are alternately stacked may be formed on the semiconductor substrate 200 to be spaced apart from each other. That is, the word lines 282 are three-dimensionally arranged on the semiconductor substrate 200.

The active patterns 230 are spaced apart from each other on the first sidewall of the word line 282 and the insulating line 210, and an insulating layer 290 is formed on the second sidewall opposite to the first sidewall. The active patterns 230 may be formed in a line pattern perpendicular to the semiconductor substrate 200, respectively. In addition, the active patterns 230 are formed to face the active patterns 230 formed on the first sidewalls of the horizontally adjacent word line 282 and the insulating lines 210, and are disposed between the active patterns 230. Is filled with the insulating film 240. In other words, the active patterns 230 extend in a direction perpendicular to the semiconductor substrate 200, and a plurality of word lines 282 are formed on one side walls of the active patterns 230.

In addition, the charge storage layer pattern 252 may be interposed between the active pattern 230 and the word line 282, and the charge storage layer pattern 252 may extend in the direction of the word line 282. In addition, the charge storage layer patterns 252 are locally formed between the vertically adjacent interlayer insulating layer patterns 210.

More specifically, the charge storage layer pattern 252 may conformally cover a portion of sidewalls of the active patterns 230 and upper and lower surfaces of the vertically adjacent interlayer insulating layer 210 patterns. That is, the charge storage layer patterns 252 are formed between the interlayer insulating layers 210 that are spaced apart from each other, and are electrically separated from each other by the other charge storage layer patterns 252 positioned above and below.

In addition, the active patterns 230 extending in a direction perpendicular to the semiconductor substrate 200 are electrically connected to bit lines BL crossing the word lines 282. The bit lines BL may be in direct contact with the top surface of the active pattern 230 or may be electrically connected through the bit line contacts.

As such, since the charge storage layer patterns 252 are separated from each other in a direction perpendicular to the semiconductor substrate 200, the charges trapped in the charge storage layer patterns 252 may be moved up and down along the surface of the active pattern 230. The spread can be prevented. Therefore, it is possible to prevent deterioration of reliability due to loss of charges in the three-dimensional nonvolatile memory device.

Hereinafter, a method of manufacturing a nonvolatile memory device according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 12 to 21.

Referring to FIG. 12, first and second insulating layers 210 and 215 having different etching selectivity are alternately stacked on the semiconductor substrate 200. In detail, the first and second insulating layers 210 and 215 are formed of materials having different wet etch rates. For example, the first and second interlayer insulating films 210 and 215 may be formed of, for example, a silicon oxide film and a silicon nitride film.

Line-type first trenches 220 are formed in the stacked first and second insulating layers 210 and 215. The first trenches 220 may be formed by performing a conventional photo and etching process. As the first trenches 220 are formed, first sidewalls of the stacked first and second insulating layers 210 and 215 may be exposed.

Referring to FIG. 13, the semiconductor layer 230 is formed on the first sidewalls of the first and second insulating layers 210 and 215 exposed by the first trenches 220. A method of forming the semiconductor layer 230 will be briefly described. The semiconductor material is conformally deposited along the first sidewalls of the stacked first and second insulating layers 210 and 215. Thereafter, the semiconductor layer 230 may be anisotropically etched to remove the semiconductor layer 230 formed on the impurity region 202 and the upper surface of the first insulating layer 210. Accordingly, the semiconductor layer 230 covering the first sidewalls of the first and second insulating layers 210 and 215 may be formed. After forming the semiconductor layer 230, an insulating material is buried and planarized in the first trench 220 to form an insulating layer 240 between the semiconductor layers 230.

Meanwhile, an epitaxial process using the semiconductor substrate 200 exposed by the first trenches 220 as a seed layer may be performed to form semiconductor layers in the first trenches 220. .

Referring to FIG. 14, second trenches 222 having a line shape are formed between the first trenches 220 (FIG. 12) in which the insulating layer 240 is filled. The second trenches 222 may expose second sidewalls of the stacked first and second insulating layers 210 and 215. As the second trenches 222 are formed, the stacked first and second insulating layers 210 and 215 may be patterned in a line shape.

Referring to FIG. 15, an etching solution having a high etching selectivity with respect to the second insulating layer 215 may be formed in the second trenches 222 exposing the second sidewalls of the stacked first and second insulating layers 210 and 215. Is supplied to remove the second insulating layers 215. That is, the extended portion 226 extended in the horizontal direction with the semiconductor substrate 200 may be formed between the stacked first insulating layers 210, and a portion of the sidewall of the semiconductor layer 230 is extended. May be exposed. In other words, between the insulating layers 230 buried in the first trench 220 (eg, FIG. 12), the impurity region 202 is exposed and the extension portions 226 are formed to expose sidewalls of the semiconductor layer 230. Three trenches 224 may be formed.

Referring to FIG. 16, the charge storage layer 250 is conformally formed along the surfaces of the third trenches 224. That is, along the surface of the extension portions 226 exposing sidewall portions of the semiconductor layer 230, the charge storage layer 250 is conformally formed. The charge storage layer 250 may be formed using a chemical vapor deposition method, and a part of a sidewall of the semiconductor layer 230, second sidewalls of the first insulating layer 210, and top surfaces of the first insulating layer 210 patterns. And a lower surface. The charge storage layer 250 may be formed by sequentially depositing the charge tunneling layer, the charge trapping layer, and the charge blocking layer. For example, the charge tunneling film may be formed of a silicon oxide film (SiO ₂ ) or a silicon oxynitride film (SiON). In addition, the charge tunneling film is a high dielectric constant material such as Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₃ , TiO ₂ , SrTiO ₃ (STO), (Ba, Sr) TiO ₃ (BST) Or it may form as a composite layer laminated by a combination of these. In this case, the charge tunneling layer may be formed of a material having a lower dielectric oil than the charge blocking layer. The charge trapping film may be formed of a silicon nitride film and / or a silicon oxynitride film. Charge blocking films are inherent, for example, Al ₂ O ₃ , HfO ₂ , ZrO ₂ , La ₂ O ₃ , Ta ₂ O ₃ , TiO ₂ , SrTiO ₃ (STO), (Ba, Sr) TiO ₃ (BST) It may be formed of a composite layer laminated with an electrifying material or a combination thereof. The charge blocking layer may be formed of a material having a higher dielectric constant than the charge tunneling layer.

Referring to FIG. 17, sacrificial layers 260 are formed by filling sacrificial materials in the third trenches 224 in which the charge storage layers 250 are formed.

As the sacrificial layer 260, a material having excellent gap filling property may be used, and the sacrificial layer 260 may be formed to a sufficient thickness up to the upper portion of the first insulating layer 210 positioned on the top layer. In this case, the top surface of the sacrificial layer 260 may be planarized, and further, may be planarized until the top surface of the first insulating layer 210 is exposed. Then, a mask pattern 275 for exposing the second sidewalls of the first insulating layers 210 is formed on the sacrificial layer 260 or the first insulating layer 210. The mask pattern 275 may be the same as the mask pattern for forming the second trench 222 of FIG. 14.

Referring to FIG. 18, the sacrificial layer 260 and the charge storage layer 260 formed on the second sidewall of the first insulating layer 210 are etched using the mask pattern 275. Accordingly, fourth trenches 222 ′ may be formed between the insulating layers 240 embedded in the first trench 220 (see FIG. 12). The fourth trenches 222 ′ expose the second sidewall of the first insulating layer 240 and the impurity region 202 again. In this case, the width of the fourth trench 222 ′ may be equal to or larger than the width of the two trenches (222 of FIG. 14).

In addition, as the fourth trenches 222 ′ are formed, the charge storage layers 250 conformally formed on the surfaces of the second trenches 222 of FIG. 14 may be separated into the charge storage layer patterns 252. have. That is, the charge storage layer patterns 252 may be locally formed in the extension portions 226 of FIG. 16 formed between the stacked first insulating layers 210. A portion of the sacrificial layer 262 remains on the charge storage layer pattern 252 in the extensions 226 of FIG. 16.

Referring to FIG. 19, the sacrificial layers 262 remaining in the extensions (226 of FIG. 16) are removed through a wet etching process. In the wet etching process, only the remaining sacrificial layers 262 may be selectively removed by using an etching solution having a high etching rate with respect to the sacrificial layers 262. Accordingly, the surface of the charge storage layer patterns 252 may be exposed by the fifth trench 224 ′ having the extensions 226 ′.

Referring to FIG. 20, a gate conductive layer 280 is formed on the charge storage layer patterns 252 to completely fill the fifth trenches 224 ′. The gate conductive layer 280 ′ may be formed using a chemical vapor deposition method, such that the gate conductive layer 280 may be filled in the extensions 226 ′. That is, the gate conductive layers 280 in the extension portions 226 ′ may be electrically connected to each other. The gate conductive layer 280 may be formed of a polysilicon layer or a metal layer.

Referring to FIG. 21, the gate conductive layer 280 is patterned so that the charge storage pattern 252 and the conductive lines 282 may be formed in the extension portions 226 ′. That is, the gate conductive layer 280 may be separated into word lines 282 having a line shape. Accordingly, word lines 282 may be formed between the stacked first insulating layers 210, and the word lines 282 and the first insulating layers 210 patterns may be perpendicular to the semiconductor substrate 200. It may have a stacked structure. After separating the word lines 282, the insulating layer 290 is buried between the stacked word lines 282 and the first insulating layer 210 patterns, and the top surface of the insulating layer 290 is planarized.

Thereafter, a process of separating the semiconductor layer 230 covering the first sidewalls of the charge storage layer patterns 252 into respective lines may be performed. That is, as illustrated in FIG. 11, the semiconductor layers 230 may be formed to be spaced apart from each other in a line shape on the first sidewalls of the stacked word lines 282. On the semiconductor layers 230 separated in a line shape, bit lines BL may be formed to cross the word lines 282 and be electrically connected to the semiconductor layers 230.

As such, in the three-dimensional nonvolatile memory device, when the word lines 282 are stacked in a direction perpendicular to the semiconductor substrate 200, charge storage patterns 252 contacting the word lines 282 may be disposed on the upper and lower portions thereof. The charge storage patterns 252 may be separated from each other. Therefore, it is possible to prevent the charges trapped in the charge storage patterns 252 from being diffused and lost in the vertical direction with respect to the semiconductor substrate 200.

Meanwhile, in another embodiment of the present invention, the charge storage layer patterns 252 may be locally formed without using the sacrificial layers illustrated in FIGS. 17 to 19. This will be described in detail with reference to FIGS. 22 to 24.

Referring to FIG. 16 and FIG. 22, the charge storage layer 250 is conformally formed along the surface of the third trench 224 of FIG. 16 including the extensions 226 of FIG. A trench (224 in FIG. 16) gate conductive film 280 is buried. As the conductive material, a polysilicon film or a metal film may be used. After filling the gate conductive film 280, the upper portion of the charge storage film 250 and the gate conductive film 280 may be planarized.

Referring to FIG. 23, a gate conductive layer 280 formed between horizontally adjacent first insulating layers 210 may be removed to separate the gate conductive layer 280 into word lines 282. That is, word lines 282 may be formed in the extension portions 222 of FIG. 16. During the anisotropic etching of the gate conductive layer made of the conductive material, the charge storage layer 250 of the sidewalls of the first insulating layers 210 may be removed together or partially remain. That is, trenches 233 are formed again between the horizontally adjacent first insulating layers 210.

Referring to FIG. 24, after the word lines 282 are formed, the charge storage layer 250 formed on the sidewalls of the first insulating layers 210 is removed. Accordingly, the charge storage layer patterns 252 covering one side wall and the top and bottom surfaces of the word line 282 may be locally formed in the extension portions 226 of FIG. 16.

Separating the charge storage layer 250 into the charge storage layer patterns 252 may be performed by performing an anisotropic or isotropic etching process. When the charge storage layer 250 is removed, the charge storage layer 250 on the sidewalls of the first insulating layers 210 may be selectively etched using a material having an etching selectivity with respect to the gate conductive layer using an etching gas or an etching solution. can do. For example, when the charge storage layer 250 of the sidewalls of the first insulating layers 210 is removed through an isotropic etching process, an etching solution such as HF, O ₃ / HF, phosphoric acid, sulfuric acid, and LAL may be used. have. In addition, in order to remove the charge storage layer 250, a fluoride-based etching solution and a phosphoric acid or sulfuric acid solution may be sequentially used.

On the other hand, when the word lines 283 are formed and then the charge storage layer 250 of FIG. 23 is removed on the sidewalls of the first insulating layers 210, gate conduction remaining on the surface of the charge storage layer 250 of FIG. 23. The materials can be removed together. Therefore, the charge storage layer patterns 252 are separated from each other, so that the charges trapped in the charge storage patterns 252 can be prevented from being diffused and lost in the vertical direction with respect to the semiconductor substrate 200, as well as the charges. The conductive material may remain on the storage layer 250 to prevent an electrical short between the word lines 282.

25 is a schematic diagram of a memory system including a nonvolatile memory device according to example embodiments.

Referring to FIG. 25, the memory system 1100 may include a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, It can be applied to a memory card or any device capable of transmitting and / or receiving information in a wireless environment.

The memory system 1100 includes a controller 1110, an input / output device 1120 such as a keypad, a keyboard, and a display, a memory 1130, an interface 1140, and a bus 1150. The memory 1130 and the interface 1140 communicate with each other via the bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or similar other processing devices. Memory 1130 may be used to store instructions performed by the controller. The input / output device 1120 may receive data or a signal from the outside of the system 1100 or output data or a signal to the outside of the system 1100. For example, the input / output device 1120 may include a keyboard, a keypad, or a display element.

The memory 1130 includes a nonvolatile memory device according to embodiments of the present invention. The memory 1130 may also further include other types of memory, volatile memory that can be accessed at any time, and various other types of memory.

The interface 1140 transmits data to the communication network or receives data from the network.

FIG. 26 is a block diagram schematically illustrating an example of a memory card 1200 including a flash memory device according to an exemplary embodiment.

Referring to FIG. 26, a memory card 1200 for supporting a high capacity of data storage capability includes a flash memory device 1210 according to the present invention. The memory card 1200 according to the present invention includes a memory controller 1220 that controls overall data exchange between the host and the flash memory device 1210.

SRAM 1221 is used as an operating memory of the processing unit 1222. The host interface 1223 includes a data exchange protocol of a host that is connected to the memory card 1200. The error correction block 1224 detects and corrects an error included in data read from the multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs various control operations for exchanging data of the memory controller 1220. Although not shown in the drawings, the memory card 1200 according to the present invention may further be provided with a ROM (not shown) for storing code data for interfacing with a host. Self-explanatory to those who have learned.

According to the flash memory device and the memory card or the memory system of the present invention, a highly reliable memory system can be provided through the flash memory device 1210 having improved erase characteristics of dummy cells. In particular, the flash memory device of the present invention may be provided in a memory system, such as a solid state disk (SSD) device, which is actively progressing recently. In this case, it is possible to implement a reliable memory system by blocking the read error caused by the dummy cell.

27 is a block diagram schematically illustrating an information processing system 1300 incorporating a flash memory system 1310 according to the present invention.

Referring to FIG. 27, the flash memory system 1310 of the present invention is mounted in an information processing system such as a mobile device or a desktop computer. The information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350 electrically connected to a system bus 1360, respectively. It includes. The flash memory system 1310 may be configured substantially the same as the above-described memory system or flash memory system. The flash memory system 1310 stores data processed by the CPU 1330 or data externally input. Here, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD), in which case the information processing system 1300 can stably store large amounts of data in the flash memory system 1310. As the reliability increases, the flash memory system 1310 may reduce resources required for error correction, thereby providing a high speed data exchange function to the information processing system 1300. Although not shown, the information processing system 1300 according to the present invention may be further provided with an application chipset, a camera image processor (CIS), an input / output device, and the like. Self-explanatory to those who have learned.

In addition, the flash memory device or the memory system according to the present invention may be mounted in various types of packages. For example, a flash memory device or a memory system according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline ( SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer- It can be packaged and mounted in the same manner as Level Processed Stack Package (WSP).

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention belongs may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. You will understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

1 is a simplified circuit diagram of a nonvolatile memory device according to embodiments of the present invention.

2 is a perspective view of a nonvolatile memory device according to an embodiment of the present invention.

3 is a cross-sectional view of a nonvolatile memory device according to an embodiment of the present invention.

4 through 10 are diagrams sequentially illustrating a method of manufacturing a nonvolatile memory device, according to an exemplary embodiment.

11 is a perspective view of a nonvolatile memory device according to another embodiment of the present invention.

12 to 21 are views sequentially illustrating a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention.

22 through 24 are diagrams sequentially illustrating a method of manufacturing a nonvolatile memory device, according to another exemplary embodiment.

25 is a schematic diagram of a memory system including a nonvolatile memory device according to example embodiments.

FIG. 26 is a block diagram schematically illustrating an example of a memory card including a flash memory device according to an exemplary embodiment. Referring to FIG.

27 is a block diagram schematically showing an information processing system equipped with a flash memory system according to the present invention.

Claims (14)

Alternately stacking a plurality of first and second material films having different etching selectivity on the semiconductor substrate, An opening penetrating the plurality of first and second material films, Removing the first material films exposed by the opening to form extended portions extending from the opening in a direction parallel to the semiconductor substrate, Forming a charge storage film conformally along the surface of the openings and extensions, And removing the charge storage layer formed on sidewalls of the second material layer to locally form charge storage layer patterns in the extension. The method of claim 1, And forming the openings form holes or trenches through the first and second material layers. The method of claim 1, Forming the charge storage layer patterns, Filling a sacrificial layer in the openings and extensions in which the charge storage layer is formed; Forming a mask pattern covering an upper portion of the second material layers, Using the mask pattern as an etching mask, removing the sacrificial layer and the charge storage layer in the opening, And removing the sacrificial layer filled in the extension parts to form the charge storage layer patterns. The method of claim 1, The extensions are formed by removing some of the first material layers, The charge storage layer patterns may be in contact with sidewalls of the first material layer. The method of claim 4, wherein And the first material layers are formed of a conductive layer. The method of claim 4, wherein The charge storage layer pattern may include a charge blocking layer, a charge trapping layer, and a charge tunneling layer, wherein the charge blocking layer is in contact with sidewalls of the first material layer. The method of claim 1, And forming a semiconductor pillar by filling a semiconductor material in the openings and the extension portions after forming the charge storage layer patterns. The method of claim 1, Before forming the openings, further comprising forming semiconductor patterns passing through the first and second material films, And the openings are formed between a pair of the semiconductor patterns. The method of claim 8, The extensions are formed by removing all of the first material layers, The charge storage layer patterns may be in contact with sidewalls of the semiconductor patterns. The method of claim 1, Before forming the charge storage layer patterns, And forming a conductive pattern in each of the extension portions in which the charge storage layer is formed. Conductive films stacked on the semiconductor substrate via an insulating film; Active pillars including a body portion penetrating the conductive layers and connected to the semiconductor substrate, and a plurality of protrusions protruding from the body portion toward sidewalls of the conductive layers; And And a charge storage layer pattern formed between sidewalls of the conductive layers and a protrusion of the active pillar. The method of claim 11, The protrusions are formed between insulating layers adjacent to each other in a vertical direction, and the charge storage layer patterns extend between the protrusions and the insulating layers. Conductive patterns three-dimensionally arranged on a semiconductor substrate; Semiconductor patterns extending from the semiconductor substrate and passing between the conductive patterns; And A charge storage layer pattern interposed between the semiconductor pattern and the conductive pattern; The charge storage pattern is separated from the charge storage layer pattern in contact with the other conductive pattern. The method of claim 13, The charge storage layer pattern extends to an upper surface and a lower surface of the conductive pattern.

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