KR20100050973A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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Publication number
KR20100050973A
KR20100050973A KR1020080110119A KR20080110119A KR20100050973A KR 20100050973 A KR20100050973 A KR 20100050973A KR 1020080110119 A KR1020080110119 A KR 1020080110119A KR 20080110119 A KR20080110119 A KR 20080110119A KR 20100050973 A KR20100050973 A KR 20100050973A
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KR
South Korea
Prior art keywords
fuse
film
contact
region
forming
Prior art date
Application number
KR1020080110119A
Other languages
Korean (ko)
Inventor
유창준
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080110119A priority Critical patent/KR20100050973A/en
Publication of KR20100050973A publication Critical patent/KR20100050973A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method of manufacturing a semiconductor device are provided to allow the edge of a contact plug of a pad region to be higher than the center of the contact plug by forming the contact plug which has higher density of a pattern in the pad region than a fuse region. CONSTITUTION: An insulating layer(120) is formed on a semiconductor substrate(100). The semiconductor substrate has a fuse region(F) and a pad region(P). A plurality of first contact holes are formed on the fuse region. A plurality of second contact holes are formed in the pad region. The second contact hole has a center higher than an edge. A plurality of first contact plugs(130a) are formed within the first contact hole. A plurality of second contact plugs(130b) are formed within the second contact hole. The conductive film(170) is formed on the first and second contact plug and the insulating layer. The fuse and conductive pattern are formed by etching the conductive.

Description

Manufacturing method of semiconductor device {METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving the manufacturing yield of the semiconductor device by simplifying the process.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. Accordingly, the manufacturing technology of semiconductor devices has been developed to improve the degree of integration, reliability, and response speed.

The semiconductor device mainly includes a fabrication process of repeatedly forming a circuit pattern set on a silicon substrate to form cells having an integrated circuit, and an assembly process of packaging the substrate on which the cells are formed in units of chips. In addition, a process for inspecting electrical characteristics of cells formed on the substrate is performed between the fabrication process and the assembly process.

The inspection step is a step of determining whether the cells formed on the substrate have an electrically good state or a bad state. This is to reduce the effort and cost consumed in the assembly process by removing the cells having a bad state through the inspection process before performing the assembly process. In order to detect the cells having the defective state at an early stage and regenerate them through a repair process.

Here, the repair process will be described in more detail as follows.

If a defect occurs during the semiconductor device manufacturing process, an extra cell is added to replace the defective device or circuit in the device design for the purpose of improving the yield of the device. A fuse is designed in the fuse area. The fuse is formed of a multilayer structure of, for example, a TiN film, an Al film, and a TiN film. The repair process is a process in which a cell, which has been found to be defective through an inspection process, is connected to an extra cell embedded in a chip using the fuse to be regenerated. That is, by cutting only specific fuses, location information of cells to be repaired is generated.

However, in the above-described prior art, since the fuse formed in the fuse region is formed on the same layer as the metal wiring formed in the pad region for inputting / outputting signals of the semiconductor device, the metal film for the fuse and the metal film for the metal wiring are formed. Due to the thickness difference therebetween, different masks may be applied to the fuse region and the pad region during the etching process for forming the fuse and the etching process for forming the metal wiring. As a result, in the above-described prior art, two mask processes must be performed during the etching process for forming the fuse and the etching process for forming the metal wiring, and thus, the process becomes complicated, resulting in a manufacturing yield of a semiconductor device. Is lowered.

The present invention provides a method for manufacturing a semiconductor device that can simplify the manufacturing process of the semiconductor device.

In addition, the present invention provides a method for manufacturing a semiconductor device capable of improving the production yield of the semiconductor device.

A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming an insulating film on a semiconductor substrate having a fuse region and a pad region, and etching the insulating layer to form a plurality of first contact holes in the fuse region. And forming a plurality of second contact holes in the pad region having a height higher than that at the center portions at both edge portions of the pad region, and a plurality of first contact plugs in the first contact holes of the fuse region. And forming a plurality of second contact plugs in the second contact hole of the pad region, forming a conductive film on the first and second contact plugs and the insulating film, and etching the conductive film. Forming a fuse in contact with the first contact plug in a fuse region, and forming a conductive pattern in contact with the second contact plug in the pad region Steps.

The second contact holes of the pad area are formed to have a higher pattern density than the first contact holes of the fuse area.

The first and second contact plugs are formed of a tungsten film.

The conductive film is formed in a multilayer structure of a first TiN film, an Al film, and a second TiN film.

The conductive layer is etched using one mask pattern.

The conductive pattern is formed of metal wiring.

The fuse is formed to have a thickness thinner than that of the conductive pattern.

In addition, the method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a first insulating film on a semiconductor substrate having a fuse region and a pad region, etching the first insulating film, Forming a first contact hole and forming a plurality of second contact holes in the pad area at both edge portions of the pad area, the second contact holes having a higher height than the center part, and in the first contact hole of the fuse area. Forming a plurality of first contact plugs and forming a plurality of second contact plugs in a second contact hole of the pad region, and a conductive film and a barrier on the first and second contact plugs and the first insulating film. Forming a film in sequence, forming a second insulating film on the barrier film, forming a mask pattern on the second insulating film, and etching the mask pattern. Etching the second insulating film and the barrier film portion of the fuse region, partially etching the second insulating film portion of the pad region, and etching the mask pattern as an etching mask. Performing a secondary etching process to form a fuse by etching a portion of the conductive layer of the fuse region to form a fuse, and forming a conductive pattern by etching the barrier layer of the pad region.

The second contact holes of the pad area are formed to have a higher pattern density than the first contact holes of the fuse area.

The first and second contact plugs are formed of a tungsten film.

The barrier film is formed of a TiN film.

The conductive film is formed in a stacked structure of a TiN film and an Al film.

The conductive pattern is formed of metal wiring.

The fuse is formed to have a thickness thinner than that of the conductive pattern.

The present invention forms contact plugs having a height higher than the center portion at the edge portion of the pad region in the pad region by forming contact plugs in the fuse region and the pad region, respectively, to have a higher pattern density in the pad region than in the fuse region. can do.

Therefore, the present invention can be formed so that the conductive film is stepped as the height difference between the contact plugs formed in the fuse area and the pad area is generated. Therefore, the present invention uses only one mask pattern by using the step difference to fuse the fuse. A fuse may be formed in the region and a metal wiring may be formed in the pad region.

Through this, the present invention can simplify the manufacturing process of the semiconductor device than the conventional case of using each mask pattern to form the fuse and the metal wiring, so that the present invention can improve the manufacturing yield of the semiconductor device Can be.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1A to 1G are cross-sectional views of processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, a first metal wire 110 is formed on a semiconductor substrate 100 having a fuse region F and a pad region P, and on which a predetermined lower structure (not shown) is formed. The first metal wiring 110 is formed of, for example, a copper film. The first insulating layer 120 is formed on the first metal wire 110.

Referring to FIG. 1B, the first insulating layer 120 is etched to form a plurality of first contact holes H1 in the fuse region F, and a plurality of second contacts in the pad region P. Referring to FIG. The hole H2 is formed. The second contact holes H2 of the pad region P are formed to have a higher pattern density than the first contact holes H1 of the fuse region F. As a result, the second contact holes H2 are formed. They are formed to have a higher height at both edge portions of the pad region P than at the center portion.

Referring to FIG. 1C, a metal layer 130a is formed to fill the first and second contact holes H1 and H2 on a result of the semiconductor substrate 100 on which the first and second contact holes H1 and H2 are formed. For example, a tungsten film is formed. The metal layer 130a is formed to be stepped along the profile of the second contact holes H2 in the pad region Pd.

Referring to FIG. 1D, a plurality of first contact plugs 130a are formed in the first contact hole H1 of the fuse region F by etching back the metal film to expose the first insulating layer 120. In addition, a plurality of second contact plugs 130b are formed in the second contact hole H2 of the pad region P. FIG. In this case, the second contact plugs 130b are formed to have a higher height at both edge portions of the pad region P than at the center portion.

Referring to FIG. 1E, a conductive layer 170 is formed on the first and second contact plugs 130a and 130b and the first insulating layer 120. The conductive film 170 has a multilayer structure of the first TiN film 140, the Al film 150, and the second TiN film 160, and the first and second TiN films 140 and 160 are barriers. It just acts. Here, the conductive layer 170 is formed to be stepped along the profile of the second contact plugs 130b in the pad region P. Referring to FIG. Subsequently, a second insulating film 180 is formed on the conductive film 170.

Referring to FIG. 1F, a mask pattern 190 is formed on the second insulating layer 180. Thereafter, a first etching process E1 using the mask pattern 190 as an etching mask is performed to etch portions of the second insulating layer 180 and the second TiN layer 160 of the fuse region F. FIG. In addition, a portion of the second insulating layer 180 of the pad region P is etched in a certain thickness.

Due to the difference in pattern density between the first contact plugs 130a formed in the fuse region F and the second contact plugs 130b formed in the pad region P, the fuse region F and the pad region P Since a step is generated and the conductive film 170 is formed to be stepped in the fuse area F and the pad area P due to the step, the fuse area F may be formed in the fuse area F during the first etching process E1. While part of the 2 TiN film 160 is removed, only a part of the thickness of the second insulating film 180 is etched in the pad region P, but the part of the second TiN film 160 is not etched.

Referring to FIG. 1G, a second etching process E2 using the mask pattern 190 as an etching mask is performed to form a fuse by etching a portion of the Al layer 160 in the fuse region F in a thickness thereof. In addition, a portion of the second TiN film 160 of the pad region P is etched to form a conductive pattern, for example, a second metal wiring.

As in the above-described first etching process, a portion of the Al film 160 may be etched in the fuse region during the second etching process E2 due to the step generated between the fuse region F and the pad region P. FIG. On the other hand, in the pad region P, only the second TiN film 160 is etched, but the Al film 160 is not etched. Therefore, in the exemplary embodiment of the present invention, only one mask pattern 190 may be used to form fuses and second metal wires having different thicknesses in the fuse region F and the pad region P, respectively. For example, according to the present invention, a fuse having a thickness thinner than that of the second metal wire of the pad region P may be formed in the fuse region F. FIG.

Subsequently, although not shown, a series of subsequent known processes are sequentially performed to complete the manufacture of the semiconductor device according to the embodiment of the present invention.

In the above-described embodiment of the present invention, the plurality of contact plugs having a height higher than the center portion at the edge of the pad region by having a pattern density higher than that of the fuse region in the pad region of the semiconductor substrate may be formed. The conductive film may be formed to be stepped in the pad region.

Therefore, in the exemplary embodiment of the present invention, a fuse and a second metal wiring having different thicknesses may be formed in the fuse region and the pad region, respectively, using only one mask pattern. Through this, the present invention can simplify the process compared with the conventional case where each mask pattern is used separately to form the fuse and the second metal wiring, and therefore, the present invention can improve the manufacturing yield of the semiconductor device. Can be.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

1A to 1G are cross-sectional views illustrating processes of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

F: Fuse area P: Pad area

100 semiconductor substrate 110 first metal wiring

120: first insulating film H1: first contact hole

H2: second contact hole 130: metal film

130a: first contact plug 130b: second contact plug

140: first TiN film 150: Al film

160: second TiN film 170: conductive film

180: second insulating film 190: mask pattern

E1: 1st etching process E2: 2nd etching process

Claims (14)

Forming an insulating film on the semiconductor substrate having a fuse region and a pad region; Etching the insulating layer to form a plurality of first contact holes in the fuse region, and to form a plurality of second contact holes having a height higher than that of a center portion at both edge portions of the pad region in the pad region; step; Forming a plurality of first contact plugs in the first contact hole of the fuse area and forming a plurality of second contact plugs in the second contact hole of the pad area; Forming a conductive film on the first and second contact plugs and the insulating film; And Etching the conductive layer to form a fuse in contact with the first contact plug in the fuse region and to form a conductive pattern in contact with the second contact plug in the pad region; Method of manufacturing a semiconductor device comprising a. The method of claim 1, And forming second contact holes in the pad area to have a higher pattern density than first contact holes in the fuse area. The method of claim 1, And the first and second contact plugs are formed of a tungsten film. The method of claim 1, The conductive film is a semiconductor device manufacturing method, characterized in that formed in a multilayer structure of the first TiN film, Al film and the second TiN film. The method of claim 1, The etching of the conductive film is a method of manufacturing a semiconductor device, characterized in that performed using one mask pattern. The method of claim 1, The conductive pattern is a semiconductor device manufacturing method, characterized in that formed by metal wiring. The method of claim 1, The fuse may be formed to have a thickness thinner than that of the conductive pattern. Forming a first insulating film on the semiconductor substrate having a fuse region and a pad region; The first insulating layer is etched to form a plurality of first contact holes in the fuse region, and a plurality of second contact holes having a height higher than that of the center portion at both edge portions of the pad region in the pad region. Forming; Forming a plurality of first contact plugs in the first contact hole of the fuse area and forming a plurality of second contact plugs in the second contact hole of the pad area; Sequentially forming a conductive film and a barrier film on the first and second contact plugs and a first insulating film; Forming a second insulating film on the barrier film; Forming a mask pattern on the second insulating film; Performing a first etching process using the mask pattern as an etching mask to etch the second insulating film and the barrier film portion of the fuse region and to partially etch the second insulating film portion of the pad region; And Performing a secondary etching process using the mask pattern as an etch mask, etching a portion of the conductive layer of the fuse region to form a fuse, and etching the barrier layer of the pad region to form a conductive pattern step; Method of manufacturing a semiconductor device comprising a. The method of claim 8, And forming second contact holes in the pad area to have a higher pattern density than first contact holes in the fuse area. The method of claim 8, And the first and second contact plugs are formed of a tungsten film. The method of claim 8, The barrier film is a manufacturing method of a semiconductor device, characterized in that formed by a TiN film. The method of claim 8, The conductive film is a semiconductor device manufacturing method, characterized in that formed in a laminated structure of the TiN film and Al film. The method of claim 8, The conductive pattern is a semiconductor device manufacturing method, characterized in that formed by metal wiring. The method of claim 8, The fuse may be formed to have a thickness thinner than that of the conductive pattern.
KR1020080110119A 2008-11-06 2008-11-06 Method of manufacturing semiconductor device KR20100050973A (en)

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KR1020080110119A KR20100050973A (en) 2008-11-06 2008-11-06 Method of manufacturing semiconductor device

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