KR20100047071A - Liquid crystal display device - Google Patents

Abstract

PURPOSE: A liquid crystal display device is provided to reduce manufacturing costs by replacing an optical connection line with an option data line. CONSTITUTION: A liquid crystal panel(102) comprises a plurality of gate lines and a plurality of data lines. The liquid crystal panel displays an image. An input unit supplies data. The input unit supplies a synchronizing signal, a clock signal, and option data. A timing controller(108) generates a timing control signal. The timing controller performs an option function which is performed using the option data. A driving unit drives the liquid crystal panel according to a timing control signal. A connector(112) supplies all kinds of signals and option data to the timing controller. An input port and more than one option pair are connected to the input unit and the connector.

Description

Liquid crystal display device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which can reduce manufacturing costs by reducing the number of optional connection lines and connection terminals.

As the information society develops, the demand for display devices is increasing in various forms. In response to this, various flat panel display devices such as liquid crystal display (LCD), plasma display panel (PDP), and electro luminescent display (ELD) have been studied, and some of them have already been used as display devices in various devices.

Among them, liquid crystal display devices are the most widely used, replacing CRTs for mobile image display devices due to the advantages of excellent image quality, light weight, thinness, and low power consumption. In addition to the mobile applications, various developments such as television monitors have been developed.

A liquid crystal display device displays an image using the optical anisotropy and polarization property of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

The liquid crystal display device includes a liquid crystal panel for displaying an image and a driving unit for driving the liquid crystal panel. The driving unit of the liquid crystal display may include a gate driver for driving a gate line on the liquid crystal panel, a data driver for driving a data line on the liquid crystal panel, and a timing controller for controlling the gate driver and the data driver.

The timing controller receives synchronization signals Vsync and Hsync, a clock signal DCLK, a data enable signal DE, data, and the like from an external system. The system also supplies an optional signal with the above signals to enable the timing controller to perform various optional functions.

There is an interface between the system and the timing controller. The interface converts data from the system to a specific data format of the liquid crystal panel and supplies the data to the timing controller. In addition, the interface converts the synchronization signals Vsync and Hsync, the clock signal DCLK, and the data enable signal DE from the system in accordance with the format of the liquid crystal panel to supply the timing controller.

Similarly, the interface modifies the option signal to perform the various option functions supplied from the system and supplies it to the timing controller. For example, the option signal is a signal for processing a function such as data format change, data bit number change or resolution change.

As described above, the option signal for processing various functions is supplied from the interface to the timing controller through an option connection line (eg, a cable) connected between the interface and the timing controller. The number of the option connection lines is present as many as the function of the option to be processed, and connection terminals respectively connected one-to-one with the option connection line exist in the timing controller. As a result, the number of option connection lines and connection terminals increases for each option function, thereby increasing the manufacturing cost of the liquid crystal display.

In addition, it is necessary to select whether to use a specific option function in the system in driving the liquid crystal display device. In this case, it is difficult to apply within a limited number of connection terminals when changing the driving method or applying new technology according to the system conditions. Points may occur.

It is an object of the present invention to provide a liquid crystal display device which can reduce manufacturing cost by replacing an option connection line to which an option signal is applied with an option data line.

According to an exemplary embodiment of the present invention, a liquid crystal display device includes a liquid crystal panel including a plurality of gate lines and a plurality of data lines, and displays an image, and supplies data corresponding to an image to be displayed on the liquid crystal panel and simultaneously synchronizes a signal. And an input unit for supplying option signals in which various signals including a clock signal and functions corresponding to various options are converted into data, and timing control using various signals including the synchronization signal and the clock signal by aligning data from the input unit. A timing controller for generating a signal and performing an option function corresponding to the option data, a driver for driving the liquid crystal panel according to a timing control signal from the timing controller, and between the input unit and the timing controller, Data, including the synchronization signal and the clock signal A connector for receiving various signals and option data and supplying them to the timing controller, an input port for inputting various signals including data from the input unit, a synchronization signal, and a clock signal between the input unit and the connector; At least one or more option pairs to which option data from an input unit are input are connected.

The liquid crystal display according to the present invention can reduce the manufacturing cost by reducing the number of option connection lines (cables) and connection terminals by processing the use of the option as data bits through option mapping synchronized to the clock signal. have.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a liquid crystal display device according to the present invention.

As shown in FIG. 1, the liquid crystal display according to the present invention crosses a plurality of gate lines GL1 to GLn and a plurality of gate lines GL1 to GLn and defines a plurality of data lines DL1 defining pixel regions. A liquid crystal panel 102 in which ~ DLm is arranged, a gate driver 104 for driving the plurality of gate lines GL1 to GLn, and a data driver 106 for driving the plurality of data lines DL1 to DLm. ), A timing controller 108 that controls driving timing of the gate driver 104 and the data driver 106, the liquid crystal panel 102, the gate driver 104, the data driver 106, and the timing. It includes a power supply 110 for supplying power for driving the controller 108.

In addition, the liquid crystal display according to the present invention is located between an external system (for example, a graphic module of a computer system or an image demodulation module of a television receiving system, not shown) and the timing controller 108, and an external system. And a connector 112 for transmitting data and various signals from the timing controller 108 to the timing controller 108.

The liquid crystal panel 102 includes pixels formed in regions divided by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm. Each of the pixels includes a thin film transistor TFT formed at an intersection between a corresponding gate line GL and a corresponding data line DL, and a liquid crystal cell connected between the thin film transistor TFT and a common electrode. . The thin film transistor TFT switches the pixel data voltage to be supplied to the corresponding liquid crystal cell from the corresponding data line DL in response to a gate scan signal on the corresponding gate line GL.

The gate driver 104 correspondingly supplies a plurality of gate scan signals to the plurality of gate lines GL1 to GLn in response to the gate control signal GSC from the timing controller 108. These multiple gate scan signals cause the multiple gate lines GL1 to GLn to be sequentially enabled for one horizontal synchronization signal.

The data driver 106 generates a plurality of pixel data voltages whenever any one of the plurality of gate lines GL1 to GLn is enabled in response to the data control signal DCS from the timing controller 108. And supplies them to a plurality of data lines DL1 to DLm on the liquid crystal panel 102. To this end, the data driver 106 inputs pixel data from the timing controller 108 by one line, and converts one line of pixel data into analog pixel data voltages using a gamma voltage set. To convert.

The power supply unit 110 receives an input voltage Vin from an external system to drive the timing controller 108, the data driver 106, the gate driver 104, and the liquid crystal panel 102. Create

At this time, the external system has a built-in LVDS transmitter for digitizing and compressing data (image signals), clock signals and synchronization signals, and lowering the voltage to 1V or less. The data (image signal), clock signal, and synchronization signals are supplied to the timing controller 108 through the connector 112 through the LVDS transmitter of the external system. In addition, the external system supplies option data obtained by converting options corresponding to option functions such as resolution change, data bit number change, etc. into data bits to the connector 112.

The connector 112 is located between an external system and the timing controller 108, and data (image signal) and various signals (clock signal CLK, horizontal synchronization signal Hsync, vertical synchronization) supplied from an external system. A signal Vsync, a data enable signal DE, and the like are received and supplied to the timing controller 108. In addition, the connector 112 receives option data capable of performing various option functions from an external system and supplies the option data to the timing controller 108.

The timing controller 108 rearranges the data supplied from the connector 112 and the clock signal CLK, the horizontal synchronization signal Hsync, the vertical synchronization signal Vsync and the data supplied from the connector 112. The gate control signal GCS and the data control signal DSC are generated using the enable signal DE. The gate control signal GCS is supplied to the gate driver 104 and the data control signal DCS is supplied to the data driver 106. In addition, the timing controller 108 performs an option function corresponding to the option data supplied from the connector 112.

In detail, the timing controller 108 includes data supplied from the connector 112 and various signals (clock signal CLK, horizontal synchronization signal Hsync, vertical synchronization signal Vsync, and data enable signal DE). ) And a receiving unit 114 for receiving the option data, wherein the receiving unit 114 includes an LVDS receiving unit 114a for receiving the data and various signals, and an option data receiving unit 114b for receiving the option data signal. It may be made of.

In addition, the timing controller 108 receives the data from the LVDS receiver 114a and arranges the data for one line of data to be supplied to the data driver 106, and the LVDS receiver ( Various signals (clock signal CLK, horizontal sync signal Hsync, vertical sync signal Vsync, and data enable signal DE) from 114a are received, and the gate control signal GCS and data control signal ( A control signal generator 118 for generating DCS, and an option processor 120 for receiving option data from the option receiver 114b and performing a corresponding option function. The option processor 120 reads information on the option function included in the option data to perform the corresponding option function.

LVDS between data (image signal) and various signals (clock signal CLK, horizontal sync signal Hsync, vertical sync signal Vsync, and data enable signal DE) between the external system and the connector 112. The LVDS 2-port is connected for supply in a controlled manner. In addition, an option pair for supplying the option data is connected between the external system and the connector 112. The option data is supplied to the connector 112 from the external system through the option pair.

The option pair consists of a pair of connection lines and supplies option data from an external system to the connector 112 in an LVDS manner. The connector 112 supplies the option data supplied through the option pair to the option processor 120 of the timing controller 102.

The connector 112 inputs data and various signals (clock signal CLK, horizontal sync signal Hsync, vertical sync signal Vsync, and data enable signal DE from an external system through the LVDS 2-port. Is supplied to the timing controller 108, the option data is also supplied to the option receiver 114b of the timing controller 108.

The option data is data set to a specific number of bits by the user, and is supplied to the connector 112 through the option pair from an external system. The option data supplied to the connector 112 is supplied to the timing controller 108. As shown in Table 1, the option data allocates a plurality of option functions to each bit, and when a high signal (eg, “1”) is input to a bit corresponding to each option, the option function is performed. The optional functions may include, for example, functions such as changing the number of bits of data, changing the resolution, changing the LVDS data transmission format, and improving image quality.

Option data Optional features 000000 Do not perform option 010000 Change number of data bits 001000 Change resolution 011000 Changing the number of data bits and resolution ... ...

In Table 1, option data is set to 6 bits of data. The number of bits of the option data may be set to a different number of bits by the user.

As described above, if the option data is 6 bits and a plurality of option functions are designated for each bit of the 6 bits, and a high signal is input to the corresponding bit, a high signal is input to the input bit. The corresponding option function is performed by the option processor 120.

As shown in Table 1, when option data of 010000 is inputted to the option processor 120 in which a high signal is input to the second bit of the 6-bit option data, the option processor 120 determines the value of 010000. The option function corresponding to the option data (change the number of data bits) is performed. When option data of 000000 which does not include a high signal is input to the option processor 120, the option processor 120 does not perform any option function.

When the option data of 001000 in which a high signal is input to the third bit of the 6-bit option data is input to the option processor 120, the option processor 120 corresponds to an option function corresponding to the option data of 00100. Change the resolution). In addition, when the option data of 011000 in which a high signal is input to the second and third bits of the 6-bit option data is input to the option processor 120, the option processor 120 corresponds to the option data of 011000. It performs optional functions (change of data bit number and change of resolution).

FIG. 2 is a diagram illustrating data, various signals, and option data supplied from the connector of FIG. 1 to the timing controller.

1 and 2, data and various signals (clock signal CLK, horizontal sync signal Hsync, vertical sync signal Vsync, and data enable signal DE) are LVDS from an external system. At the same time as input through the two-port, option data is specified for each bit to select a specific option function. The data and various signals (clock signal CLK, horizontal synchronization signal Hsync, vertical synchronization signal Vsync, data enable signal DE) and option data are LVDS clock signal LVDS CLK of the connector 112. Are synchronized to the LVDS 2-port and optional pairs, respectively.

As described above, the liquid crystal display according to the present invention is located between the connector 112 and the timing controller 108 by inputting option data for selecting an option function through a data bit in an option pair. The number of option connection lines can be reduced as compared with the conventional liquid crystal display device having a plurality of option connection lines (eg, cables). In addition, the liquid crystal display according to the present invention can reduce the number of connection terminals connected one-to-one with the plurality of option connection lines inside the timing controller 108 as compared to the conventional liquid crystal display. Due to this, the liquid crystal display device according to the present invention can reduce the manufacturing cost.

On the other hand, when it is necessary to add a new option function in driving the liquid crystal display, by specifying a new option function in a bit of the option data in advance so that a new option function is selected when a high signal is input to the bit. The addition of a new option function can be facilitated compared to the conventional liquid crystal display device, which has been difficult to add a new option function within a limited number of connection terminals.

1 is a view showing a liquid crystal display device according to the present invention.

FIG. 2 is a diagram showing data supplied from a connector of FIG. 1 to a timing controller, various signals, and option data. FIG.

<Brief description of the main parts of the drawing>

102: liquid crystal panel 104: gate driver

106: data driver 108: timing controller

110: power supply 112: connector

114: Receiver 114a: LVDS Receiver

114b: Optional data receiver 116: Data alignment unit

118: control signal generation unit 120: option processing unit

Claims (4)

A liquid crystal panel having a plurality of gate lines and a plurality of data lines and displaying an image; An input unit for supplying data corresponding to an image to be displayed on the liquid crystal panel and at the same time supplying various signals including a synchronization signal and a clock signal and option data in which functions corresponding to various options are converted into data; A timing controller aligning data from the input unit, generating a timing control signal using various signals including the synchronization signal and a clock signal, and performing an option function corresponding to the option data; A driver for driving the liquid crystal panel according to a timing control signal from the timing controller; And A connector positioned between the input unit and the timing controller and receiving various signals and option data including data from the input unit, a synchronization signal, and a clock signal, and supplying them to the timing controller, An input port to which various signals including data from the input, a synchronization signal, and a clock signal are input is connected between the input unit and the connector, and at least one option pair to which option data from the input unit is input. There is a liquid crystal display device. According to claim 1, And the option data is simultaneously input to the timing controller when the data and various signals are input to the timing controller in synchronization with the clock signal. According to claim 1, The option data is set to data having a specific number of bits, and if a high signal is input to each bit by designating a bit for each of a plurality of option functions, the liquid crystal display device characterized in that it performs the corresponding option function. According to claim 1, The timing controller, A receiver configured to receive data and various signals input through the input port; An option receiver configured to receive option data input through the option pair; A data arranging unit for arranging the data received in the receiving unit; A timing control signal generator for generating a timing control signal for controlling timing of the driver by using various signals received by the receiver; And And an option processor configured to process an option corresponding to the option data received by the option receiver.

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