KR20120131047A - Driving apparatus for image display device and method for driving the same - Google Patents

Abstract

PURPOSE: A driving device of an image display device and a driving method thereof are provided to improve power consumption reducing efficiency by respectively changing a driving power mode of data integrated circuits according to a temporal and spatial analyzing result of image data. CONSTITUTION: A display panel(2) includes a plurality of pixel areas. A gate driver(3) drives gate lines of a display panel. A plurality of data integrated circuits(4) drives data lines of the display panel. A timing controller(8) analyzes image data for each data line driving area. The timing controller converts the driving power mode of each data integrated circuit.

Description

DRIVING APPARATUS FOR IMAGE DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}

The present invention relates to an image display device, and in particular, by analyzing the image data displayed on the display panel in time and space and converting the driving power modes of the corresponding data integrated circuits according to the analysis result, respectively, it is possible to further improve the power consumption reduction efficiency. And a driving method of the video display device.

Recently, a flat panel type image display device has emerged as a liquid crystal display, a field emission display, a plasma display panel, a light emitting display, and the like. There is this.

The flat panel display devices are being actively applied to notebook PCs, desktop monitors, and mobile terminals due to their excellent resolution, color display, and image quality.

In recent years, flat panel type video display devices have been actively applied to portable notebook PCs or mobile terminals, and many studies have been conducted to reduce power consumption of each image display device.

Thus, in the related art, a method of reducing driving power of a display panel or driving integrated circuits has been applied when predetermined image patterns having high power consumption are preset and image data corresponding to the preset patterns are input.

However, the method of reducing power consumption through the preset image patterns can only reduce the efficiency for a very short time period in consideration of the current various usage environments. In other words, in recent years, more various Internet environments or Microsoft Office environments are displayed for a long time, so that a period in which an image having a pattern similar to a power consumption reduction pattern is displayed is further reduced, and display screens displaying long time display images are reduced in power consumption. There was a problem that the power consumption reduction efficiency was further lowered because it could not be set as a pattern.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and analyzes the image data displayed on the display panel in time and space, and converts the driving power modes of the corresponding data integrated circuits according to the analysis result to further reduce power consumption efficiency. It is an object of the present invention to provide a driving device and a driving method thereof for improving the image display device.

According to an aspect of the present invention, there is provided a driving apparatus of an image display device including: a display panel configured to display an image having a plurality of pixel areas; A gate driver driving gate lines of the display panel; A plurality of data integrated circuits driving data lines of the display panel; And a timing controller configured to analyze image data for each of a plurality of data line driving regions driven by each of the plurality of data integrated circuits and to convert driving power modes of the data integrated circuits according to the analysis result. .

The timing controller is a data aligning unit for aligning the image data from the outside in accordance with the driving of the display panel to supply the aligned image data to the respective data integrated circuit, the sorted image data for each data integrated circuit A mode setting unit for generating power mode switching signals for changing the driving power mode of each of the data integrated circuits by analyzing each horizontal line unit at least one horizontal line unit, using at least one signal from external synchronization signals Generating a data control signal and supplying it to each of the data integrated circuits; and a gate control generating a gate control signal using at least one of the synchronization signals and supplying the gate control signal to the gate driver. And a signal generator.

The mode setting unit counts the number of pixel data of a predetermined gradation level having a small visual difference in the alignment image data included in the horizontal line unit of each data integrated circuit, and compares the counted pixel data number with a preset threshold value. Thus, the power mode switching signals are generated according to the comparison result.

The mode setting unit counts the same number of gray levels between pixel data adjacent to each other in the aligned image data of each horizontal line unit of each data integrated circuit, and compares the counted number with a preset threshold value. According to the power mode switching signals are generated.

The mode setting unit generates a low power mode switching signal for driving the data integrated circuit in a low power driving power mode when the counted pixel data number is less than or equal to the preset threshold value, and the counted pixel data number When the threshold value is larger than the predetermined threshold value, a high power power mode switching signal for driving the data integrated circuit in the high power driving power mode is generated and supplied to the data integrated circuit.

In addition, a driving method of an image display apparatus according to an exemplary embodiment of the present invention for achieving the above object includes a plurality of pixel panels each including a display panel for displaying an image and a plurality of data lines for driving the data lines of the display panel. A method of driving an image display device having a data integrated circuit, the method comprising: analyzing image data for each of a plurality of data line driving regions driven by each of the plurality of data integrated circuits, and driving the respective data integrated circuits according to the analysis result And converting the power modes.

The converting the driving power mode of each of the data integrated circuits may include: aligning the image data from the outside with the driving of the display panel, and supplying the aligned image data to the respective data integrated circuits; Analyzing each of the data integrated circuits in a horizontal line unit to generate power mode switching signals for switching a driving power mode of each of the data integrated circuits in at least one horizontal line unit.

The generating of the power mode switching signals may include counting the number of pixel data having a predetermined gradation level having a small visual difference, which is included in the aligned image data of the horizontal line unit for each data integrated circuit, and counting the number of pixel data and the counted pixel data in advance. By comparing the set threshold value, the power mode switching signals are generated according to the comparison result.

The generating of the power mode switching signals may include counting the same number of gray levels between pixel data adjacent to each other in the aligned image data of the horizontal line unit of each data integrated circuit, and then counting the counted number with a preset threshold value. By comparing, the power mode switching signals are generated according to the comparison result.

The generating of the power mode switching signals may include generating a low power mode switching signal for driving the corresponding data integrated circuit in a low power driving power mode when the counted pixel data number is less than or equal to the preset threshold value. When the counted pixel data number is larger than the predetermined threshold value, a high power power mode switching signal for driving the data integrated circuit in the high power driving power mode is generated and supplied to the corresponding data integrated circuit, respectively. .

An apparatus and a driving method of an image display apparatus according to an exemplary embodiment of the present invention having the various features as described above analyze image data displayed on a display panel in time and space, respectively, and drive corresponding data integrated circuits according to the analysis result. By switching the power modes respectively, the power consumption reduction efficiency can be further improved.

1 is a configuration diagram showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating each of divided regions of a liquid crystal panel according to the data integrated circuits of FIG. 1.
3A to 3C illustrate display regions divided according to a plurality of data line driving regions of each data integrated circuit.
4 is a diagram illustrating divided display areas divided according to driving areas of data integrated circuits.
FIG. 5 is a diagram illustrating the timing controller shown in FIG. 2 in more detail.
6 is an input / output waveform diagram of the timing controller shown in FIG. 5;

Hereinafter, a driving apparatus and a driving method thereof of a video display device according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings. Here, the image display device of the present invention may be a liquid crystal display device, a field emission display device, a plasma display panel, a light emitting display device and the like.

1 is a block diagram showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention. 2 is a configuration diagram illustrating divided regions of the liquid crystal panel according to the data integrated circuits of FIG. 1.

The driving device of the large-screen liquid crystal display device shown in FIGS. 1 and 2 includes a liquid crystal panel 2 having a plurality of pixel areas to display an image; At least one gate driver 3 driving the gate lines GL1 to GLn of the liquid crystal panel 2; A plurality of data integrated circuits 4 driving the data lines DL1 to DLm of the liquid crystal panel 2; And analyzing image data for each of the plurality of data lines DL1 to DLm driving regions 1DM to 6DM driven by each of the plurality of data integrated circuits 4, and driving power of each of the data integrated circuits 4 according to the analysis result. The timing controller 8 which changes a mode is provided.

The liquid crystal panel 2 includes a thin film transistor (TFT) and a liquid crystal capacitor connected to a TFT formed in each pixel area defined by the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. (Clc). The liquid crystal capacitor Clc is constituted of a pixel electrode connected to a TFT, and a common electrode facing each other with the pixel electrode and the liquid crystal interposed therebetween. The TFT supplies the image signals from the respective data lines DL1 to DLm to the pixel electrodes in response to the scan pulses from the respective gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the image signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating layer interposed therebetween. In contrast, the storage capacitor Cst is formed by overlapping the pixel electrode with the storage line and the insulating layer interposed therebetween.

Referring to FIG. 2, the liquid crystal panel 2 may be divided into a plurality of display areas according to the plurality of data lines DL1 to DLm driving regions 1DM to 6DM respectively driven by the plurality of data integrated circuits 4. Can be. Each data integrated circuit 4 corresponds to each of the driving regions 1DM to 6DM and is provided between one side of the liquid crystal panel 2 and each source printed circuit board 5 so as to correspond to the corresponding data lines DL1 through. DLm). Here, each of the plurality of data integrated circuits 4 is mounted on the data circuit film 6 and connected between the liquid crystal panel 2 and the source printed circuit board 5.

The data circuit film 6 may be a tape carrier package (TCP) film or a chip on flexible printed circuit (COF) film. In particular, in the case of the data circuit film 6 on which the data integrated circuit 4 is mounted, the data printed circuit board 5 is attached between each source printed circuit board 5 and the liquid crystal panel 2 by a tape automated bonding (TAB) method. .

Each data integrated circuit 4 includes a data control signal from the timing controller 8, for example, a source start signal (SSP), a source shift clock (SSC), and a source output enable (SOE). The data arranged from the timing controller 8 is converted into an analog voltage, that is, an image signal using a Source Output Enable) signal. Specifically, each data integrated circuit 4 latches alignment image data input from the timing controller 8 according to the SSC, and then scan pulses are supplied to the gate lines GL1 to GLn in response to the SOE signal. Each horizontal line is supplied with one horizontal line of video signal to each of the data lines DL1 through DLm.

On the other hand, each of the data integrated circuits 4 receives the power mode switching signal from the timing controller 8, and is switched to the high power driving mode or the low power driving mode in response to the supplied mode switching signal. In other words, each of the plurality of data integrated circuits 4 is driven in a high power driving mode in which the driving current is increased by driving the amount of driving current, or in response to the power mode switching signals input in units of at least one bit. It can be driven in a drive mode. The power mode switching signal is a digital signal input in units of at least one bit, and each data integrated circuit 4 drives its output current by increasing or decreasing the amount of output current for at least one horizontal line period according to a power mode switching signal of high or low level. Switch the mode. The high power or low power driving method of the data integrated circuits 4 will be described in more detail later with reference to the accompanying driving waveform diagram.

At least one gate driver 3 may be integrally formed with the liquid crystal panel 2 in the image non-display area of the liquid crystal panel 2 or may be formed in an integrated circuit and separately provided on both sides of the liquid crystal panel 2. . The gate driver 3 sequentially drives the plurality of gate lines GL1 to GLn. Specifically, the gate driver 3 may include a gate control signal, for example, a gate start signal from the timing controller 8. Scan pulses are sequentially supplied to the gate lines GL1 to GLn using a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE) signal, and the like. . The gate low voltage is supplied to the gate lines GL1 to GLn during the period in which the scan pulse is not supplied.

The timing controller 8 may be provided in a separate control printed circuit board 10 or may be provided in the source printed circuit board 5 so that each data integrated circuit 4 may be provided according to image data and a plurality of synchronization signals from the outside. And the gate driver 3. For example, when the timing controller 8 is provided on a separate control printed circuit board 10, the timing controller 8 may include each source printed circuit board 5 and each data circuit through at least one connector and a cable. The gate 6 and the data control signal are supplied to the film 6 or the like.

The timing controller 8 arranges image data input from an external system or the like to be suitable for driving the liquid crystal panel 2 and supplies the data data to each data integrated circuit 4 in units of at least one horizontal line. In addition, the gate and data control signals are generated by using synchronization signals input from the outside, for example, dot clocks, data enable signals, and horizontal and vertical synchronization signals. Each data integrated circuit 4 and the gate integrated circuit 3 are controlled using the generated gate and data control signals.

In addition, the timing controller 8 analyzes the image data arranged in units of the at least one horizontal line in the horizontal line unit of each data integrated circuit 4 to switch the power driving mode of each data integrated circuit 4. Generate power mode switching signals for each. The power driving mode of each data integrated circuit 4 is controlled by supplying each power mode switching signal to each data integrated circuit 4.

3A to 3C illustrate display regions divided according to a plurality of data line driving regions of each data integrated circuit. 4 is a diagram illustrating divided display areas divided according to driving areas of data integrated circuits.

Referring to FIGS. 3A to 3C, in the case of recent notebook PCs or portable terminal devices, more various Internet environments or Microsoft Office environments are mainly displayed. Although each of the display screens is displayed in various ways at various gradation levels, it can be seen that gradations of the same or similar level are frequently arranged in separate display regions. In particular, it can be seen that mainly displayed screens are displayed more frequently than bright levels of gray levels. Therefore, when a specific pattern is used to reduce the power consumption of each data integrated circuit 4, it is difficult to expect the effect in a display environment having more dynamic and bright gray level representations. Accordingly, in order to improve the power consumption reduction effect of each of the data integrated circuits 4, the power consumption of the data integrated circuits 4 considering the partial display screens and corresponding to the partial screens, rather than the overall display screen, is also considered. It may be more efficient to reduce.

Referring to the Internet display screen of FIG. 4, the same or similar gradation level images are repeatedly displayed on the horizontal line indicated by I-I ', so that there are also areas (1DM and 6DM) which are only brightly displayed as a whole. There are also complex display areas 2DM to 5DM that display a large amount of text at gradation levels. In this case, an area in which the gray level of the series which cannot visually notice a large difference, for example, the bright white series or the dark black series repeatedly displays the driving power mode of the data integrated circuit 4. Even if you convert, you do not feel the difference visually. Therefore, when the driving power mode of each of the data integrated circuits 4 is converted and driven according to the gray scale change pattern of the image data displayed on every horizontal line of each display area, the power consumption is reduced. The reduction effect can be further improved. To this end, the timing controller 8 analyzes the image data arranged in at least one horizontal line unit in each horizontal line unit of each data integrated circuit 4 to switch the power driving mode of each data integrated circuit 4. Power mode switch signals are generated and output respectively.

FIG. 5 is a diagram illustrating the timing controller shown in FIG. 2 in more detail.

The timing controller 8 shown in FIG. 5 aligns the image data RGB from the outside in accordance with driving of the liquid crystal panel 2 to supply the aligned image data Data to the respective data integrated circuits 4. The data aligning unit 22 analyzes the alignment image data Data in the horizontal line units of each of the data integrated circuits 4 to determine the driving power mode of each data integrated circuit 4 in at least one horizontal line unit. The mode control unit 24 which generates the power mode switching signals FLSn for switching, and the data control signal DCS using at least one of the external synchronization signals DCLK, Vsync, Hsync, and DE. And a gate control signal (GCS) using at least one of the data control signal generator 26 and the synchronization signals DCLK, Vsync, Hsync, and DE for generating the data and supplying the same to the respective data integrated circuits 4. ) And supply it to the gate driver 6 A gate control signal generator 23 is provided.

The data aligning unit 22 generates the aligned image data Data by aligning the image data RGB from the outside in every horizontal line unit to be suitable for driving the liquid crystal panel 2, and converting the image data RGB to each data integrated circuit 4. The horizontal lines of the respective data integrated circuits 4 are divided and supplied according to the number of driving data lines.

The mode setting unit 24 analyzes the alignment image data Data in the horizontal line unit of each data integrated circuit 4 to determine the power driving mode of each data integrated circuit 4 in at least one horizontal line unit. Power mode switching signals FLSn for switching are generated and supplied to the corresponding data integrated circuits 4, respectively. In this case, the mode setting unit 24 compares the number of pixel data of a specific gradation level included in the aligned image data of the horizontal line unit of each data integrated circuit 4 with a preset threshold value, and according to the comparison result. Mode switching signals FLSn may be generated.

In addition, the mode setting unit 24 compares the same number of gray levels between pixel data adjacent to each other in the aligned image data of the horizontal line unit of each data integrated circuit 4 with a preset threshold value according to the comparison result. The power mode switch signals FLSn may be generated. The method of generating the power mode switching signal FLSn of the mode setting unit 24 will be described in more detail with reference to the accompanying waveform diagram.

The data control signal generator 26 may perform SOE using at least one of the input synchronization signals DCLK, DE, Hsync, and Vsync, for example, a data enable signal DE and a vertical synchronization signal Vsync. Generates the SSC, SSP, and POL signals that are the polarity control signals, including the signal. At this time, the data control signal generator 26 generates the POL signal by converting the voltage level of the POL signal according to the preset inversion scheme of the liquid crystal panel 2. The data control signal DCS generated in this way is supplied to the data integrated circuit 4, respectively.

The gate control signal generator 28 generates a GSP and a GSC including a GOE signal, that is, a gate control signal GCS, using at least one of the input synchronization signals DCLK, DE, Hsync, and Vsync. The generated gate control signal GCS is supplied to the gate driver 3. The gate control signal GCS is a signal for controlling the driving timing of the gate driver 6, that is, the gate driver 3 is generated so as to sequentially supply the gate-on voltage to the gate lines GL1 to GLn. Signals.

6 is an input / output waveform diagram of the timing controller shown in FIG. 5.

As shown in FIG. 6, the data aligning unit 22 arranges the image data RGB in units of horizontal lines according to the data enable signal DE of every horizontal line period. In this case, the image data RGB Are arranged in horizontal line units SD-IC1 to SD-ID6 for each data integrated circuit 4 according to the number of data integrated circuits 4. In other words, the data enable signal DE of every horizontal line period is divided into pieces according to the number of corresponding data integrated circuits 4 (for example, the number of SD-IC1 to SD-ID6), and the image data to be aligned. In addition, the data integrated circuits 4 are arranged in units of horizontal lines for each data integrated circuit 4. The aligned alignment image data Data is dividedly supplied by the horizontal lines of the data integrated circuits 4 according to the number of driving data lines of the data integrated circuits 4.

At this time, the mode setting unit 24 compares and analyzes the aligned image data Data in units of horizontal lines of each data integrated circuit 4 with a preset threshold value Ts. According to the comparative analysis result, power mode switching signals FLSn for switching the driving power mode of each of the data integrated circuits 4 are generated in units of at least one horizontal line, and each of the power mode switching signals FLSn is generated. Supply.

The mode setting unit 24 may have a predetermined gray level (eg, a gray level of a white series or a gray level of a black series) with a small visual difference included in the aligned image data of each horizontal line unit for each data integrated circuit 4. Count the number of pixel data. The power mode switch signals FLSn may be generated according to the comparison result by comparing the counted pixel data number CV with a preset threshold value Ts. Here, the mode setting unit 24 is a low power for driving the data integrated circuit 4 in a low power driving power mode when the counted pixel data number CV is less than or equal to a predetermined threshold value Ts. When the mode switching signal FLSn of power is generated and the counted pixel data number CV is larger than the preset threshold Ts, the high power for driving the data integrated circuit 4 in the high power driving power mode. The mode switching signal FLSn is generated and supplied to the data integrated circuit 4, respectively.

On the other hand, the mode setting unit 24 counts the same number of gradation levels between pixel data adjacent to each other in the aligned image data of the horizontal line unit of each data integrated circuit 4, and then presets the counted number CV in advance. The power mode switch signals FLSn may be generated according to the comparison result by comparing with the set threshold value Ts. Here, the mode setting unit 24 is a low power for driving the data integrated circuit 4 in a low power driving power mode when the counted pixel data number CV is less than or equal to a preset threshold value Ts. When the mode switching signal FLSn is generated and the counted pixel data number CV is larger than the preset threshold Ts, the high power for driving the corresponding data integrated circuit 4 in the high power driving power mode. The power mode switching signal FLSn is generated and supplied to the data integrated circuit 4, respectively.

Each data integrated circuit 4 increases or decreases the output current in at least one horizontal line period in response to the mode switching signal FLSn supplied from the mode setting unit 24 in at least one horizontal line unit. Switch the driving power mode of (L_Power) or high power (H_Power).

As shown in Table 1, as a result of experiments applying the main technical features of the present invention to a specific model, as a result of the overall consumption in a white environment with a variety of display environments that are mainly displayed recently, that is, the Internet environment or various Microsoft Office environments It can be seen that power is reduced.

Accordingly, the driving device and the driving method of the image display apparatus according to an embodiment of the present invention analyze the image data displayed on the image display panel in the horizontal line unit of each display area, and the corresponding data integrated circuit according to the analysis result By converting each of the driving power modes of (4), the power consumption can be reduced in response to the image characteristic of the space-time position.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

A display panel including a plurality of pixel areas to display an image;
A gate driver driving gate lines of the display panel;
A plurality of data integrated circuits driving data lines of the display panel; And
And a timing controller configured to analyze image data for each of a plurality of data line driving regions driven by each of the plurality of data integrated circuits and to convert driving power modes of the respective data integrated circuits according to the analysis result. Drive of display device. The method of claim 1,
The timing controller is
A data alignment unit for aligning the image data from the outside to be suitable for driving the display panel and supplying the aligned image data to the respective data integrated circuits;
A mode setting unit configured to analyze the aligned image data in units of horizontal lines for each data integrated circuit, and to generate power mode switching signals for switching a driving power mode of each data integrated circuit in units of at least one horizontal line;
A data control signal generator for generating a data control signal using at least one signal from external synchronization signals and supplying the same to the respective data integrated circuits;
And a gate control signal generator for generating a gate control signal using at least one of the synchronization signals and supplying the gate control signal to the gate driver. The method of claim 2,
The mode setting unit
The comparison result is obtained by counting the number of pixel data of a predetermined gradation level having a small visual perception difference included in the aligned image data of the horizontal line unit of each data integrated circuit, and comparing the counted pixel data number with a preset threshold value. And the power mode switching signals are generated according to the driving. The method of claim 2,
The mode setting unit
After counting the same number of gradation levels between pixel data adjacent to each other in the aligned image data of the horizontal line unit of each data integrated circuit, the counted number is compared with a preset threshold value, according to the comparison result. And a power mode switching signal. The method according to claim 3 or 4,
The mode setting unit
Generating a low power mode switching signal for driving the corresponding data integrated circuit in a low power driving power mode when the counted pixel data number is less than or equal to the preset threshold;
When the counted pixel data number is larger than the preset threshold, a high power power mode switching signal for driving the data integrated circuit in a high power driving power mode is generated and supplied to the corresponding data integrated circuit, respectively. Driving device for a video display device. A driving method of an image display apparatus including a display panel having a plurality of pixel regions to display an image and a plurality of data integrated circuits driving the data lines of the display panel, respectively.
And analyzing the image data for each of the plurality of data line driving regions respectively driven by the plurality of data integrated circuits, and converting the driving power modes of the respective data integrated circuits according to the analysis result. Driving method. The method according to claim 6,
Converting the driving power mode of each of the data integrated circuits
Supplying the aligned image data to the respective data integrated circuits by aligning the image data from the outside in accordance with driving of the display panel; and
Analyzing the sorted image data in units of horizontal lines for each data integrated circuit, and generating power mode switching signals for switching a driving power mode of each data integrated circuit in units of at least one horizontal line. A driving method of a video display device characterized in that. The method of claim 7, wherein
Generating the power mode switching signals
The comparison result is obtained by counting the number of pixel data of a predetermined gradation level having a small visual perception difference included in the aligned image data of the horizontal line unit of each data integrated circuit, and comparing the counted pixel data number with a preset threshold value. And generating the power mode switching signals according to the present invention. The method of claim 7, wherein
Generating the power mode switching signals
After counting the same number of gradation levels between pixel data adjacent to each other in the aligned image data of the horizontal line unit of each data integrated circuit, the counted number is compared with a preset threshold value, according to the comparison result. And a power mode switching signal. The method of claim 8 or 9,
Generating the power mode switching signals
Generating a low power mode switching signal for driving the corresponding data integrated circuit in a low power driving power mode when the counted pixel data number is less than or equal to the preset threshold;
When the counted pixel data number is larger than the preset threshold, a high power power mode switching signal for driving the data integrated circuit in a high power driving power mode is generated and supplied to the corresponding data integrated circuit, respectively. A method of driving a video display device.

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