KR101735398B1 - Driving apparatus for image display device and method for driving the same - Google Patents

Abstract

The present invention relates to a driving apparatus for a video display device capable of further improving power consumption reduction efficiency by analyzing video data displayed on a display panel in time and space and converting driving power modes of the data integrated circuits according to the analyzed results, And a method of driving the display panel, the display panel including a plurality of pixel regions to display an image; A gate driver for driving gate lines of the display panel; A plurality of data integration circuits for driving data lines of the display panel; And a timing controller for analyzing image data for each of a plurality of data line drive regions driven by each of the plurality of data integrated circuits and converting a drive power mode of each of the data integrated circuits according to the analysis result .

Description

TECHNICAL FIELD [0001] The present invention relates to a driving apparatus for a video display device and a driving method thereof. BACKGROUND OF THE INVENTION [0002]

In particular, the present invention relates to a video display device, and more particularly, to a video display device that analyzes video data displayed on a display panel in time and space and converts driving power modes of respective data integrated circuits according to the analysis results, And more particularly, to a driving apparatus for a video display device and a driving method thereof.

2. Description of the Related Art In recent years, flat panel display devices such as a liquid crystal display, a field emission display, a plasma display panel, and a light emitting display .

The flat panel display devices are excellent in resolution, color display and image quality, and are actively applied to notebook PCs, desktop monitors, and mobile terminals.

In recent years, flat panel display devices have been actively applied to portable notebook PCs and mobile terminals, and many studies have been conducted to reduce the power consumption of the respective image display devices.

Conventionally, a method of presetting specific image patterns with high power consumption and reducing driving power of a display panel or driving integrated circuits when image data corresponding to the preset patterns are input has been applied.

However, the method of reducing the power consumption through the preset image patterns has a reduction effect only for a very short period of time considering the present various use environments, and the efficiency is lowered. In other words, recently, a variety of Internet environments and Microsoft Office environments are displayed for a long time, so that a period of time in which an image of a pattern similar to the power consumption reduction pattern is displayed is further reduced, Pattern can not be set, and there is a problem that the power consumption reduction efficiency is further lowered.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide an image display apparatus and a data display method thereof, in which image data displayed on a display panel are analyzed in time and space, And an object of the present invention is to provide a driving apparatus for a video display device and a driving method thereof.

According to an aspect of the present invention, there is provided an apparatus for driving an image display apparatus including a display panel including a plurality of pixel regions to display an image; A gate driver for driving gate lines of the display panel; A plurality of data integration circuits for driving data lines of the display panel; And a timing controller for analyzing image data for each of a plurality of data line drive regions driven by each of the plurality of data integrated circuits and converting a drive power mode of each of the data integrated circuits according to the analysis result .

Wherein the timing controller comprises: a data arranging unit for aligning image data from outside in accordance with driving of the display panel and supplying the aligned image data to the respective data accumulating circuits; A mode setting unit for generating power mode switching signals for switching the driving power mode of each of the data integrated circuits in at least one horizontal line unit by analyzing each horizontal line unit, using at least one of synchronizing signals from outside A data control signal generator for generating a data control signal and supplying the data control signal to each of the data integrated circuits, and a gate control unit for generating a gate control signal using at least one of the synchronization signals and supplying the gate control signal to the gate driver And a signal generator.

Wherein the mode setting unit counts the number of pixel data of a predetermined gradation level in which the sensory difference included in the aligned image data per horizontal line unit for each data integration circuit is small and compares the counted number of pixel data with a predetermined threshold value And the power mode switching signals are generated according to the comparison result.

Wherein the mode setting unit counts the same number of gradation levels between pixel data adjacent to each other in the aligned image data for each horizontal line unit for each data integration circuit and then compares the counted number with a predetermined threshold value, And the power mode switching signals are generated according to the power mode switching signals.

Wherein the mode setting unit generates a low-power mode switching signal for driving the data integration circuit in a low-power driving power mode when the counted number of pixel data is less than or equal to the preset threshold value, Power mode switching signal for driving the corresponding data integrated circuit in a high-power driving power mode when the voltage is greater than the preset threshold value, and supplies the high-power mode switching signal to the corresponding data integrated circuit.

According to another aspect of the present invention, there is provided a method of driving an image display apparatus including a display panel having a plurality of pixel regions to display an image, A method of driving a video display device having a data integration circuit, comprising the steps of: analyzing image data for each of a plurality of data line drive regions driven by each of the plurality of data integration circuits; And converting the power mode.

Wherein the step of converting the driving power mode of each of the data integrated circuits comprises the steps of: arranging image data from outside in accordance with driving of the display panel and supplying the aligned image data to the respective data integrated circuits; And generating power mode switching signals for switching the driving power mode of each of the data integrated circuits in units of at least one horizontal line by analyzing each of the data lines in units of horizontal lines for each of the data integrated circuits.

Wherein the generating of the power mode switching signals includes counting the number of pixel data of a predetermined gradation level having a small difference in sensibility contained in the aligned image data of each horizontal line unit for each data integration circuit, And comparing the set threshold values, thereby generating the power mode switching signals in accordance with the comparison result.

The power mode switching signals may be generated by counting the same number of gradation levels of pixel data adjacent to each other in the aligned image data of each horizontal line unit for each data integration circuit and then setting the counted number to a predetermined threshold value And the power mode switching signals are generated according to the comparison result.

Wherein the generation of the power mode switching signals includes generating a low power mode switching signal for driving the data integrated circuit in a low power driving power mode when the counted number of pixel data is less than or equal to the predetermined threshold value, Power mode switching signals for driving the corresponding data integrated circuits in a high-power driving power mode when the number of counted pixel data is greater than the predetermined threshold value, and supplies the high-power mode switching signals to the corresponding data integrated circuits .

According to an embodiment of the present invention, there is provided a driving apparatus for a video display device and a driving method thereof, which analyze video data displayed on a display panel in time and space, The power consumption efficiency can be further improved by converting each of the power modes.

1 is a configuration diagram showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention;
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display panel.
FIGS. 3A to 3C are diagrams showing display regions divided according to a plurality of data line driving regions of each data integration circuit; FIG.
FIG. 4 is a diagram showing the divided display areas according to the driving areas of the data integrated circuits. FIG.
5 is a configuration diagram more specifically showing the timing controller shown in Fig.
6 is an input / output waveform diagram of the timing controller shown in Fig.

Hereinafter, a driving apparatus and a driving method thereof for an image display apparatus according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. Here, the video display device of the present invention may be a liquid crystal display device, a field emission display device, a plasma display panel, a light emitting display device, and the like, but the following description will be made by way of example only for a liquid crystal display device for convenience of explanation.

1 is a block diagram showing a driving apparatus of a liquid crystal display according to an embodiment of the present invention. FIG. 2 is a diagram showing the divided regions of the liquid crystal panel according to the data integrated circuits of FIG. 1. Referring to FIG.

1 and 2 includes a liquid crystal panel 2 having a plurality of pixel regions and displaying an image; At least one gate driver (3) for driving the gate lines (GL1 to GLn) of the liquid crystal panel (2); A plurality of data integration circuits 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2; And the plurality of data lines DL1 to DLm driving regions 1DM to 6DM driven by the plurality of data integrated circuits 4 and supplies the driving power of each data integration circuit 4 And a timing controller 8 for converting the mode.

The liquid crystal panel 2 includes a thin film transistor (TFT) formed in each pixel region defined by a plurality of gate lines GL1 to GLn and a plurality of data lines DL1 to DLm, and a liquid crystal capacitor (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode facing the pixel electrode and the liquid crystal. The TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the common voltage supplied to the common electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage. The storage capacitor Cst is connected in parallel to the liquid crystal capacitor Clc so that the voltage charged in the liquid crystal capacitor Clc is maintained until the next data signal is supplied. The storage capacitor Cst is formed by overlapping the pixel electrode with the previous gate line and the insulating film interposed therebetween. Alternatively, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating film interposed therebetween.

2, the liquid crystal panel 2 is divided into a plurality of display regions according to a plurality of data lines DL1 to DLm driving regions 1DM to 6DM driven by a plurality of data integrated circuits 4, respectively . Each of the data integrated circuits 4 corresponds to each of the driving regions 1DM to 6DM and is provided between one side of the liquid crystal panel 2 and each of the source printed circuit boards 5, DLm. Here, each of the plurality of data integrated circuits 4 is mounted on the data circuit film 6 and connected between the liquid crystal panel 2 and the source printed circuit board 5.

The data circuit film 6 may be a TCP (Tape Carrier Package) film or a COF (Chip On Flexible Printed Circuit) film. In particular, in the case of the data circuit film 6 on which the data integrated circuit 4 is mounted, it is attached between each source printed circuit board 5 and the liquid crystal panel 2 by a TAB (Tape Automated Bonding) method or the like .

Each data integration circuit 4 includes a data control signal from the timing controller 8 such as a source start signal SSP, a source shift clock SSC, a source output enable signal SOE (Source Output Enable) signal from the timing controller 8 into an analog voltage, that is, a video signal. Specifically, each data integration circuit 4 latches the aligned image data inputted from the timing controller 8 in accordance with the SSC, and then outputs the data to the gate lines GL1 to GLn in response to the SOE signal. And supplies video signals for one horizontal line to each of the data lines DL1 to DLm for each horizontal period.

On the other hand, each of the data integrated circuits 4 receives the power mode switching signal from the timing controller 8 and is driven to switch to the high power driving mode or the low power driving mode in response to the supplied mode switching signal. In other words, each of the plurality of data integrated circuits 4 is driven in a high-power driving mode in which the driving current amount is increased in response to the power mode switching signals input in units of at least one bit, or a low- And can be driven in a driving mode. The power mode switching signal is a digital signal inputted in at least one bit unit. Each data integrated circuit 4 is driven by increasing or decreasing the amount of output current for at least one horizontal line period in response to a high or low level power mode switching signal Mode. The high-power or low-power driving method of the data integrated circuits 4 will be described in more detail with reference to the accompanying driving waveforms.

At least one gate driver 3 may be formed in the image non-display area of the liquid crystal panel 2 integrally with the liquid crystal panel 2 or may be formed in the form of an integrated circuit separately on both sides of the liquid crystal panel 2 . The gate driver 3 sequentially drives the plurality of gate lines GL1 to GLn. Specifically, the gate driver 3 receives a gate control signal from the timing controller 8, for example, a gate start signal A scan pulse is sequentially supplied to each of the gate lines GL1 to GLn using a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable (GOE) signal or the like . A gate low voltage is supplied during a period in which no scan pulse is supplied to each of the gate lines GL1 to GLn.

The timing controller 8 may be provided on a separate control printed circuit board 10 or may be provided on the source printed circuit board 5 and may be connected to each data integration circuit 4 in accordance with video data and a plurality of synchronization signals, And the gate driver 3 are controlled. For example, when the timing controller 8 is provided on a separate control printed circuit board 10, the timing controller 8 controls each source printed circuit board 5 and each data circuit And supplies the gate and data control signals to the film 6 or the like.

The timing controller 8 arranges image data inputted from an external system or the like so as to be suitable for driving the liquid crystal panel 2 and supplies the image data to each data integration circuit 4 in units of at least one horizontal line. In addition, a gate and a data control signal are generated using synchronizing signals input from the outside, for example, a dot clock, a data enable signal, and horizontal and vertical synchronizing signals. Then, each of the data integrated circuit 4 and the gate integrated circuit 3 is controlled by using the generated gate and data control signals.

In addition, the timing controller 8 analyzes the image data arranged in units of at least one horizontal line on a horizontal line basis for each data integration circuit 4, and switches the power operation mode of each data integration circuit 4 Respectively. ≪ RTI ID = 0.0 > Then, each of the power mode switching signals is supplied to the respective data integrated circuits 4, thereby controlling the power driving modes of the respective data integrated circuits 4. [

FIGS. 3A to 3C are diagrams showing display regions divided according to a plurality of data line driving regions of each data integration circuit. FIG. FIG. 4 is a diagram showing the divided display areas according to the driving areas of the data integrated circuits.

Referring to FIGS. 3A to 3C, recently, notebook PCs and portable terminal devices mainly display various Internet environments and Microsoft Office environments. Although each of these display screens is variously displayed at various gradation levels as a whole, it can be seen that gradations of the same or similar level are frequently arranged in the display areas which are distinguished from each other. In particular, it can be seen that mainly the displayed images are displayed more frequently in the gradation levels of the bright series than in the gradation levels of the dark series. Therefore, when a specific pattern is used to reduce the power consumption of each of the data integrated circuits 4, it becomes more dynamic and it is difficult to expect the effect in a display environment in which many gradation expressions of a bright series are represented. Therefore, in order to improve the power consumption reduction effect of each data integration circuit 4, it is necessary to consider a partial display screen rather than considering the entire display screen, and to consider the power consumption of the data integration circuits 4 corresponding to the partial screens May be more efficient.

Referring to the Internet display screen of FIG. 4, there are regions 1DM and 6DM in which the same or similar gradation level images are repeatedly displayed on the horizontal line I-I ' There are also complicated display areas 2DM to 5DM that display a large amount of text with gradation levels. In this case, a gradation level of a series in which the gradation level of the series can not be appreciably visually sensed, for example, the gradation level of the bright white series or the gradation level of the dark black series is repetitively indicated is the driving power mode of the data integration circuit 4 The conversion does not feel the difference visually. Therefore, when the drive power mode of the data integrated circuits 4 is converted and driven in accordance with the gradation change pattern of the image data displayed in the drive display area of each data integration circuit 4, particularly, each horizontal line of each display area, The reduction effect can be further improved. To this end, the timing controller 8 analyzes image data arranged in units of at least one horizontal line on a horizontal line basis for each data integration circuit 4, and outputs the image data for switching the power drive mode of each data integration circuit 4 And generates and outputs power mode switching signals, respectively.

5 is a block diagram showing the timing controller shown in Fig. 2 in more detail.

The timing controller 8 shown in Fig. 5 arranges video data RGB from outside in accordance with driving of the liquid crystal panel 2 and supplies the aligned video data Data to the respective data integrating circuits 4 The data sorting unit 22 analyzes the alignment image data Data in units of horizontal lines for each of the data integration circuits 4 to determine a driving power mode of each data integration circuit 4 in at least one horizontal line unit A mode setting unit 24 for generating power mode switching signals FLSn for switching and a data control signal DCS using at least one of synchronizing signals DCLK, Vsync, Hsync, And a data control signal generator 26 for generating a gate control signal GCS using at least one of the synchronization signals DCLK, Vsync, Hsync and DE, ) And supplies it to the gate driver 6 And a gate control signal generator 23.

The data sorting unit 22 arranges the image data RGB from the outside in units of horizontal lines in accordance with the driving of the liquid crystal panel 2 to generate aligned image data Data, In accordance with the number of the driving data lines of the respective data integrated circuits 4.

The mode setting unit 24 analyzes the alignment image data Data in units of horizontal lines for each of the data integration circuits 4 and outputs the power drive mode of each of the data integration circuits 4 in units of at least one horizontal line Generates power mode switching signals (FLSn) for switching and supplies them to the corresponding data integration circuit (4). At this time, the mode setting unit 24 compares the number of pixel data of the specific gradation level included in the aligned image data in the horizontal line unit for each data integration circuit 4 with a predetermined threshold value, And can generate the mode switching signals FLSn.

The mode setting unit 24 compares the same number of gradation levels between pixel data adjacent to each other in the aligned image data in units of horizontal lines for each data integration circuit 4 with a preset threshold value, And may generate the power mode switching signals FLSn. A method of generating the power mode switching signal FLSn of the mode setting unit 24 will be described in more detail with reference to the accompanying waveform diagrams.

The data control signal generating unit 26 generates at least one of the input synchronizing signals DCLK, DE, Hsync and Vsync by using the data enable signal DE and the vertical synchronizing signal Vsync, An SSC including a signal, an SSP, and a polarity control signal POL. At this time, the data control signal generator 26 converts the voltage level of the POL signal according to the preset inversion method of the liquid crystal panel 2 to generate the data signal. The data control signal DCS thus generated is supplied to the data integration circuit 4, respectively.

The gate control signal generator 28 generates a GSP and a GSC including a GOE signal, that is, a gate control signal (GCS) using at least one of the input synchronization signals DCLK, DE, Hsync, and Vsync, And supplies the generated gate control signal GCS to the gate driver 3. The gate control signal GCS is generated so that the gate driver 3 can sequentially supply the gate-on voltage to the gate lines GL1 to GLn, that is, a signal for controlling the driving timing of the gate driver 6 Signals.

6 is an input / output waveform diagram of the timing controller shown in Fig.

6, the data arrangement unit 22 arranges the image data RGB in every horizontal line according to the data enable signal DE of each horizontal line period. At this time, (SD-IC1 to SD-ID6) for each data integration circuit 4 according to the number of the data integration circuits 4. [ In other words, the data enable signal DE of each horizontal line period is segmented according to the number of the data integrated circuits 4 (for example, the number of SD-IC1 to SD-ID6) And are arranged in units of horizontal lines for each data integration circuit 4 according to the number of data integration circuits 4. [ The alignment image data (Data) thus aligned is divided and supplied in units of horizontal lines of each data integration circuit 4 according to the number of drive data lines of each data integration circuit 4. [

At this time, the mode setting unit 24 compares and analyzes the aligned image data Data in units of horizontal lines for each data integration circuit 4 with a preset threshold value Ts. And generates power mode switching signals FLSn for switching the driving power modes of the respective data integrated circuits 4 in units of at least one horizontal line according to a result of the comparison analysis and supplies the power mode switching signals FLSn to the corresponding data integration circuit 4 Supply.

The mode setting unit 24 sets a predetermined gradation level (for example, a gradation level of a white series or a gradation level of a black series, which is included in the aligned image data of each horizontal line unit for each data integration circuit 4) Is counted. Then, the power mode switching signals FLSn can be generated according to the comparison result by comparing the counted number of pixel data CV with a preset threshold value Ts. Here, when the number of counted pixel data (CV) is less than or equal to a preset threshold value (Ts), the mode setting unit (24) sets a mode for driving the corresponding data integrated circuit (4) in a low- And generates a mode switching signal FLSn of a high power for driving the data integration circuit 4 in a high power driving power mode when the counted number of pixel data CV is larger than a preset threshold value Ts Generates the mode switching signal FLSn, and supplies the mode switching signal FLSn to the data integration circuit 4, respectively.

On the other hand, the mode setting unit 24 counts the same number of gradation levels of pixel data adjacent to each other in the aligned image data of each horizontal line unit for each data integration circuit 4, It is possible to generate the power mode switching signals FLSn according to the comparison result by comparing the power mode switching signals FLSn with the set threshold value Ts. Here, when the counted number of pixel data CV is less than or equal to a preset threshold value Ts, the mode setting unit 24 sets the low power mode for driving the data integration circuit 4 in the low power driving power mode When the counted number of pixel data CV is larger than a preset threshold value Ts, the mode switching signal FLSn is generated and the high-power Generates power mode switching signal FLSn, and supplies it to corresponding data integration circuit 4, respectively.

Each data integration circuit 4 responds to the mode switching signal FLSn supplied in units of at least one horizontal line from the mode setting unit 24 to increase or decrease the output current amount in units of at least one horizontal line period, (L_Power) or high power (H_Power).

As shown in the following Table 1, the main technical features of the present invention are applied to a specific model. As a result, it has been found that a variety of display environments, such as the Internet environment and various Microsoft office environments, It can be seen that the power is reduced.

Accordingly, in the driving apparatus and the driving method of the video display apparatus according to the embodiment of the present invention, the video data displayed on the video display panel are analyzed in units of horizontal lines of each display region, The power consumption modes can be reduced corresponding to the image characteristics of the temporal and spatial positions.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

A display panel having a plurality of pixel regions to display an image;
A gate driver for driving gate lines of the display panel;
A plurality of data integration circuits for driving data lines of the display panel; And
And a timing controller for analyzing image data for each of a plurality of data line drive regions driven by each of the plurality of data integrated circuits and converting a drive power mode of each of the data integrated circuits according to the analysis result A driving device for a display device,
The timing controller
A data arrangement unit for arranging image data from outside in accordance with driving of the display panel and supplying the sorted image data to the respective data integration circuits,
A mode setting unit for generating power mode switching signals for switching the driving power mode of each of the data integrated circuits in units of at least one horizontal line by analyzing the aligned image data in units of horizontal lines for each of the data integrated circuits,
A data control signal generating unit for generating a data control signal using at least one of synchronous signals from outside and supplying the data control signal to each of the data integrated circuits,
And a gate control signal generator for generating a gate control signal using at least one of the synchronization signals and supplying the gate control signal to the gate driver,
The mode setting unit
Counting the number of pixel data having the same gradation level between pixel data adjacent to each other in the aligned image data for each horizontal line unit for each data integration circuit and comparing the counted number of pixel data with a preset threshold value, And the power mode switching signals are generated according to the power mode switching signals. delete delete delete The method according to claim 1,
The mode setting unit
Generates a low-power mode switching signal for driving the data integrated circuit in a low-power driving power mode when the counted number of pixel data is less than or equal to the preset threshold value,
Power mode switching signal for driving the corresponding data integrated circuit in a high-power driving power mode when the number of counted pixel data is greater than the predetermined threshold value, and supplies the high-power mode switching signal to the corresponding data integrated circuit, respectively And a driving circuit for driving the video display device. A method of driving a video display device having a display panel having a plurality of pixel regions and displaying an image, and a plurality of data integrated circuits driving data lines of the display panel,
Analyzing image data for each of a plurality of data line drive regions driven by each of the plurality of data integrated circuits and converting a drive power mode of each of the data integrated circuits according to the analysis result,
The step of converting the driving power mode of each of the data integrated circuits
Arranging image data from outside in accordance with driving of the display panel and supplying the sorted image data to the respective data integrated circuits, and
And generating power mode switching signals for switching the driving power mode of each of the data integrated circuits in units of at least one horizontal line by analyzing the aligned image data in units of horizontal lines for each of the data integrated circuits ,
The step of generating the power mode switching signals
Counting the number of pixel data having the same gradation level between pixel data adjacent to each other in the aligned image data for each horizontal line unit for each data integration circuit and comparing the counted number of pixel data with a preset threshold value, And the power mode switching signals are generated according to the power mode switching signals. delete delete delete The method according to claim 6,
The step of generating the power mode switching signals
Generates a low-power mode switching signal for driving the data integrated circuit in a low-power driving power mode when the counted number of pixel data is less than or equal to the preset threshold value,
Power mode switching signal for driving the corresponding data integrated circuit in a high-power driving power mode when the number of counted pixel data is greater than the predetermined threshold value, and supplies the high-power mode switching signal to the corresponding data integrated circuit, respectively And a driving method of the video display device.

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