KR20100037903A - Method for fabricaing semiconductor device - Google Patents

Method for fabricaing semiconductor device Download PDF

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Publication number
KR20100037903A
KR20100037903A KR1020080097241A KR20080097241A KR20100037903A KR 20100037903 A KR20100037903 A KR 20100037903A KR 1020080097241 A KR1020080097241 A KR 1020080097241A KR 20080097241 A KR20080097241 A KR 20080097241A KR 20100037903 A KR20100037903 A KR 20100037903A
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South Korea
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epitaxial silicon
silicon layer
semiconductor device
layer
ion implantation
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KR1020080097241A
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Korean (ko)
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안태항
오재근
전승준
이영호
주민애
백승범
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주식회사 하이닉스반도체
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Priority to KR1020080097241A priority Critical patent/KR20100037903A/en
Publication of KR20100037903A publication Critical patent/KR20100037903A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The present invention is to provide a method for manufacturing a semiconductor device that can prevent the generation of facets (Facet) when forming the epitaxial silicon germanium layer, the present invention comprises the steps of forming a plurality of gate patterns on the substrate; Forming an epitaxial silicon layer in the source / drain regions on the substrate; Including the step of implanting germanium into the epitaxial silicon layer, by forming an epitaxial silicon germanium layer by ion implantation after forming the epitaxial silicon layer, the effect of preventing the generation of facets, cells After forming the epitaxial silicon layer in both the region and the peripheral region at the same time, by selectively ion implantation to form the epitaxial silicon germanium layer, process margins can be secured rather than dividing the epitaxial layer separately. There is an effect that can improve the device characteristics by improving the imbalance of the dopant profile by the facet by preventing the effect and the occurrence of facets.

Silicon, Ion Implantation, SiGe

Description

Semiconductor device manufacturing method {METHOD FOR FABRICAING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of manufacturing a semiconductor device having an ESD.

As a design rule of a semiconductor device decreases, a short channel effect (SCE) occurs, and thus device characteristics deteriorate as a whole, such as a sudden decrease in a threshold voltage of the device.

To address this, an elevated source / drain (ESD) process is being applied. ESD grows epitaxial-silicon to a certain thickness on the substrate of the cell and the peripheral (circuit) region, and mainly uses the ion implantation process, and the junction and the source / drain regions of the cell region By forming the epitaxial-silicon, the effect of the short channel effect is greatly reduced, as well as the shallow junction effect.

Meanwhile, as devices continue to be highly integrated, there is a need to increase mobility of carriers and increase on-current of devices in NMOS as well as PMOS channels.

Currently, NMOS mainly adopts spacer nitride, which applies tensile stress to the channel, and epitaxial silicon-germanium layer, which applies compressive stress, to the channel. (Operation Current) is improving.

1 is a TEM photograph for explaining a semiconductor device according to the prior art.

As shown in FIG. 1, it can be seen that an epitaxial silicon germanium layer (Silicon Germanium_Selective Epitaxial Growth) is formed in the source / drain regions between the gate patterns. In the case of PMOS, when the epitaxial silicon germanium layer is formed in the source / drain region to form the ESD, the compressive stress is applied to the channel and the operating current of the device can be improved.

However, in the case of the epitaxial silicon germanium layer, there is a problem in that facets are severely generated in a portion adjacent to the gate pattern. Facets not only affect the stress on the channel, but also affect the distribution of stress. In addition, in the subsequent ion implantation process for the epitaxial silicon germanium layer, a serious imbalance of the dopant profile is caused, which makes it difficult to secure normal device characteristics.

Therefore, when the epitaxial silicon layer is used for the PMOS of the device, it is necessary to improve such facets.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device capable of preventing the generation of facets during the formation of the epitaxial silicon germanium layer.

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming a plurality of gate patterns on a substrate; Forming an epitaxial silicon layer in the source / drain regions on the substrate; And implanting germanium into the epitaxial silicon layer.

In particular, the ion implantation of the germanium proceeds to tilt ion implantation, but proceeds to 1 ° to 30 ° based on the sidewall of the gate pattern, and 1.0 × 10 14 atoms / cm 2 to 5.0 × 10 18 atoms It is characterized by advancing with a dose of / cm 2 and an energy of 20keV to 80keV.

In addition, the epitaxial silicon layer is characterized by being formed in a thickness of 300 Pa to 2000 Pa at a temperature of 600 ℃ to 900 ℃.

In addition, the epitaxial silicon layer may be formed of a doped doped with impurities in an undoped or in-situ manner.

In addition, when the epitaxial silicon layer is undoped, the method may further include ion implanting impurities into the epitaxial silicon layer before the ion implantation of germanium.

In addition, the impurities are characterized in that it comprises a boron or boron-based compound.

In addition, the substrate is characterized in that the PMOS of the peripheral region.

The semiconductor device manufacturing method according to the present invention described above has an effect of preventing the generation of facets by forming the epitaxial silicon germanium layer by ion implantation after forming the epitaxial silicon layer.

In addition, the epitaxial silicon layer is simultaneously formed in both the cell region and the peripheral region, and then only the peripheral region is selectively implanted to form an epitaxial silicon germanium layer, thereby forming a process margin rather than dividing the epitaxial layer. There is an effect that can be secured.

In addition, it is possible to improve the device characteristics by preventing the occurrence of facets to improve the imbalance of the dopant profile by the facets.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

(Example 1)

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

As shown in FIG. 2A, a gate pattern 12 is formed on the substrate 11. The substrate 11 may be a semiconductor substrate undergoing a DRAM process, and in particular, may be a substrate of a PMOS region.

Before forming the gate pattern 12, a gate insulating film (not shown) may be formed. The gate insulating film is for insulating between the gate pattern 12 and the substrate 11 and may be formed of an oxide film. The oxide film may be formed of a thermal oxide film or a plasma oxide film.

The gate pattern 12 may have a stacked structure of the first electrode 12A, the second electrode 12B, and the gate hard mask 12C. In addition, the first electrode 12A may include polysilicon, the second electrode 12B may include tungsten or tungsten silicide, and the gate hard mask 12C may include a nitride film.

Subsequently, the gate spacer 13 is formed on the sidewall of the gate pattern 12. The gate spacer 13 is to protect the sidewall of the gate pattern 12 in a subsequent process, and forms an insulating film on the entire structure including the gate pattern 12, and performs full surface etching to form the gate pattern 12. It can be formed by remaining on the side wall. The gate spacer 13 may be formed of any one selected from a nitride film or a stacked structure of an oxide film and a nitride film or a stacked structure of an oxide film, a nitride film, and an oxide film.

Subsequently, a pretreatment process is performed on both substrates 11 of the gate pattern 12. The pretreatment process is to remove the by-products and the natural oxide film formed on the substrate 11 after the gate pattern 12 is etched. The pretreatment process may be performed by wet cleaning, dry cleaning, or mixing wet and dry cleaning.

If the pretreatment process proceeds to wet cleaning, it can be carried out using HF series solutions. When the pretreatment process is carried out by dry cleaning, it may be carried out in any one atmosphere selected from the group consisting of a mixed gas of hydrogen, hydrogen and nitrogen, CF gas, NF gas and NH gas. In addition, it may be carried out by any one process selected from the group consisting of a plasma process, a thermal process and a rapid heat treatment process.

The pretreatment step can proceed at a temperature of 30 ° C to 900 ° C.

As shown in FIG. 2B, an epitaxial silicon layer 14 is formed on the substrate 11 between the gate patterns 12. The epitaxial silicon layer 14 may be formed using selective epitaxial growth.

The epitaxial silicon layer 14 may include low pressure chemical vapor deposition (LPCVD), very low pressure CVD (VLPCVD), plasma enhanced CVD (PE-CVD), ultrahigh vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), and APCVD (APCVD). Atmosphere Pressure CVD) and MBE (Molecular Beam Epitaxy) can be formed in any one device selected from the group consisting of.

The epitaxial silicon layer 14 may be formed under a condition in which facets are minimized, and may be formed in a thickness of 300 kPa to 2000 kPa at a temperature of 600 ° C to 900 ° C. In addition, the epitaxial silicon layer 14 may be formed as a doped undoped or doped in an in-situ manner.

When the substrate 11 is a PMOS, the impurities may include P-type impurities. P-type impurities may include, for example, boron or boron-based compounds.

In the case where the epitaxial silicon layer 14 is formed of doped, the concentration of the dopant is preferably adjusted to 1.0 × 10 17 atoms / cm 3 to 1.0 × 10 21 atoms / cm 3.

In the case where the epitaxial silicon layer 14 is undoped, a subsequent ion implantation process can be performed, with the ion implantation dose being 1.0 × 10 13 atoms / cm 2 to 1.0 × 10 16 atoms / cm 2. It is desirable to adjust. In this case, the dopant used in the ion implantation process may include boron or boron-based compounds.

In the case of the epitaxial silicon layer 14, since it is possible to grow uniformly to the vicinity of the gate pattern 12, no facet occurs. This will be described later in detail with reference to FIG. 4.

As shown in FIG. 2C, germanium (Ge) is ion-implanted into the epitaxial silicon layer 14 (see FIG. 2B) to convert the epitaxial silicon layer 14 into an epitaxial silicon germanium layer 14A.

Ion implantation of germanium (Ge) may be selectively performed only in the region adjacent to the gate pattern 12, that is, adjacent to the channel region, and for this purpose, tilt ion implantation may be performed. By ion implanting germanium into the epitaxial silicon layer 14 adjacent to the channel region in a tilting manner, the epitaxial silicon germanium layer 14A may be locally formed only in the ion implanted portion. In this case, the tilt is preferably adjusted to be 1 ° to 30 ° based on the sidewall of the gate pattern 12.

When compressive stress is applied to the channel through the epitaxial silicon germanium layer 14A, the germanium content in the film must be at least 20%. For this purpose, germanium is 1.0 × 10 14 atoms / cm 2 to 5.0 × 10 18 atoms It is preferable to perform ion implantation by adjusting to a dose of / cm 2. In addition, the ion implantation energy is preferably adjusted in the range of 20keV to 80keV.

As described above, after forming the epitaxial silicon layer 14 on the substrate 11 without forming the epitaxial silicon germanium layer 14A, the epitaxial silicon germanium layer 14A is locally formed through ion implantation. By this, generation of facets can be prevented. Therefore, the device characteristics can be improved by improving the stress change applied to the channel by the facet, the distribution of the stress, and the imbalance of the dopant profile in the ion implantation process.

In addition, since the epitaxial silicon germanium layer 14A is formed in the portion adjacent to the channel region, sufficient compressive stress can be applied to the channel region, thereby improving mobility of the carrier and operating current of the device. -current) is possible.

(Example 2)

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

As shown in FIG. 3A, a gate pattern 22 is formed on a substrate 21 having a cell region and a peripheral (circuit) region. The substrate 21 may be a semiconductor substrate in which a DRAM process is performed, and the peripheral region has an NMOS and a PMOS. In particular, the second embodiment of the present invention will be described assuming a PMOS of the peripheral region.

Before forming the gate pattern 22, an isolation layer may be formed on the substrate 21 to define an active region, and a gate insulating layer (not shown) may be formed on the substrate 21. The gate insulating film is for insulating between the gate pattern 22 and the substrate 21 and may be formed of an oxide film. The oxide film may be formed of a thermal oxide film or a plasma oxide film.

The gate pattern 22 may have a stacked structure of the first electrode 22A, the second electrode 22B, and the gate hard mask 22C. In addition, the first electrode 22A may include polysilicon, the second electrode 22B may include tungsten or tungsten silicide, and the gate hard mask 22C may include a nitride film. In particular, the cell region and the peripheral region have different densities and line widths of the gate pattern 22.

Subsequently, a gate spacer 23 is formed on the sidewall of the gate pattern 22. The gate spacer 23 is to protect the sidewall of the gate pattern 22 in a subsequent process. An insulating layer is formed on the entire structure including the gate pattern 22, and the entire surface is etched to form the gate pattern 22. It can be formed by remaining on the side wall. The gate spacer 23 may be formed of any one selected from a nitride film, a stacked structure of an oxide film and a nitride film, or a stacked structure of an oxide film, a nitride film, and an oxide film.

Subsequently, a pretreatment process is performed on both substrates 21 of the gate pattern 22. The pretreatment process is to remove the by-products and the natural oxide film formed on the substrate 21 after the gate pattern 22 is etched, and may be performed by wet cleaning, dry cleaning, or mixing wet and dry cleaning.

If the pretreatment process proceeds to wet cleaning, it can be carried out using HF series solutions. When the pretreatment process is carried out by dry cleaning, it may be carried out in any one atmosphere selected from the group consisting of a mixed gas of hydrogen, hydrogen and nitrogen, CF gas, NF gas and NH gas. In addition, it may be carried out by any one process selected from the group consisting of a plasma process, a thermal process and a rapid heat treatment process.

The pretreatment step can proceed at a temperature of 30 ° C to 900 ° C.

As shown in FIG. 3B, an epitaxial silicon layer 24 is formed on the substrate 21 between the gate patterns 22. The epitaxial silicon layer 24 may be formed using selective epitaxial growth.

The epitaxial silicon layer 24 includes low pressure chemical vapor deposition (LPCVD), very low pressure CVD (VLPCVD), plasma enhanced CVD (PE-CVD), ultrahigh vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), and APCVD (APCVD). Atmosphere Pressure CVD) and MBE (Molecular Beam Epitaxy) can be formed in any one device selected from the group consisting of.

The epitaxial silicon layer 24 may be formed under a condition in which facets are minimized, and may be formed in a thickness of 300 kPa to 2000 kPa at a temperature of 600 ° C to 900 ° C. In addition, the epitaxial silicon layer 24 may be formed of an undoped or doped dopant in an in-situ manner.

In the case where the epitaxial silicon layer 24 is formed of doped, the concentration of the dopant is preferably adjusted to 1.0 × 10 17 atoms / cm 3 to 1.0 × 10 21 atoms / cm 3.

In the case where the epitaxial silicon layer 24 is undoped, a subsequent ion implantation process may be performed, with the ion implantation dose being 1.0 × 10 13 atoms / cm 2 to 1.0 × 10 16 atoms / cm 2. It is desirable to adjust.

The impurities implanted into the epitaxial silicon layer 24 when doped or undoped may include N-type impurities. N-type impurities may include phosphorus (P) or arsenic (As). When the substrate 21 in the peripheral region is a PMOS, the epitaxial silicon layer 24 may be formed, and then P-type impurities may be selectively doped into the epitaxial silicon layer 24 in the peripheral region. . In this case, the P-type impurities may include boron or boron-based compounds. Counter doping may be selectively performed only in the peripheral region after forming a photoresist pattern (not shown) that opens the substrate 21 in the peripheral region.

In the case of the epitaxial silicon layer 24, since it is possible to grow uniformly adjacent to the gate pattern 22, no facet occurs. This will be described later in detail with reference to FIG. 4.

As shown in FIG. 3C, a photoresist pattern 25 is formed on the epitaxial silicon layer 24 and the gate pattern 22 of the cell region to open the peripheral region. The photoresist layer pattern 25 may be formed by forming a photoresist layer having a thickness higher than the height of the gate pattern 22 to sufficiently protect the cell region during subsequent ion implantation on the entire structure, and patterning the peripheral region to be opened by exposure and development. have.

Subsequently, germanium (Ge) is ion-implanted into the epitaxial silicon layer 24 in the peripheral region, thereby changing the epitaxial silicon layer 24 to the epitaxial silicon germanium layer 24A. This is because, in the case of PMOS in the peripheral region, the carrier mobility and the operating current can be increased only by applying a compressive stress to the channel. In addition, in the case of the NMOS cell region, a tensile stress must be applied to form the photosensitive film pattern 25 as the ion implantation barrier layer so that the epitaxial silicon layer 24 is maintained as it is.

Ion implantation of germanium (Ge) may be selectively performed only in the region adjacent to the gate pattern 22, that is, adjacent to the channel region, and for this purpose, tilt ion implantation may be performed. By implanting germanium in a tilting manner into the epitaxial silicon layer 24 adjacent to the channel region, the epitaxial silicon germanium layer 24A may be locally formed only in the ion implanted portion. In this case, the tilt is preferably adjusted to be 1 ° to 30 ° based on the sidewall of the gate pattern 22.

When compressive stress is applied to the channel through the epitaxial silicon germanium layer 24A, the germanium content in the film should be at least 20% or more. For this purpose, germanium is 1.0 × 10 14 atoms / cm 2 to 5.0 × 10 18 atoms It is preferable to perform ion implantation by adjusting to a dose of / cm 2. In addition, the ion implantation energy is preferably adjusted in the range of 20keV to 80keV.

As described above, after forming the epitaxial silicon layer 24 on the substrate 21 in the peripheral region without forming the epitaxial silicon germanium layer 24A directly, the epitaxial silicon germanium layer 24A is locally formed through ion implantation. ) Can be prevented from occurring. Therefore, the device characteristics can be improved by improving the stress change applied to the channel by the facet, the distribution of the stress, and the imbalance of the dopant profile in the ion implantation process.

In addition, since the epitaxial silicon germanium layer 24A is formed in the portion adjacent to the channel region, sufficient compressive stress can be applied to the channel region, thereby improving mobility of the carrier and operating current of the device. -current) is possible.

In addition, since the epitaxial silicon layer 24 is formed at once without dividing the cell region and the peripheral region, it is possible to reduce the process steps in which the formation of each epitaxial layer and the ion implantation process should be performed, thereby securing a process margin. can do.

In particular, when the substrate 21 in the peripheral region is a PMOS, P is not applied to the epitaxial silicon layer 24 doped with N-type impurities before the ion implantation of germanium in FIG. 3C without counter-doping in FIG. 3B. Counter doping may be performed. In this case, since two ion implantation processes may be performed by one mask process, process margins may be further secured.

As shown in FIG. 3D, the photosensitive film pattern 25 is removed. The photoresist pattern 25 may be removed by dry etching, and the dry etching may be performed by an oxygen strip process.

Subsequently, an interlayer insulating film 26 is formed on the epitaxial silicon layer 24 and the epitaxial silicon germanium layer 24A to fill the gate pattern 22. The interlayer insulating film 26 is for insulating between the gate patterns 22 and for insulating the upper layer, and after forming an oxide film having a thickness higher than the height of the gate pattern 22 to sufficiently fill the gaps between the gate patterns 22, the gate The upper surface of the pattern 22 may be formed by planarizing the target. Planarization may be carried out by an etch back or chemical mechanical polishing process.

Subsequently, a mask pattern 27 is formed on the interlayer insulating film 26. The mask pattern 27 may be formed by coating a photoresist on the interlayer insulating layer 26 and patterning the photoresist to open the landing plug contact region by exposure and development. In addition, a hard mask may be further formed before the photoresist layer is formed in order to secure an etching margin that may be insufficient with the photoresist layer alone.

As shown in FIG. 3E, the self-aligned contact etching (SAC) is performed using the mask pattern 27 as an etch barrier. Accordingly, the interlayer insulating layer 26 of the cell region is etched to form a landing plug contact hole 28 that opens the epitaxial silicon layer 24. The self-aligned contact etching is to selectively etch only the interlayer insulating film 26, which is an oxide film, by using a selectivity ratio between the oxide film and the nitride film in order to solve the problem that patterning becomes difficult due to the high integration of the device.

The epitaxial silicon layer 24 can then be subjected to a pretreatment step.

As shown in FIG. 3F, the mask pattern 27 is removed. When the mask pattern 27 is a photoresist pattern, it may be removed by dry etching, and the dry etching may be performed by an oxygen strip process.

Subsequently, a conductive material is embedded on the epitaxial silicon layer 24 to form a landing plug contact 29.

Specifically, in order to form the landing plug contact 29, first, a conductive material such as polysilicon or a metal material that fills the gate pattern 22 is formed on the epitaxial silicon layer 24, and then the gate pattern is formed. The landing plug contact 29 may be formed by planarizing the target to which the upper portion of the 22 is exposed. Planarization can be done by etch back or chemical mechanical polishing processes.

In particular, when the stack structure of the epitaxial silicon layer 24 and the metal material is formed as the landing plug contact 29, the first metal material along the step is formed on the entire surface of the substrate 21 including the landing plug contact hole 28. To form a metal silicide by reacting the epitaxial silicon layer 24 with the first metal material to form a metal silicide, forming a barrier metal on the metal silicide, and forming a gate pattern on the barrier metal. The second metal material may be formed to fill the gaps. In this case, the first metal material may be any one selected from the group consisting of titanium (Ti), cobalt (Co), and nickel (Ni), and the barrier metal may be a titanium nitride film (TiN) or a tungsten nitride film (ＷN). The second metal material may be tungsten.

As described above, when the landing plug contact 29 is formed in a stacked structure of the epitaxial silicon layer 24 and polysilicon or a metal material, the contact resistance may be reduced.

Figure 4 is a TEM photograph for explaining the epitaxial silicon layer according to an embodiment of the present invention.

As shown in FIG. 4, when the epitaxial silicon layer is formed between the gate patterns, it can be seen that the epitaxial silicon germanium layer is formed without facets, unlike the epitaxial silicon germanium layer of FIG. 1. Therefore, the device characteristics can be improved by improving the stress change applied to the channel by the facet, the distribution of the stress, and the imbalance of the dopant profile in the ion implantation process.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a TEM photograph for explaining SiGe_SEG according to the prior art;

2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention;

3A to 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention;

4 is a TEM photograph for explaining Si_SEG according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

11: substrate 12: gate pattern

13: gate spacer 14: Si_SEG

Claims (20)

Forming a plurality of gate patterns on the substrate; Forming an epitaxial silicon layer in the source / drain regions on the substrate; And Implanting germanium into the epitaxial silicon layer A semiconductor device manufacturing method comprising a. The method of claim 1, Injecting the germanium ion, A semiconductor device manufacturing method that proceeds by tilt ion implantation. The method of claim 2, And the tilt ion implantation proceeds to be 1 ° to 30 ° with respect to the sidewall of the gate pattern. The method of claim 1, Injecting the germanium ion, A method for manufacturing a semiconductor device, which proceeds with a dose of 1.0 × 10 14 atoms / cm 2 to 5.0 × 10 18 atoms / cm 2. The method of claim 1, Injecting the germanium ion, The semiconductor device manufacturing method which advances with the energy of 20 keV-80 keV. The method of claim 1, The epitaxial silicon layer is formed at a temperature of 600 ° C to 900 ° C. The method of claim 1, The epitaxial silicon layer is a semiconductor device manufacturing method to form a thickness of 300 GPa to 2000 GPa. The method of claim 1, The epitaxial silicon layer is formed of a doped (doped) doped with impurities in an undoped (In-Situ) method. The method of claim 8, When the epitaxial silicon layer is formed undoped, Before the ion implantation of germanium, Implanting impurities into the epitaxial silicon layer A semiconductor device manufacturing method further comprising. 10. The method according to claim 8 or 9, The impurity is a semiconductor device manufacturing method comprising a boron or boron-based compound. The method of claim 1, And the substrate is a PMOS in a peripheral region. Forming a plurality of gate patterns on a substrate having a cell region and a peripheral region; Forming an epitaxial silicon layer in the source / drain regions on the substrate; And Implanting germanium into the epitaxial silicon layer of the peripheral region A semiconductor device manufacturing method comprising a. The method of claim 12, Injecting the germanium ion, A semiconductor device manufacturing method that proceeds by tilt ion implantation. The method of claim 13, And the tilt ion implantation proceeds to be 1 ° to 30 ° with respect to the sidewall of the gate pattern. The method of claim 12, Injecting the germanium ion, A method for manufacturing a semiconductor device, which proceeds with a dose of 1.0 × 10 14 atoms / cm 2 to 5.0 × 10 18 atoms / cm 2. The method of claim 12, Injecting the germanium ion, The semiconductor device manufacturing method which advances with the energy of 20 keV-80 keV. The method of claim 12, The epitaxial silicon layer is formed at a temperature of 600 ° C to 900 ° C. The method of claim 12, The epitaxial silicon layer is a semiconductor device manufacturing method to form a thickness of 300 GPa to 2000 GPa. The method of claim 12, The epitaxial silicon layer is formed of a doped (doped) doped with impurities in an undoped (In-Situ) method. The method of claim 12, And a peripheral region of the substrate is a PMOS.
KR1020080097241A 2008-10-02 2008-10-02 Method for fabricaing semiconductor device KR20100037903A (en)

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