KR20100013137A - Shallow trench isolation in semiconductor and the method of forming the same - Google Patents

Shallow trench isolation in semiconductor and the method of forming the same Download PDF

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Publication number
KR20100013137A
KR20100013137A KR1020080074671A KR20080074671A KR20100013137A KR 20100013137 A KR20100013137 A KR 20100013137A KR 1020080074671 A KR1020080074671 A KR 1020080074671A KR 20080074671 A KR20080074671 A KR 20080074671A KR 20100013137 A KR20100013137 A KR 20100013137A
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KR
South Korea
Prior art keywords
nitride film
forming
trench
semiconductor substrate
layer
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KR1020080074671A
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Korean (ko)
Inventor
신동원
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주식회사 동부하이텍
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Priority to KR1020080074671A priority Critical patent/KR20100013137A/en
Publication of KR20100013137A publication Critical patent/KR20100013137A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

Abstract

A device isolation film formation method of a semiconductor device is provided. The method of forming an isolation layer may include forming a first nitride film on a semiconductor substrate, forming a hard mask on the first nitride film, and sequentially using the first nitride film and the semiconductor substrate using the hard mask as an etching mask. Etching to form a first nitride film pattern on the semiconductor substrate, forming a trench in the semiconductor substrate, removing the hard mask, and forming a second nitride film on an entire surface of the semiconductor substrate on which the first nitride film pattern and the trench are formed. Forming a charge trap layer between the semiconductor substrate and the gapped oxide layer by forming a gap fill gap between the semiconductor substrate and the gapped oxide layer by forming a gap fill gap in the trench in which the second nitride layer is formed; Include.

Description

Device isolation film of a semiconductor device and a method of forming the same {Shallow Trench Isolation in semiconductor and the method of forming the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method for forming a device isolation film.

Current semiconductor manufacturing technologies require high integration and high performance. Therefore, the isolation technology of the device along with the gate line width reduction technology of the MOSFET is most closely related to the high integration of the semiconductor device, and many efforts have been made in each field to improve it.

In response to this, the device isolation technology mainly used a recessed-local oxide of silicon (R-LOCOS) technology to show some effect on the high integration of semiconductor devices. However, from below 0.25um, trench isolation technology is used to form device isolation (Shallow Trench Isolation, STI) in almost all devices.

1 shows a cross-sectional view of a device isolation film of a general semiconductor device. Referring to FIG. 1, an isolation layer may be formed by gap filling an insulating material in a trench formed in the semiconductor substrate 110. SiO 2 may be used as an insulating material for forming the device isolation layer.

As the voltage used in the semiconductor device increases, the depth of the device isolation layer must be deep to prevent leakage current. That is, since the size of the semiconductor element is reduced, the width of the element isolation film is small and the depth cannot be free from the leakage current unless the depth is increased.

An object of the present invention is to provide an isolation layer and a method of forming the same so as to be less affected by leakage current.

According to another aspect of the present invention, there is provided a method of forming an isolation layer of a semiconductor device, the method including forming a first nitride film on a semiconductor substrate, forming a hard mask on the first nitride film, and forming a hard mask. Sequentially etching the first nitride film and the semiconductor substrate using a mask as an etch mask to form a first nitride film pattern on the semiconductor substrate, and forming a trench in the semiconductor substrate, removing the hard mask, and Forming a second nitride film on an entire surface of the semiconductor substrate on which the first nitride film pattern and the trench are formed, gap-filling an oxide film in the trench on which the second nitride film is formed, and removing the first nitride film pattern and the second nitride film on the semiconductor substrate Forming a charge trap layer between the semiconductor substrate and the gapped oxide film; .

According to an aspect of the present disclosure, a semiconductor device including an isolation layer includes a semiconductor substrate, a trench formed in the semiconductor substrate, and an isolation layer formed in the trench, wherein the isolation layer is formed in the trench. And a charge trap layer formed along the surface of the oxide layer, and an oxide film gap-filled in the trench in contact with the charge trap layer.

In the method of forming a device isolation layer of a semiconductor device according to an embodiment of the present invention, a leakage current may be reduced by trapping charges leaked by a charge trap layer, and a dividet is formed on the device isolation layer without performing a separate photolithography process. There is an effect that can be easily formed.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

2A to 2G are flowcharts illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 2A, the first silicon nitride film 220 and the first silicon oxide film 230 are sequentially formed on the semiconductor substrate 210. For example, the first silicon nitride film 220 may be Si 3 N 4 , and the first silicon oxide film 230 may be SiO 2 .

Subsequently, a photoresist pattern 240 is formed on the first silicon oxide layer 230 by performing a photolithography process. The photoresist pattern 240 is patterned to form a trench for forming a shallow trench isolation of a semiconductor device.

Next, as shown in FIG. 2B, the first silicon oxide layer 230 is etched until the first silicon nitride layer 220 is exposed using the photoresist pattern 240 as an etching mask, and then photoresist. The pattern 230 is removed to form the hard mask 230 ′. In this case, reactive ion etching may be used to form the hard mask 230 ′.

Next, as shown in FIG. 2C, the first silicon nitride film 220 and the semiconductor substrate 210 are sequentially etched using the hard mask 230 ′ as an etch mask, and thus the upper surface of the semiconductor substrate 210 is etched. A first silicon nitride film pattern 220 'is formed on the trench, and a trench 235 is formed in the semiconductor substrate 210. At this time, the width of the trench 235 is formed may be 1000Å ~ 3000Å.

Next, as illustrated in FIG. 2D, the hard mask 230 ′ is removed through dry etching or wet etching. The second silicon nitride layer 245 is deposited on the semiconductor substrate 210 on which the first silicon nitride layer pattern 220 ′ and the trench 235 are formed. In this case, the deposited second silicon nitride layer 245 may be formed on the top and sidewall surfaces of the first silicon nitride layer pattern 220 ′ and the sidewalls and bottom surfaces of the trench 235. The second silicon nitride layer 245 may be Si 3 N 4 . In this case, the thickness of the deposited second silicon nitride film 245 may be 100 kPa to 500 kPa.

Next, as illustrated in FIG. 2E, a second silicon oxide layer 250 is deposited on the entire surface of the semiconductor substrate 210 so as to gapfill the trench 235 in which the second silicon nitride layer 245 is formed. In this case, the second silicon oxide layer 250 may be SiO 2 .

Next, as illustrated in FIG. 2F, the deposited second silicon oxide layer 250 is planarized by performing a chemical mechanical polishing (CMP) process. The CMP is performed until the second silicon nitride film 245 is exposed, wherein the second silicon nitride film 245 serves as a CMP stopping layer.

The CMP process is first performed only on the second silicon oxide film 250, and at the same time, when the second silicon nitride film 245 is exposed, the CMP process is simultaneously performed on the second silicon oxide film 250 and the second silicon nitride film 245. The process can be performed.

As described above, when the CMP process is performed on the second silicon oxide film 250 and the second silicon nitride film 245 at the same time, a difference in polishing amount may occur and dishing may occur. That is, as shown in FIG. 2F, a second silicon oxide film 250 ′ having a recessed shape may be formed in the second silicon oxide film 250 compared to the second silicon nitride film 250.

Next, as shown in FIG. 2G, after the CMP process is performed, the first silicon nitride layer pattern 220 ′ formed on the semiconductor substrate 210 and the second silicon nitride layer 245 formed on the second silicon nitride layer are dry. And using wet etching.

Specifically, the etching between the nitride film (eg, the second silicon nitride film 245 and the first silicon nitride film pattern 220 ') and the oxide film (eg, the second silicon oxide film 250') without using an etching mask. The second silicon nitride layer 245 and the first silicon nitride layer pattern 220 ′ may be removed by dry etching or wet etching the nitride layer and the oxide layer simultaneously by adjusting the selectivity.

For example, when the etching process is performed with the etching rate of the second silicon nitride layer 245 and the first silicon nitride layer pattern 220 ′ higher than that of the second silicon oxide layer 250 ′, the second silicon nitride layer 245 may be formed. The first silicon nitride layer pattern 220 ′ is quickly etched and removed, but the second silicon oxide layer 250 ′ is hardly etched.

The dry or wet etching process may be performed until both the second silicon nitride layer 245 and the first silicon nitride layer pattern 220 ′ are removed to expose the surface of the semiconductor substrate 210.

If the dry or wet etching process is further performed after the surface of the semiconductor substrate below the first silicon nitride layer pattern 220 'is exposed, the semiconductor substrate 210 may be spaced between the gap-filled second silicon oxide layer 250'. A portion of the upper portion of the second silicon nitride layer 245 ′ formed in the upper portion may be easily etched to form a divot 270.

That is, when the surface of the semiconductor substrate below the first silicon nitride layer pattern 220 ′ is exposed and a dry or wet etching process is further performed, a second silicon nitride layer formed on the upper portion 270 of the sidewall of the trench 235. A divot 270 may be formed by etching and removing 245 '. In this case, since the etch rate of the nitride film 245 'is much faster than that of the oxide film 250', the divot 270 may be easily formed.

As shown in FIG. 2G, the device isolation layer of the present invention includes a trench 235 formed in the semiconductor substrate 210 and an element isolation film formed in the trench 235. The device isolation layer may include a charge trap layer 245 ′ formed along a surface of the trench 235; And an oxide film 250 'gap-filled in the trench 235 in contact with the charge trap layer 245'.

The width W2 of the trench 235 may be 1000 mW to 3000 mW, and the charge trap layer may be formed to have a thickness d1 of 100 mW to 500 mW. The charge trap layer 245 ′ is formed between the gap-filled oxide layer 250 ′ and the semiconductor substrate 210. The device isolation layer includes a divot 270 formed by partial loss of the charge trap layer 245 ′ formed on the sidewall of the trench 235.

The charge trap layer 245 ′ may be Si 3 O 4 , and the gap-filled oxide layer 250 ′ may be SiO 2 . The width W1 of the gap-filled oxide layer 250 ′ may be determined according to the thickness d1 of the charge trap layer 245 ′. Since the dielectric constant of the charge trap layer 245 'formed of the nitride film is larger than that of the gap-filled oxide film 250' and the dielectric constant of the semiconductor substrate (for example, the silicon substrate), the charge trap layer 245 'has a leakage current ( It traps leakage current.

Therefore, the device isolation film of the present invention can reduce the leakage current by trapping the charge leaked by the charge trap layer, and as shown in FIG. 2G, a divot is formed on the device isolation film without a separate portography process. It can be formed easily.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 shows a cross-sectional view of a device isolation film of a general semiconductor device.

2A to 2G are flowcharts illustrating a method of forming an isolation layer in a semiconductor device according to an embodiment of the present invention.

Claims (11)

Forming a first nitride film on the semiconductor substrate; Forming a hard mask on the first nitride film; Sequentially etching the first nitride film and the semiconductor substrate using the hard mask as an etching mask to form a first nitride film pattern on the semiconductor substrate, and forming a trench in the semiconductor substrate; Removing the hard mask and forming a second nitride film on an entire surface of the semiconductor substrate on which the first nitride film pattern and the trench are formed; Gap-filling an oxide film in the trench in which the second nitride film is formed; And Forming a charge trap layer between the semiconductor substrate and the gapped oxide film by removing the first nitride film pattern and the second nitride film on the semiconductor substrate. The method of claim 1, Wherein the first nitride film and the second nitride film are Si 3 N 4 and the oxide film is SiO 2 . The method of claim 1, wherein forming a trench in the semiconductor substrate comprises: Forming a trench having a width of 1000 mV to 3000 mV in the semiconductor substrate. The method of claim 1, wherein the forming of the second nitride film includes: And forming the second nitride film on the upper and sidewall surfaces of the first nitride film pattern and on the sidewalls and the bottom surface of the trench. The method of claim 4, wherein forming the second nitride film includes: And forming the second nitride film on the upper and sidewall surfaces of the first nitride film pattern and the sidewalls and the bottom surface of the trench so as to have a thickness of about 100 to about 500 microseconds. The method of claim 1, wherein the step of gap-filling an oxide film in the trench in which the second nitride film is formed includes: Depositing the oxide film on the entire surface of the semiconductor substrate so as to gap fill the trench in which the second nitride film is formed; And And planarizing the deposited oxide film (250) by performing a chemical mechanical polishing (CMP) process. The method of claim 1, wherein the forming of the charge trap layer comprises: The charge isolation layer is formed by removing the first nitride layer pattern and the second nitride layer on the semiconductor substrate by increasing the etching rate of the second nitride layer and the first nitride layer pattern as compared to the oxide layer. Forming method. The method of claim 7, wherein forming the charge trap layer, And forming a divot by etching the second nitride film formed on the upper portion of the sidewall of the trench. Semiconductor substrates; A trench formed in the semiconductor substrate; And A device isolation layer formed in the trench; The device isolation layer, A charge trap layer formed along the surface of the trench; And And an oxide layer gapping into the trench in contact with the charge trap layer. The method of claim 9, wherein the charge trap layer, A semiconductor device having a thickness of 100 mW to 500 mW. The method of claim 9, wherein the device isolation layer, And a divot formed by partial loss of the charge trap layer formed on the sidewalls of the trench.
KR1020080074671A 2008-07-30 2008-07-30 Shallow trench isolation in semiconductor and the method of forming the same KR20100013137A (en)

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