KR20100011555A - Method for fabricating fuse in semiconductor device - Google Patents

Method for fabricating fuse in semiconductor device Download PDF

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Publication number
KR20100011555A
KR20100011555A KR1020080072820A KR20080072820A KR20100011555A KR 20100011555 A KR20100011555 A KR 20100011555A KR 1020080072820 A KR1020080072820 A KR 1020080072820A KR 20080072820 A KR20080072820 A KR 20080072820A KR 20100011555 A KR20100011555 A KR 20100011555A
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KR
South Korea
Prior art keywords
fuse
pattern
forming
semiconductor device
layer
Prior art date
Application number
KR1020080072820A
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Korean (ko)
Inventor
고민구
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080072820A priority Critical patent/KR20100011555A/en
Publication of KR20100011555A publication Critical patent/KR20100011555A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE: A method for forming a fuse of a semiconductor device is provided to prevent a generation of a bridge by preventing the formation of the sharp-shaped sidewall of a fuse pattern. CONSTITUTION: A dummy fuse pattern(225) is formed in the fuse regions of a semiconductor substrate(200). A SOG(Spin On Glass) layer(230) and an inter-metal insulating layer(235) are formed on the semiconductor substrate. A plurality of fuse patterns(260a) is formed in the fuse regions of the semiconductor substrate. The metal wiring pattern(260b) is formed in the cell region of the semiconductor substrate. A first passivation layer(270) and a second passivation layer(275) are successively formed on the top of an overall structure including the fuse pattern and the metal wiring pattern. A photosensitive pattern(280) is formed on the top of the second passivation layer.

Description

Method for forming fuse of semiconductor device {METHOD FOR FABRICATING FUSE IN SEMICONDUCTOR DEVICE}

The present invention relates to a method of forming a fuse of a semiconductor device, and to a method of forming a thin fuse pattern without etching the upper portion of the fuse.

In general, in the manufacture of a semiconductor device, especially a memory device, if any one of a number of fine cells is defective, the semiconductor device does not function as a memory and thus is treated as a defective product.

However, even though only a few cells in the memory have failed, discarding the entire device as a defective product is an inefficient treatment method in terms of yield.

Therefore, the current yield is improved by replacing a defective cell in which a defect has occurred by using a redundancy cell previously installed in the memory device.

A repair method using a spare cell typically includes a spare word line for replacing a normal word line and a spare bit line for replacing a normal bit line for each cell array, and includes a normal word including a cell when a defect occurs in a specific cell. The line or normal bit line is replaced with a spare word line or a spare bit line.

To this end, the memory device includes a circuit for changing an address corresponding to a defective cell to an address of a spare cell when a defective cell is found through testing after completion of wafer processing.

Therefore, when an address signal corresponding to a defective cell is input in actual use, the data of the spare cell replaced corresponding to the defective cell is accessed.

The most widely used repair method described above is to replace a path of an address by blowing and blowing a fuse with a laser beam.

Therefore, a conventional memory device includes a fuse unit capable of replacing an address path by irradiating a laser with a fuse to blow the laser. Here, the wiring broken by laser irradiation is called a fuse, and the fuse and the area | region surrounding it are called a fuse box.

Conventionally, a blowing process is performed in a state in which an oxide film is partially left on the fuse, but the thickness of the remaining oxide film is not uniformly formed. It is happening. In particular, since the introduction of metal fuses, such a problem becomes more serious, and the yield reduction of the device is increasing beyond the allowable range.

1A to 1C illustrate a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, a metal layer (not shown) and a barrier metal layer (not shown) are formed on a semiconductor substrate 100 having a lower structure.

Next, a first photosensitive film pattern (not shown) defining a fuse pattern is formed on the barrier metal layer (not shown), and the barrier metal layer (not shown) and the metal layer (using the first photosensitive film pattern (not shown) are masked. The metal layer pattern 110a and the barrier metal layer pattern 110b are formed by etching.

The first photoresist layer pattern (not shown) is removed to form the fuse pattern 110. In this case, an Al 2 O 3 film (not shown) is formed on the sidewall of the fuse pattern 110 during the photosensitive film strip process for removing the first photoresist pattern (not shown).

Next, the insulating film 120 and the passivation layer 130 are sequentially formed on the entire semiconductor substrate 100 including the fuse pattern 110.

The insulating film 120 is formed of a stacked structure of an intermetal dielectric and an SOG film. At this time, it is preferable that the intermetallic insulating film is formed to a thickness of 800 to 1200 kPa, and the SOG film is formed to a thickness of 5000 to 7000 kPa.

Then, a curing process is performed on the SOG film. Here, the curing process serves to planarize the SOG film.

The passivation layer 130 may be formed as a stacked structure of a first passivation layer having a thickness of 10000 to 12000 μs and a second passivation layer having a thickness of 2000 to 4000 μs.

Referring to FIG. 1B, a photoresist layer pattern 140 defining a fuse open region is formed on the passivation layer 130 by using a repair mask.

Next, the passivation layer 130 and the insulating layer 120 are etched using the photoresist pattern 140 as an etch mask to form a fuse open region 150 that exposes the fuse pattern 110. At this time, a portion of the semiconductor substrate 100 under both sides of the fuse pattern 110 is also etched due to the etching process for forming the fuse open region 150.

Referring to FIG. 1C, the upper portion of the fuse pattern 110 is etched to thin the thickness of the fuse pattern 110. This is because if the thickness of the fuse pattern 110 is too thick, the blowing may not be performed properly and thus may not be suitable for use as a fuse to etch the upper portion of the fuse pattern 110 to thin the thickness thereof.

In this case, the sidewall of the fuse pattern 110 is hardly etched by the Al 2 0 3 film formed on the sidewall of the fuse pattern 110 during the process of etching the upper portion of the fuse pattern 110. 110 is formed.

FIG. 2 is an SEM image of a fuse pattern etched at an upper portion, as shown in FIG.

Such a sharp state of the residue may act as a bridge (Cridge) by falling down the pointed residue in the subsequent fuse blowing process, in which case there is a problem that the fuse cutting is not made normally, thereby reducing the reliability of the device.

The present invention is to improve the process of forming a fuse pattern to be able to form a thin thickness of the fuse without further proceeding the process of etching the fuse pattern.

The fuse forming method of the semiconductor device according to the present invention

Forming an insulating film having a step on the substrate, forming a flattened fuse material layer on the insulating film, and patterning the fuse material layer to form a fuse pattern.

The forming of the insulating layer having the step may include forming a dummy fuse pattern on the substrate and forming the insulating layer on the dummy fuse pattern and the substrate.

Here, the insulating film includes a spin on glass (SOG) film, and the SOG film is formed to a thickness of 5000 ~ 7000 Å.

In addition, the fuse material layer includes aluminum, and the fuse material layer further includes a barrier metal layer. At this time, the barrier metal layer is preferably any one selected from the group consisting of titanium and titanium nitride film.

The insulating film is formed to have a step of 4000 to 6000 mW, and the fuse pattern is formed to have a thickness of 2000 to 3000 mW. In this case, the fuse pattern is preferably formed in a region having a high height of the insulating layer due to the step.

After forming the fuse pattern, forming a passivation layer on the fuse pattern and the insulating layer, and forming a fuse open region through which the fuse pattern is exposed by etching the passivation layer and the insulating layer. It is done.

The present invention can prevent the fuse pattern sidewalls from being formed in a sharp shape by not further performing the process of etching the upper portion of the fuse pattern in order to reduce the thickness of the fuse pattern. Therefore, in the fuse blowing process, such a sharp fuse pattern is cut off to prevent the bridge from being induced, thereby improving the reliability of the device.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

3A to 3E are cross-sectional views illustrating a fuse forming method of a semiconductor device according to the present invention.

Referring to FIG. 3A, a dummy fuse pattern 225 is formed in a fuse region on an upper portion of a semiconductor substrate 200 having a lower structure. In this case, the dummy fuse pattern 225 may be formed by forming and patterning the first metal layer 210 and the first barrier metal layer 220 on the semiconductor substrate 200.

Here, the first metal layer 210 may be formed of aluminum, and the first barrier metal layer 220 may be formed of a laminated structure of a titanium nitride film and a titanium film.

An oxide film (not shown) is formed on the dummy fuse pattern 225 and the semiconductor substrate 200.

Next, a SOG (Spin On Glass) film 230 is formed on the oxide film (not shown).

At this time, the SOG film 230 is preferably formed to a thickness of 5000 ~ 7000Å. Since the SOG film 230 has excellent step coverage characteristics, the SOG film 230 is formed along the dummy fuse pattern 225 formed in the lower layer. do.

Next, an intermetal dielectric 235 is formed on the SOG film 230.

At this time, the intermetallic insulating film 235 is formed along a topology in which the SOG film 230 is formed, and is preferably formed to have a thickness of 3000 to 5000 kPa.

Referring to FIG. 3B, a second metal layer 250 is formed on the intermetallic insulating layer 235. Here, the second metal layer 250 is preferably formed of aluminum, it is preferable to form a thickness of 9000 ~ 11000Å.

Next, the CMP process is performed to planarize the second metal layer 250.

At this time, due to the step by the dummy fuse pattern 225, the second metal layer 250 having a thickness of 2000 to 3000 kV is formed in the region having a high height, and the second metal layer 250 having a thickness of 6000 to 8000 kPa is formed at the region having a low height. Is formed.

That is, the thickness of the second metal layer 250 formed in the fuse region by the dummy fuse pattern 225 is formed to be thinner than the thickness of the second metal layer 250 formed in the cell region, and the thickness difference is about 4000 to 6000 kPa. .

Next, a second barrier metal layer 255 is formed on the planarized second metal layer 250. In this case, the second barrier metal layer 255 is formed of any one selected from the group consisting of titanium (Ti) and titanium nitride film (TiN).

Referring to FIG. 3C, the second barrier metal layer 255 and the second metal layer 250 are patterned to form a plurality of fuse patterns 260a in the fuse region. At this time, the metal wiring pattern 260b is formed in the cell region.

Although one fuse pattern 260a is formed on one dummy fuse pattern 225, a plurality of fuse patterns 260a may be formed on one dummy fuse pattern 225. . For example, by forming the dummy fuse pattern 225 wide, a plurality of fuse patterns 260a may be formed thereon.

At this time, the thickness of the second metal layer 250 is formed differently depending on the presence or absence of the dummy fuse pattern 225 due to the step by the dummy fuse pattern 225 as shown in Figure 3b, the thickness of the fuse pattern 260a It is formed thinner than the wiring pattern 260b.

Referring to FIG. 3D, the first passivation layer 270 and the second passivation layer 275 are sequentially formed on the resultant product of FIG. 3C including the fuse pattern 260a and the metal wiring pattern 260b.

At this time, the first passivation layer 270 is formed to a thickness of 10000 ~ 12000Å, the second passivation layer 275 is formed to a thickness of 2000 ~ 4000Å.

Next, a photoresist pattern 280 is formed on the second passivation layer 275 by using a repair mask that defines a fuse open region.

Referring to FIG. 3E, the second passivation layer 275 and the first passivation layer 270 are etched using the photoresist pattern 280 as an etch mask to form a fuse open region 285 exposing the fuse pattern 260a. . At this time, as the over-etching proceeds, the intermetallic insulating layer 235 on both sides of the lower portion of the fuse pattern 260a is also etched.

In the related art, since the fuse pattern (110 in FIG. 1A) is formed to be thick, a repair metal etching process for additionally etching the upper portion of the fuse pattern after forming the fuse open region is required.

However, when the fuse pattern 260a is formed as in the present invention, the thickness of the fuse pattern 260a may be thinly formed without further etching the fuse pattern 260a. Accordingly, when the fuse pattern 260a is etched, the phenomenon in which the fuse pattern 260a is not etched on the sidewall of the fuse pattern 260a and thus remains sharp may be prevented.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1A to 1C are cross-sectional views illustrating a fuse forming method of a semiconductor device according to the prior art.

Figure 2 is a photograph showing a problem occurred in the fuse forming method of the semiconductor device according to the prior art.

3A to 3E are cross-sectional views illustrating a fuse forming method of a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

200: substrate 225: dummy fuse pattern

230: SOG film 235: intermetallic insulating film

260a: fuse pattern 270: first passivation layer

280: second passivation layer 280: photosensitive film pattern

285: fuse open area

Claims (11)

Forming an insulating film having a step on the substrate; Forming a planarized fuse material layer on the insulating film; And Patterning the fuse material layer to form a fuse pattern A fuse forming method of a semiconductor device comprising a. The method of claim 1, Forming the insulating film having the step is Forming a dummy fuse pattern on the substrate; And Forming the insulating layer on the dummy fuse pattern and the substrate. A fuse forming method of a semiconductor device comprising a. The method of claim 1, The insulating film is a fuse on the semiconductor device, characterized in that it comprises a SOG (Spin On Glass) film. The method of claim 3, wherein The SOG film is a fuse forming method of the semiconductor device, characterized in that formed in a thickness of 5000 ~ 7000Å. The method of claim 1, And the fuse material layer comprises aluminum. The method of claim 5, wherein And the fuse material layer further comprises a barrier metal layer. The method of claim 6, The barrier metal layer is a fuse forming method of a semiconductor device, characterized in that any one selected from the group consisting of titanium and titanium nitride film. The method of claim 1, The insulating film is a fuse forming method of a semiconductor device, characterized in that formed to have a step of 4000 ~ 6000 ~. The method of claim 1, The fuse pattern is a fuse forming method of the semiconductor device, characterized in that formed in a thickness of 2000 ~ 3000Å. The method of claim 1, And the fuse pattern is formed in a region having a high height of the insulating layer due to the step difference. The method of claim 1, Forming a passivation layer on the fuse pattern and the insulating layer after forming the fuse pattern; And Etching the passivation layer and the insulating layer to form a fuse open region through which the fuse pattern is exposed; A fuse forming method of a semiconductor device further comprising.
KR1020080072820A 2008-07-25 2008-07-25 Method for fabricating fuse in semiconductor device KR20100011555A (en)

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KR1020080072820A KR20100011555A (en) 2008-07-25 2008-07-25 Method for fabricating fuse in semiconductor device

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Application Number Priority Date Filing Date Title
KR1020080072820A KR20100011555A (en) 2008-07-25 2008-07-25 Method for fabricating fuse in semiconductor device

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KR20100011555A true KR20100011555A (en) 2010-02-03

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