KR20090076132A - Method for manufacturing semiconductor device - Google Patents

Abstract

A manufacturing method of the semiconductor device is provided, which improves the repair efficiency by reducing the thickness of fuse more than the metal wiring of the cell region by using the planarization process. The respective metal wirings(18a,18b) and fuse(24b) are formed at the upper part of the semiconductor substrate(10) segmented by the cell region and fuse regions. The first interlayer insulating film(14) is formed at the upper part of the metal wiring and fuse. The first interlayer insulating film of the fuse regions is etched and fuse is exposed. The first interlayer insulating film is planarized until the metal wiring is exposed. The fuse is determined in the predetermined thickness. The metal wiring and fuse are formed in the thickness of 4000~8000Å. The planarization process is performed until fuse remains in the thickness of 500~2000Å.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, when a metal wiring is used as a fuse, the repair efficiency can be improved by reducing the thickness of the fuse than the metal wiring in the cell region by using a planarization process.

In general, in the manufacture of a semiconductor device, especially a memory device, if any one of a number of fine cells is defective, the semiconductor device does not function as a memory and thus is treated as a defective product.

However, even though only a few cells in the memory have failed, discarding the entire device as a defective product is an inefficient treatment method in terms of yield.

Therefore, the current yield is improved by replacing a defective cell in which a defect has occurred by using a redundancy cell previously installed in the memory device.

A repair method using a spare cell typically includes a defective cell in which defects are generated by preliminarily providing a spare word line provided to replace the normal word line and a spare bit line provided to replace the normal bit line for each cell array. The normal word line or the normal bit line is replaced with a spare word line or a spare bit line.

In detail, when a defect cell is selected through a test after wafer processing is completed, a program is executed in an internal circuit to replace an address corresponding to the defective cell with an address of a spare cell. Therefore, when the address signal corresponding to the defective cell is input in actual use, the data of the spare cell replaced in correspondence with the defective cell is accessed.

The most widely used method as described above is to blow a fuse with a laser beam to blow, thereby replacing a path of an address. Therefore, a conventional memory device includes a fuse unit capable of replacing an address path by irradiating a laser with a fuse to blow the laser. Here, the wiring broken by the laser irradiation is called a fuse, and the broken part and the surrounding area are called a fuse box.

The fuse part includes a plurality of fuse sets, and one fuse set may replace one address path. The number of fuse sets provided in the fuse unit is determined corresponding to the number of spare word lines or spare bit lines included in the memory device.

Although not shown in the drawings, a method of manufacturing a conventional semiconductor device is as follows.

First, a planarized interlayer insulating film is formed on a fuse region of a semiconductor substrate, and a plurality of metal fuses are formed on the interlayer insulating film. Next, an insulating film and a protective film are formed on the semiconductor substrate to cover the metal fuse.

Next, a partial thickness of the insulating film and the protective film is etched to form a fuse open area such that an insulating film having a predetermined thickness is left over the metal fuse of the blowing region. Then, a blowing process of cutting a specific metal fuse by irradiating a laser to the fuse open area is performed.

Such metal fuses are simultaneously formed during the metallization process of the cell region. In particular, when formed simultaneously with the second metal wiring, the metal fuse is formed of a copper (Cu) material, and the thickness thereof is formed to be about 4000 to 8000 kPa thick.

Therefore, a repair failure occurs during the blowing process in which the metal fuse is not properly cut. For this reason, there is a problem that the repair efficiency is reduced and the yield and reliability of the device are lowered.

The present invention has the purpose of improving the repair efficiency by reducing the thickness of the fuse than the metal wiring in the cell area using a planarization process when using the metal wiring as a fuse.

A method of manufacturing a semiconductor device according to the present invention includes forming metal wires and a fuse on an upper portion of a semiconductor substrate divided into a cell region and a fuse region; Forming a first interlayer insulating film on the metal wiring and the fuse; Etching the first interlayer dielectric layer in the fuse region to expose the fuse; And planarizing the first interlayer insulating film until the metal wiring is exposed, and simultaneously removing the fuse by a predetermined thickness.

Here, the metal wiring and the fuse is formed to a thickness of 4000 ~ 8000 Å, the planarization process is performed until the fuse is left by the thickness of 500 ~ 2000 Å, the planarization process is a chemical mechanical polishing (CMP) method It is characterized by performing.

And forming a second interlayer insulating film over the entire surface after the fuse removing step; And selectively etching the second interlayer dielectric layer of the fuse region to form a fuse open region.

The present invention provides the effect of improving the repair efficiency by reducing the thickness of the fuse than the metal wiring in the cell area using a planarization process when using the metal wiring as a fuse.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, a predetermined lower structure (not shown) including a gate is formed in the cell region A of the semiconductor substrate 10 partitioned into the cell region A and the fuse region B. Referring to FIG.

Next, bit lines 12 are formed in the cell region A and the fuse region B of the semiconductor substrate 10, respectively.

Next, a first interlayer insulating film 14 is formed on the semiconductor substrate 10 including the bit lines 12.

Thereafter, the first interlayer insulating film 14 of the fuse region B is selectively etched to form a first contact hole (not shown) exposing the bit line 12.

Next, a first contact plug 16 is formed by filling a conductive film in the first contact hole.

Next, the first metal wiring 18a is formed on the first interlayer insulating film 14 of the cell region A, and at the same time, the first contact plugs are formed on the first interlayer insulating film 14 of the fuse region B. The first metal wiring 18b to be connected to 16 is formed.

Next, a second interlayer insulating film 20 is formed on the first metal wirings 18a and 18b.

Thereafter, the second interlayer insulating film 20 in the fuse region B is selectively etched to form a second contact hole (not shown) exposing the first metal wiring 18b.

Next, a second contact plug 22 is formed by filling a conductive film in the second contact hole.

Next, the second metal wiring 24a is formed on the second interlayer insulating film 20 of the cell region A, and at the same time, the second contact plugs are formed on the second interlayer insulating film 20 of the fuse region B. A fuse 24b connected to 22 is formed.

At this time, the second metal wiring 24a and the fuse 24b are formed of a metal such as copper (Cu), and preferably formed at a thickness of 4000 to 8000 kPa.

The second metal wiring 24a and the fuse 24b are preferably formed by a damascene process.

Referring to FIG. 1B, a third interlayer insulating film 26 is formed on the entire surface.

Next, the third interlayer insulating film 26 of the fuse region B is etched to expose the fuse 24b.

In this case, the etching process of the third interlayer dielectric layer 26 may be performed such that the third interlayer dielectric layer 26 remains on the fuse 24b.

Referring to FIG. 1C, the third interlayer insulating film 26 is planarized until the second metal wiring 24a is exposed, and at the same time, the fuse 24b is removed by a predetermined thickness.

Here, the planarization process for the third interlayer insulating film 26 is preferably performed by the chemical mechanical polishing (CMP) method until the fuse 24b is left to the thickness of 500 ~ 2000Å.

Referring to FIG. 1D, a fourth interlayer insulating film 28 is formed over the entire surface.

Next, the fourth interlayer insulating layer 28 of the fuse region B is selectively etched to form the fuse open region 30.

In this case, the etching process of the fourth interlayer insulating film 28 is preferably performed such that the fourth interlayer insulating film 28 remains a predetermined thickness on the upper portion of the fuse 24b.

 Subsequently, a blowing process is performed in which the fuse open area 30 is irradiated with a laser to cut the fuse 24b.

In the embodiment of the present invention, a case in which the second metal wiring is used as a fuse has been described as an example. However, the present invention is not limited thereto, and the first metal wiring or the third metal wiring may be used as the fuse.

That is, the present invention can reduce the thickness of the fuse to facilitate the cutting of the fuse during the blowing process (blocking) can improve the repair efficiency.

1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Claims (5)

Forming metal wirings and fuses on the semiconductor substrate divided into a cell region and a fuse region, respectively; Forming a first interlayer insulating film on the metal wiring and the fuse; Etching the first interlayer dielectric layer in the fuse region to expose the fuse; And Planarizing the first interlayer insulating film until the metal wiring is exposed, and simultaneously removing the fuse by a predetermined thickness. Method of manufacturing a semiconductor device comprising a. The method of claim 1, wherein the metal wiring and the fuse are formed to a thickness of 4000 to 8000 Å. The method of claim 1, wherein the planarization process is performed until the fuse has a thickness of 500 to 2000 kV. The method of claim 1, wherein the planarization process is performed by chemical mechanical polishing (CMP). The method of claim 1, wherein after the fuse removing step Forming a second interlayer insulating film over the entire surface; And Selectively etching the second interlayer dielectric layer of the fuse region to form a fuse open region Method of manufacturing a semiconductor device further comprising.

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