KR101102048B1 - The fuse of semicondutor device and method for fabricating the same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse of a semiconductor device and a method of manufacturing the same, wherein the copper component is moved after the fuse blowing process by forming a fuse pattern in which the blowing portion is bent in a 's' shape and forming an interlayer insulating layer adjacent to the inside of the bent portion. Disclosed is a technique for preventing a phenomenon and improving characteristics and reliability of a semiconductor device.

Description

Fuse of semiconductor device and manufacturing method thereof {THE FUSE OF SEMICONDUTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a fuse of a semiconductor device and a method of manufacturing the same. In particular, it relates to a copper fuse.

In general, in the manufacture of a semiconductor device, especially a memory device, if any one of a number of fine cells is defective, the semiconductor device does not function as a memory and thus is treated as a defective product.

However, even though only a few cells in the memory have failed, discarding the entire device as a defective product is an inefficient treatment method in terms of yield.

Therefore, the current yield is improved by replacing a defective cell in which a defect has occurred by using a redundancy cell previously installed in the memory device.

A repair method using a spare cell typically includes a spare word line for replacing a normal word line and a spare bit line for replacing a normal bit line for each cell array, and includes a normal word including a cell when a defect occurs in a specific cell. The line or normal bit line is replaced with a spare word line or a spare bit line.

To this end, the memory device includes a circuit for changing an address corresponding to a defective cell to an address of a spare cell when a defective cell is found through testing after completion of wafer processing.

Therefore, when an address signal corresponding to a defective cell is input in actual use, the data of the spare cell replaced corresponding to the defective cell is accessed.

The most widely used repair method described above is to replace a path of an address by blowing and blowing a fuse with a laser beam.

Therefore, a conventional memory device includes a fuse unit capable of replacing an address path by irradiating a laser with a fuse to blow the laser. Here, the wiring broken by laser irradiation is called a fuse.

As the material of the metal wiring, aluminum (Al) and tungsten (W) having excellent electrical conductivity have been mainly used, and recently, research into using copper (Cu) as a next generation metal wiring material has been conducted. Since copper has better electrical conductivity and lower resistance than aluminum and tungsten, when copper is used as a metal wiring material, there is an advantage that the RC signal delay problem can be solved in a highly integrated high speed operation device.

Hereinafter, a fuse of a semiconductor device and a method of manufacturing the same according to the related art will be described with reference to the accompanying drawings.

Referring to FIG. 1A, a first interlayer insulating layer 100, an etch stop layer 105, and a second interlayer insulating layer 110 are formed on a semiconductor substrate (not shown).

Next, a first photosensitive layer pattern 115 is formed on the second interlayer insulating layer 110 to open the fuse region.

Next, the second interlayer insulating layer 110 and the etch stop layer 105 are etched using the first photoresist pattern 115 as a mask to form a fuse region in which the first interlayer insulating layer 100 is exposed.

Referring to FIG. 1B, after removing the first photoresist layer pattern 115, a metal material is deposited on the first interlayer insulating layer 100 and the second interlayer insulating layer 110 including the fuse region. At this time, the metal material is preferably copper.

Next, the CMP process is performed until the second interlayer insulating layer 110 is exposed to form the fuse pattern 120.

1C and 1D, a capping layer and a third interlayer insulating layer 130 are formed on the second interlayer insulating layer 110 and the fuse pattern 120. Here, the capping film (not shown) is preferably formed of a nitride film and the third interlayer insulating film 130 is formed of an oxide film.

Next, a second photoresist layer pattern 135 for repair etching is formed on the third interlayer insulating layer 130. Next, the third interlayer insulating layer 130 is etched using the second photoresist pattern 135 as a mask to form a fuse open region.

Next, a blowing process using a laser is performed to cut the fuse pattern 120. In this case, a problem occurs in that a copper component is diffused in the cut portion of the fuse pattern 120.

As such, as the copper component diffuses in the cut fuse pattern, a fail in the fuse area is caused. Specifically, in the fuse area, a repair process is performed in which a specific fuse is selectively cut and then a potential difference is applied in a high temperature and high humidity atmosphere to determine whether there is a defect, and then a cell that is found to be defective is connected to a spare cell embedded in the chip to be regenerated. do. However, when the copper component of the fuse region is moved toward the cut fuse, the fuse is shorted to cause a failure in which the repair process cannot be performed properly, thereby degrading the characteristics and reliability of the semiconductor device.

The present invention is intended to improve the characteristics and reliability of the device by changing the structure of the fuse.

The fuse of the semiconductor device according to the invention

The fuse pattern includes a fuse pattern bent in a 'z' shape on the same plane and an interlayer insulating layer formed therein adjacent to the bent portion of the fuse pattern.

Here, the fuse pattern may be formed of copper, the bent portion of the fuse pattern may be a blowing part, and the fuse pattern may be formed in a single layer or a multilayer structure.

The multilayer structure includes a plurality of first fuse patterns having a line shape at a lower portion thereof, a second fuse pattern connected to the first fuse pattern and having a bent portion of the blower, and having a first fuse pattern and a second fuse pattern. Are connected by contacts to form a single line. The contact may connect an end of one first fuse pattern and the second fuse pattern.

Method of manufacturing a fuse of a semiconductor device according to a first embodiment of the present invention

Forming an interlayer insulating layer on the semiconductor substrate, forming a fuse predetermined region which is bent in an '?' Form by etching the interlayer insulating layer, and filling the fuse predetermined region with a metal material to form a fuse pattern; And etching the interlayer insulating layer outside the fuse pattern to protrude the interlayer insulating layer adjacent to the fuse pattern and the bent portion of the fuse pattern.

Here, it is preferable that the metal material is copper, the fuse pattern is a shape in which the blowing part is bent, and the interlayer insulating film is formed of an oxide film.

The etching of the interlayer insulating layer may include forming a photoresist pattern covering the fuse pattern and the interlayer insulating layer formed on an inner side of the fuse pattern and the bent portion of the fuse pattern, and etching the interlayer insulating layer using the photoresist pattern as a mask. Including the step, the photosensitive film pattern is characterized in that the triangular form.

In addition, the fuse manufacturing method of the semiconductor device according to the second embodiment of the present invention

Forming a first interlayer insulating layer and a second interlayer insulating layer on the semiconductor substrate, forming a first fuse pattern in the form of a line by embedding the second interlayer insulating layer with a metal material after etching, and forming the first fuse pattern And forming a third interlayer insulating layer on the second interlayer insulating layer, forming a contact to be connected to the first fuse pattern by etching the third interlayer insulating layer, and filling the third interlayer insulating layer with a metal material. Forming a fourth interlayer insulating layer on the interlayer insulating layer, forming a second fuse pattern connected to the contact by etching the fourth interlayer insulating layer and burying the fourth interlayer insulating layer with a metal material to form a second fuse pattern; Etching a portion of the fourth interlayer insulating layer to cause the fourth interlayer insulating layer adjacent to the inner side of the second fuse pattern and the bent portion of the second fuse pattern to protrude; And that is characterized.

Here, the metal material is copper, and the first, second, third and fourth interlayer insulating films are preferably formed of an oxide film.

The first fuse pattern may be formed in plural, and the second fuse pattern may have a blowing portion that is bent in a '?' Shape, and the contact may include one end of the first fuse pattern and the second fuse pattern. The first fuse pattern and the second fuse pattern are connected to each other to form a single line by the contact.

The etching of the fourth interlayer insulating layer may include forming a photoresist pattern covering the second fuse pattern and the fourth interlayer insulating layer formed at an inner side adjacent to the bent portion of the second fuse pattern and forming the photoresist pattern. And etching the interlayer insulating film with a mask, wherein the photoresist pattern is triangular.

The fuse of the semiconductor device and the method of manufacturing the same according to the present invention may improve the characteristics and reliability of the semiconductor device by forming a fuse pattern in which the blowing portion is bent to prevent the copper component of the fuse from moving after the blowing process.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2 is a perspective view illustrating a fuse of a semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention.

Referring to FIG. 2, a semiconductor device having a fuse pattern in which a blowing portion is bent in a '-' shape is illustrated. Here, the fuse pattern 220 has a shape in which the center part is bent, and is symmetrically formed with respect to the blowing part. The interlayer insulating layer 210 is formed adjacent to the bent portion of the fuse pattern 220.

A method of manufacturing a fuse structure of this type is as follows.

First, a first interlayer insulating layer 200 is formed on a semiconductor substrate (not shown). Next, a first photoresist pattern (not shown) is formed on the first interlayer insulating layer 200 to open the second predetermined interlayer insulating layer 210, and the fuse intended region, which is bent in a 's' shape, on the second interlayer insulating layer 210. Form a).

Next, the second interlayer insulating layer 210 is etched using the first photoresist pattern (not shown) as a mask to form a fuse predetermined region. Next, a metal material is formed on the second interlayer insulating layer 210 including the fuse predetermined region. Here, the metal material is preferably copper (Cu).

Then, the planarization process is performed until the second interlayer insulating layer 210 is exposed to form the fuse pattern 220 that is bent in a 'ㅅ' shape. Here, the fuse pattern 220 is in a form in which the center portion is bent, and preferably formed symmetrically with respect to the blowing portion.

Next, a second photoresist pattern (not shown) is formed on the fuse pattern 220 and the second interlayer insulating layer 210 adjacent to the inside of the fuse pattern 220. The second interlayer insulating layer 210 is etched using the second photoresist pattern (not shown) as a mask. As a result, the fuse pattern 220 and the second interlayer insulating layer 210 adjacent to the inside of the fuse pattern 220 protrude upward from the etched second interlayer insulating layer 210.

Next, a third interlayer insulating layer (not shown) is formed on the fuse pattern 220 and the second interlayer insulating layer 210, and a repair etching process is performed to form a fuse open region.

Next, a repair process is performed on the fuse pattern 220 in the fuse open area to cut the fuse.

When the blowing process is performed on the fuse pattern 220 that is bent in the 's' shape as described above, the movement path of the copper component is blocked in the second interlayer insulating layer 210 formed inside the bent portion of the fuse pattern 220. do. Therefore, movement of the copper component which occurs during the fuse blowing process is prevented.

As described above, the fuse pattern may be formed in a multilayer structure in addition to the method of forming a fuse pattern having a 's' shape in a single layer. As described above, the fuse structure formed of the multilayer is as follows. This is explained with reference to FIG. 3H.

A plurality of line-shaped first fuse patterns 320 are provided on the semiconductor substrate (not shown), and contacts 340 respectively connected to the first fuse patterns 320 are provided. In addition, a second fuse pattern 345 connected to the contacts 340 is provided. At this time, the second fuse pattern 345 has a shape in which the blowing portion is bent in a 's' shape. In this case, since the first fuse pattern 320 and the second fuse pattern 345 are connected through the contact 340, the first fuse pattern 320 and the second fuse pattern 345 have a single line shape. An interlayer insulating film 337 is provided inside the bent portion of the second fuse pattern 345.

As a result, the interlayer insulating layer 337 may serve as a barrier after a subsequent blowing process to prevent the copper component in the fuse from moving to the cut fuse.

3A to 3H are perspective views illustrating a fuse manufacturing method of a semiconductor device according to a second exemplary embodiment of the present invention.

Referring to FIG. 3A, a first interlayer insulating layer 300, a first etch stop layer 305, and a second interlayer insulating layer 310 are sequentially formed on a semiconductor substrate (not shown). Here, the first interlayer insulating film 300 and the second interlayer insulating film 310 are formed of an oxide film, and the first etch stop layer 305 is formed of a nitride film.

Next, a first photoresist layer pattern 315 is formed on the second interlayer insulating layer 310 to open two predetermined fuse regions.

Next, the first interlayer insulating layer 310 and the first etch stop layer 305 are etched using the first photoresist pattern 315 as a mask to form two first trenches. Then, the first photosensitive film pattern 315 is removed.

Referring to FIG. 3B, a metal material is deposited on the first interlayer insulating layer 300 and the second interlayer insulating layer 310 including the first trench. Here, the metal material is preferably copper.

Next, CMP is performed until the second interlayer insulating layer 310 is exposed to form the first fuse pattern 320. Here, the first fuse pattern 320 is formed in a line shape, it is preferable to form a plurality. More preferably, two first fuse patterns 320 are formed.

Referring to FIG. 3C, a second etch stop layer 325 and a third interlayer insulating layer 330 are formed on the exposed second interlayer insulating layer 310 and the first fuse pattern 320.

Next, a second photosensitive film pattern 335 is formed on the third interlayer insulating film 330. Here, the second photoresist layer pattern 335 is formed to open the third interlayer insulating layer 330 on the first fuse pattern 320.

Next, the third interlayer insulating layer 330 is etched using the second photoresist pattern 335 as a mask to expose the second etch stop layer 325. In addition, the exposed second etch stop layer 325 is removed to form a second trench that exposes the first fuse pattern 320. Here, the second trench is preferably formed one by one on the first fuse pattern 320. Next, the second photosensitive film pattern 335 is removed.

Referring to FIG. 3D, after filling the second trench with a metal material, the contact 340 is formed by performing a CMP process until the third interlayer insulating layer 330 is exposed. In this case, the metal material is preferably copper, but is not necessarily limited to copper.

Referring to FIG. 3E, a fourth interlayer insulating layer 337 is formed on the contact 340 and the third interlayer insulating layer 330. Next, the fourth interlayer insulating film 337 is etched to form a third trench that is bent in a 's' shape. The third trench may be formed by etching until the third interlayer insulating layer 330 is exposed.

Next, a metal material is formed on the fourth interlayer insulating layer 337 including the third trench. The metal material may be formed of copper, which is the same material as the first fuse pattern 320.

Next, the CMP process is performed until the fourth interlayer insulating layer 337 is exposed to form the second fuse pattern 345. In this case, the second fuse pattern 345 may have a shape in which the blowing portion is bent in a 's' shape, and both edge portions of the second fuse pattern 345 may be connected to one contact 340. That is, the first fuse pattern 320 and the second fuse pattern 345 are connected to one line by the contact 340.

 Referring to FIG. 3F, a third photoresist layer pattern 360 is formed on the second fuse pattern 345 and the fourth interlayer insulating layer 337. Here, the third photoresist layer pattern 360 may be formed in a triangular shape in which the second fuse pattern 345 is completely covered. In this case, the fourth interlayer insulating layer 337 formed adjacent to the inner side of the bent portion of the second fuse pattern 345 is also covered.

Next, the fourth interlayer insulating film 337 is etched using the third photosensitive film pattern 360 as a mask. That is, the fourth interlayer insulating film 337 adjacent to the inside of the bent portion of the second fuse pattern 345 and the second fuse pattern 345 may protrude.

Referring to FIG. 3G, a capping layer 365 is formed on the surface of the third interlayer insulating layer 330 including the protruding second fuse pattern 345 and the fourth interlayer insulating layer 337. Here, the capping film 365 is preferably formed of a nitride film to protect the fuse pattern formed on the lower portion.

Referring to FIG. 3H, a fifth interlayer insulating layer 370 is formed on the capping layer 365. Next, a fourth photoresist layer pattern 375 is formed on the fifth interlayer insulating layer 370 to open the fuse blowing unit. Then, the fifth interlayer insulating layer 370 is repaired by using the fourth photoresist pattern 375 as a mask to form a fuse open region.

Next, the fuse is cut by a laser blowing process.

4A and 4B are plan views showing the state before the fuse blowing process and after the blowing process.

FIG. 4A illustrates a fuse pattern before a fuse blowing process, in which fuse patterns 320 and 350 having blown portions are bent in a '?' Shape, and an interlayer insulating layer formed of an oxide film inside the bent portions of the fuse patterns 320 and 350. (337) is present.

4B illustrates a fuse pattern after the fuse blowing process, in which the blowing portions of the fuse patterns 320 and 350 are cut by the laser. In this case, the interlayer insulating layer 337 existing between the cut fuse patterns 320 and 350 serves as a barrier to prevent the copper component from moving.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1A to 1D are cross-sectional views illustrating a fuse of a semiconductor device and a method of manufacturing the same according to the prior art.

2 is a perspective view illustrating a fuse of a semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention;

3A to 3H are perspective views illustrating a fuse of a semiconductor device and a method of manufacturing the same according to a second embodiment of the present invention.

Figure 4a and 4b is a plan view showing a state before and after blowing of the fuse according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

200, 300: first interlayer insulating film 210, 310: second interlayer insulating film

220: fuse pattern 305: etch stop film

315: first photosensitive film pattern 320: first fuse pattern

330: third interlayer insulating film 335: second photosensitive film pattern

337: fourth interlayer insulating film 345: second fuse pattern

360: third photosensitive film pattern 365: capping film

370: fifth interlayer insulating film 375: fourth photosensitive film pattern

Claims (22)

In the fuse part of a semiconductor element, A fuse pattern bent in a 'ㅅ' shape on the same plane; And An interlayer insulating layer formed inside and adjacent to the bent portion of the fuse pattern The fuse of the semiconductor device, characterized in that, wherein the bent portion of the fuse pattern is blown denial. Claim 2 has been abandoned due to the setting registration fee. The method of claim 1, The fuse pattern is a fuse of the semiconductor device, characterized in that formed of copper. delete Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The fuse pattern is a fuse of the semiconductor device, characterized in that formed in a single layer or a multi-layer structure. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 4, wherein The multilayer structure has a plurality of first fuse patterns in the form of a line is provided below, the fuse of the semiconductor device, characterized in that the second fuse pattern is connected to the first fuse pattern and the shape of the blown portion is provided. Claim 6 was abandoned when the registration fee was paid. The method of claim 5, And the first fuse pattern and the second fuse pattern are connected by a contact to form a single line. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 6, The contact is a fuse of the semiconductor device, characterized in that for connecting the end of the first fuse pattern and the second fuse pattern. Forming an interlayer insulating film on the semiconductor substrate; Etching the interlayer insulating film to form a fuse predetermined region bent in a 's' shape; Filling the fuse predetermined region with a metal material to form a fuse pattern; And Etching the interlayer insulating layer outside the fuse pattern to protrude the interlayer insulating layer adjacent to the fuse pattern and a bent portion of the fuse pattern; A fuse manufacturing method of a semiconductor device comprising a. Claim 9 was abandoned upon payment of a set-up fee. The metal material is a fuse manufacturing method of the semiconductor device, characterized in that the copper. Claim 10 was abandoned upon payment of a setup registration fee. The method of claim 8, The fuse pattern is a fuse manufacturing method of the semiconductor device, characterized in that the blowing portion is bent. Claim 11 was abandoned upon payment of a setup registration fee. The method of claim 8, And said interlayer insulating film is an oxide film. Claim 12 was abandoned upon payment of a registration fee. The method of claim 8, Etching the interlayer insulating film Forming a photoresist pattern covering the fuse pattern and the interlayer insulating layer formed at an inner side adjacent to the bent portion of the fuse pattern; And And etching the interlayer insulating layer using the photoresist pattern as a mask. Claim 13 was abandoned upon payment of a registration fee. 13. The method of claim 12, Forming a first interlayer insulating film and a second interlayer insulating film over the semiconductor substrate; Filling the second interlayer insulating layer with a metal material after etching to form a first fuse pattern having a line shape; Forming a third interlayer insulating layer on the first fuse pattern and the second interlayer insulating layer; Etching the third interlayer insulating layer and filling the metal layer with a metal material to form a contact connecting the first fuse pattern; Forming a fourth interlayer insulating film over the contact and the third interlayer insulating film; Etching the fourth interlayer insulating layer and filling the metal layer with a metal material to form a second fuse pattern connected to the contact and bent in a 's' shape; And Etching a portion of the fourth interlayer insulating film so that a fourth interlayer insulating film adjacent to an inner side of the second fuse pattern and the bent portion of the second fuse pattern is protruded. . Claim 15 was abandoned upon payment of a registration fee. The method of claim 14, The metal material is a fuse manufacturing method of the semiconductor device, characterized in that the copper. Claim 16 was abandoned upon payment of a setup registration fee. The method of claim 14, And the first, second, third and fourth interlayer insulating films are oxide films. Claim 17 has been abandoned due to the setting registration fee. The method of claim 14, And a plurality of first fuse patterns are formed. Claim 18 was abandoned upon payment of a set-up fee. The method of claim 14, The second fuse pattern is a fuse manufacturing method of the semiconductor element, characterized in that the blowing portion is bent. Claim 19 was abandoned upon payment of a registration fee. The method of claim 14, The contact is a fuse manufacturing method of the semiconductor device, characterized in that for connecting the end of the first fuse pattern and the second fuse pattern. Claim 20 was abandoned upon payment of a registration fee. The method of claim 14, And the first fuse pattern and the second fuse pattern are in the form of a single line by the contact. Claim 21 has been abandoned due to the setting registration fee. The method of claim 14, Etching the fourth interlayer insulating film Forming a photoresist pattern covering the second fuse pattern and the fourth interlayer insulating layer formed at an inner side adjacent to the bent portion of the second fuse pattern; And And etching the fourth interlayer insulating layer using the photoresist pattern as a mask. Claim 22 is abandoned in setting registration fee. The method of claim 21, The photosensitive film pattern is a fuse manufacturing method of the semiconductor device, characterized in that the triangular form.

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