KR20100039038A - The fuse in semiconductor device and method for manufacturing the same - Google Patents

The fuse in semiconductor device and method for manufacturing the same Download PDF

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Publication number
KR20100039038A
KR20100039038A KR1020080098240A KR20080098240A KR20100039038A KR 20100039038 A KR20100039038 A KR 20100039038A KR 1020080098240 A KR1020080098240 A KR 1020080098240A KR 20080098240 A KR20080098240 A KR 20080098240A KR 20100039038 A KR20100039038 A KR 20100039038A
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KR
South Korea
Prior art keywords
fuse
forming
layer
contact
pattern
Prior art date
Application number
KR1020080098240A
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Korean (ko)
Inventor
변홍철
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020080098240A priority Critical patent/KR20100039038A/en
Publication of KR20100039038A publication Critical patent/KR20100039038A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present invention relates to a fuse of a semiconductor device and a method of forming the same. By forming a plate pattern between the fuse pattern and the substrate, the stress generated during the fuse blowing process is prevented from being transferred to the substrate, thereby maximizing the space utilization under the fuse pattern. I was. In other words, it is possible to form patterns such as an active region, a gate electrode or a bit line in the lower space, thereby reducing the area of the chip, increase the net die, and improve the yield of the device to increase the yield .

Description

Fuse of Semiconductor Device and Formation Method {THE FUSE IN SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fuse of a semiconductor device and a method of forming the same. The present invention relates to a method for preventing a stress generated during a blowing process from being transferred downward.

In general, in the manufacture of a semiconductor device, especially a memory device, if any one of a number of fine cells is defective, the semiconductor device does not function as a memory and thus is treated as a defective product.

However, even though only a few cells in the memory have failed, discarding the entire device as a defective product is an inefficient treatment method in terms of yield.

Therefore, the current yield is improved by replacing a defective cell in which a defect has occurred by using a redundancy cell previously installed in the memory device.

A repair method using a spare cell typically includes a spare word line for replacing a normal word line and a spare bit line for replacing a normal bit line for each cell array, and includes a normal word including a cell when a defect occurs in a specific cell. The line or normal bit line is replaced with a spare word line or a spare bit line.

To this end, the memory device includes a circuit for changing an address corresponding to a defective cell to an address of a spare cell when a defective cell is found through testing after completion of wafer processing.

Therefore, when an address signal corresponding to a defective cell is input in actual use, the data of the spare cell replaced corresponding to the defective cell is accessed.

The most widely used repair method described above is to replace a path of an address by blowing and blowing a fuse with a laser beam.

Therefore, a conventional memory device includes a fuse unit capable of replacing an address path by irradiating a laser with a fuse to blow the laser. Here, the wiring broken by laser irradiation is called a fuse, and the fuse and the area | region surrounding it are called a fuse box.

1 illustrates a fuse of a semiconductor device according to the prior art.

Referring to FIG. 1, a first insulating layer 105 is formed on the semiconductor substrate 100. The first insulating layer 105 is etched and then filled with a conductive material to form a bit line contact 107. Next, a bit line 115 connected to the bit line contact 107 is formed on the first insulating layer 105.

Next, a second insulating film 116 and a third insulating film 120 are formed over the bit line 115 and the first insulating film 105. The third insulating layer 120 and the second insulating layer 116 are etched and then filled with a conductive material to form a first contact 125 connected to the bit line 115.

Next, the first metal wire 130 connected to the first contact 125 is formed.

Next, a fourth insulating layer 135 is formed on the first metal wire 130 and the third insulating layer 120. The fourth insulating layer 135 is etched and then embedded with a conductive material to form a second contact 140 connected to the first metal wire 130.

Next, a second metal wire 145 and a plurality of fuse patterns 150 are formed on the fourth insulating layer 135. Here, the second metal wire 145 may be formed to be connected to the second contact 140.

Next, a fifth insulating layer 155 and a passivation layer 160 are formed on the second metal wiring 145, the fuse pattern 150, and the fourth insulating layer 135.

The passivation layer 160 and the fifth insulating layer 155 are sequentially etched using a repair mask defining a fuse open area to form a fuse open area.

In this case, it is preferable that the fifth insulating layer 155 remain on the fuse pattern 150.

In such a fuse configuration, a laser blow fuse process causes side stress and vertical stress (hereinafter, referred to as vertical stress) to be cut when cutting a specific fuse pattern 150. do. At this time, the side stress is prevented from being transmitted to the outside by the fuse guard ring, but the vertical stress directed to the substrate causes a problem of damaging the pattern formed at the bottom or causing a crack in the insulating layer. As a result, it is impossible to form a pattern under the fuse pattern, which makes it difficult to efficiently use space.

The present invention is to improve the fuse guard ring structure to prevent the stress generated during the fuse blowing process is transferred to the substrate.

The fuse of the semiconductor device according to the invention

And a plate pattern formed on the semiconductor substrate, an insulating film formed on the plate pattern, and a plurality of fuse patterns formed on the insulating film.

Here, the plate pattern is formed of any one selected from the group consisting of a titanium nitride film and a polysilicon layer, further comprises a bit line on the semiconductor substrate, and further comprises a first metal wire connected to the plate pattern and the bit line. .

The first metal wire may further include a second metal wire connected to the first contact connected to the bit line and a second contact connected to the plate pattern, connected to the first metal wire, and formed on the insulating layer. Characterized in that.

In addition, the fuse forming method of the semiconductor device according to the present invention

Forming a plate pattern on the semiconductor substrate, forming an insulating film on the plate pattern, and forming a plurality of fuse patterns on the insulating film.

The method may further include forming a first insulating film including a bit line on the semiconductor substrate, wherein the plate pattern is formed of any one selected from the group consisting of a titanium nitride film and a polysilicon layer.

The forming of the plate pattern may include forming a plate layer on the semiconductor substrate, forming a photoresist pattern defining a fuse open region on the plate layer, and using the photoresist pattern as an etch mask. Patterning the plate layer.

The plate layer may be formed during a plate electrode forming process in a cell region. The forming of an insulating layer on the plate pattern may include forming a second insulating layer on the plate pattern and the first insulating layer. Forming a metal wire connected to the plate pattern on the second insulating film; and forming a third insulating film on the metal wire and the second insulating film.

The forming of the metal wiring may include forming a first contact hole through which the bit line is exposed and a second contact hole through which the plate pattern is exposed by selectively etching the second insulating layer and the first insulating layer; Filling the first contact hole and the second contact hole with a conductive material to form a first contact connected to the bit line and a second contact connected to the plate pattern, the first contact and the second contact; And forming a metal layer over the contact and the second insulating layer, and patterning the metal layer so that the first contact and the second contact are connected to each other.

The method may further include forming a fourth insulating layer and a passivation layer on the third insulating layer and the fuse pattern, and forming a fuse open region by selectively etching the passivation layer and the fourth insulating layer.

The fuse of the semiconductor device and the method of forming the same according to the present invention further form a plate pattern between the fuse pattern and the substrate, thereby preventing the stress generated during the fuse blowing process from being transferred to the substrate, thereby maximizing the space utilization of the lower portion of the fuse. Accordingly, a pattern such as an active region, a gate electrode, or a bitline can be formed under the fuse pattern, thereby reducing chip area and increasing net die. The yield of the device can be improved to increase the yield.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2 is a cross-sectional view illustrating a fuse of a semiconductor device according to the present invention.

Referring to FIG. 2, an interlayer insulating layer 205 including a bit line contact 207 is provided on the semiconductor substrate 200 and a bit line connected to the bit line contact 207 on the interlayer insulating layer 205. 215 is formed.

The first insulating layer 216 is formed on the bit line 215 and the interlayer insulating layer 205, and the plate pattern 217a is formed on the first insulating layer 216 of the fuse open region. At this time, the plate pattern 217a is preferably formed of any one selected from the group consisting of a titanium nitride film and a polysilicon layer.

The second insulating film 220 is formed on the plate pattern 217a and the first insulating film 216, and is connected to the bit line 215 through the second insulating film 220 and the first insulating film 216. The first contact 225 is provided, and the second contact 227 connected to the plate pattern 217a is formed through the second insulating film 220. In this case, the second contact 227 is formed to prevent the plate pattern 217a from being deformed or broken by the stress generated during the subsequent fuse blowing process.

In addition, a first metal wire 230 connected to the first contact 225 and the second contact 227 is provided on the second insulating film 220, and the first metal wire 230 and the second insulating film 220 are provided. A third insulating layer 235 including a third contact 240 connected to the first metal wire 230 is provided on the upper side of the substrate.

The second metal wire 245 connected to the fuse pattern 250 and the third contact 240 is provided on the third insulating layer 235.

The fourth insulating layer 255 and the passivation layer 260 defining the fuse open region are provided. In this case, the fourth insulating layer 255 is formed to partially remain on the fuse pattern 250.

3A through 3E are cross-sectional views illustrating a method of forming the fuse of FIG. 2.

Referring to FIG. 3A, an interlayer insulating layer 305 is formed on a semiconductor substrate 300 provided with an isolation layer (not shown) defining an active region.

Next, the interlayer insulating layer 305 is etched and then filled with a conductive material to form a bit line contact 307.

Thereafter, a bit line 315 connected to the bit line contact 307 is formed on the interlayer insulating layer 305.

Next, a first insulating layer 316 is formed on the bit line 315 and the interlayer insulating layer 305. In addition, a plate layer 317 is formed on the first insulating layer 316.

In this case, the plate layer 317 may be formed in the fuse region when the plate electrode of the cell region is formed, so that the plate layer 317 may be formed without an additional process. Here, the plate layer 317 is formed using any one selected from the group consisting of a titanium nitride film and a polysilicon layer.

Next, a first photosensitive film pattern 318 is formed on the plate layer 317 in the fuse open region to be opened.

Referring to FIG. 3B, the plate layer 317 is etched using the first photoresist pattern 318 as an etch mask to form a plate pattern 317a, and then the first photoresist pattern 318 is removed.

The second insulating layer 320 is formed on the plate pattern 317a and the first insulating layer 316. Next, a second photoresist layer pattern 322 defining a first contact hole (not shown) and a second contact hole (not shown) are formed on the second insulating layer 320.

Referring to FIG. 3C, the second contact layer 320 and the first insulation layer 316 are etched using the second photoresist layer pattern 322 as an etching mask to form a first contact hole (not shown) in which the bit line 315 is exposed. The second insulating layer 320 is etched to form a second contact hole (not shown) through which the plate pattern 317a is exposed.

At this time, the etching of the first contact hole (not shown) and the second contact hole (not shown) are performed at the same time, and the first contact hole ( The etching stops at the point where the bit line 315 is exposed, and the etching stops at the point where the plate pattern 317a is exposed at the second contact hole (not shown).

Thereafter, the second photosensitive film pattern 322 is removed.

Next, a first contact hole (not shown) and a second contact hole (not shown) are filled with a conductive material to form a first contact 325 and a second contact 327.

Here, the second contact 327 is formed to prevent the plate pattern 317a from being deformed or broken by the stress generated during the subsequent fuse blowing process. That is, the structure of the plate pattern 317a is connected to and supported by the first metal wire 330, which is an existing fuse guard ring.

Referring to FIG. 3D, a metal layer (not shown) is formed on the second insulating layer 320. The metal layer (not shown) is patterned to form a first metal wire 330 connected to the first contact 325 and the second contact 327 simultaneously.

Referring to FIG. 3E, a third insulating film 335 is formed on the first metal wire 330 and the second insulating film 320.

Next, the third insulating layer 335 is etched to form a third contact hole (not shown) through which the first metal wire 330 is exposed. Next, a third contact hole (not shown) is filled with a conductive material to form a third contact 340.

A second metal wire 345 is formed on the third contact 340 and the third insulating layer 335 to form a metal layer (not shown) and pattern the metal layer (not shown) to be connected to the third contact 240. And a plurality of fuse patterns 350 are formed in the fuse region.

Next, a fourth insulating film 355 and a passivation layer 360 are formed on the second metal wiring 345, the fuse pattern 350, and the third insulating film 335. Next, a third photoresist pattern (not shown) is formed on the passivation layer 360 by using a repair mask defining a fuse open region.

Next, the passivation layer 360 and the fourth insulating layer 355 are selectively etched using the third photoresist pattern (not shown) as an etch mask to form a fuse open region 365. Then, the third photosensitive film pattern (not shown) is removed. In this case, it is preferable to leave the fourth insulating layer 355 on the fuse pattern 350.

In such a fuse configuration, a specific fuse pattern 350 is cut by a fuse blowing process using a laser. At this time, in the fuse blowing process, side stresses and vertical stresses occur on the substrate. Here, the side stress is prevented from being transmitted to the outside by the fuse guardring, and the vertical stress is prevented from being transferred to the substrate by the plate pattern 317a.

As such, the present invention improves the fuse guard ring structure that is vulnerable to vertical stress, thereby maximizing the utilization of the lower space of the fuse pattern, which was not available in the prior art.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1 is a cross-sectional view showing a fuse of a semiconductor device according to the prior art.

2 is a cross-sectional view showing a fuse of a semiconductor device according to the present invention.

3A to 3E are cross-sectional views illustrating a fuse forming method of a semiconductor device according to the present invention.

<Explanation of Signs of Major Parts of Drawings>

300 semiconductor substrate 305 interlayer insulating film

307: bit line contact 315: bit line

316: First insulating film 317: Plate layer

317a: Plate pattern 318: First photosensitive film pattern

320: second insulating film 322: second photosensitive film pattern

325: First contact 327: Second contact

330: first metal wiring 335: third insulating film

370: third contact 345: second metal wiring

350: fuse pattern 355: fourth insulating film

360: passivation layer 365: fuse open area

Claims (14)

A plate pattern formed on the semiconductor substrate; An insulating film formed on the plate pattern; And A plurality of fuse patterns formed on the insulating layer A fuse of the semiconductor device comprising a. The method of claim 1, The plate pattern is a fuse of the semiconductor device, characterized in that formed in any one selected from the group consisting of a titanium nitride film and a polysilicon layer. The method of claim 1, And a bit line on the semiconductor substrate. The method of claim 3, wherein And a first metal wire connected to the plate pattern and the bit line. The method of claim 4, wherein And the first metal wire is connected to a first contact connected to the bit line and a second contact connected to the plate pattern. The method of claim 4, wherein And a second metal wire connected to the first metal wire and formed on the insulating layer. Forming a plate pattern on the semiconductor substrate; Forming an insulating film on the plate pattern; And Forming a plurality of fuse patterns on the insulating layer; A fuse forming method of a semiconductor device comprising a. The method of claim 7, wherein And forming a first insulating film including a bit line on the semiconductor substrate. The method of claim 7, wherein And the plate pattern is formed of any one selected from the group consisting of a titanium nitride film and a polysilicon layer. The method of claim 7, wherein Forming the plate pattern Forming a plate layer on the semiconductor substrate; Forming a photoresist pattern on the plate layer to define a fuse open region; And Patterning the plate layer using the photoresist pattern as an etch mask A fuse forming method of a semiconductor device comprising a. The method of claim 10, And the plate layer is formed during a plate electrode forming process in a cell region. The method of claim 8, Forming an insulating film on the plate pattern is Forming a second insulating film on the plate pattern and the first insulating film; Forming a metal wire connected to the plate pattern on the second insulating layer; And Forming a third insulating film on the metal wire and the second insulating film A fuse forming method of a semiconductor device comprising a. The method of claim 12, Forming the metal wiring Selectively etching the second insulating layer and the first insulating layer to form a first contact hole through which the bit line is exposed and a second contact hole through which the plate pattern is exposed; Filling the first contact hole and the second contact hole with a conductive material to form a first contact connected to the bit line and a second contact connected to the plate pattern; Forming a metal layer on the first contact, the second contact, and the second insulating layer; And Patterning the metal layer to connect the first contact and the second contact; A fuse forming method of a semiconductor device comprising a. The method of claim 12, Forming a fourth insulating film and a passivation layer on the third insulating film and the fuse pattern; And Selectively etching the passivation layer and the fourth insulating layer to form a fuse open region A fuse forming method of a semiconductor device further comprising.
KR1020080098240A 2008-10-07 2008-10-07 The fuse in semiconductor device and method for manufacturing the same KR20100039038A (en)

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KR1020080098240A KR20100039038A (en) 2008-10-07 2008-10-07 The fuse in semiconductor device and method for manufacturing the same

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876326A (en) * 2017-02-14 2017-06-20 上海华虹宏力半导体制造有限公司 Integrated circuit with laser fuse and forming method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106876326A (en) * 2017-02-14 2017-06-20 上海华虹宏力半导体制造有限公司 Integrated circuit with laser fuse and forming method thereof

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