KR20100011243A - Non volatile memory device with aluminium nitride and method for fabricating the same - Google Patents

Non volatile memory device with aluminium nitride and method for fabricating the same Download PDF

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KR20100011243A
KR20100011243A KR1020080072377A KR20080072377A KR20100011243A KR 20100011243 A KR20100011243 A KR 20100011243A KR 1020080072377 A KR1020080072377 A KR 1020080072377A KR 20080072377 A KR20080072377 A KR 20080072377A KR 20100011243 A KR20100011243 A KR 20100011243A
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film
layer
buffer
charge
gate electrode
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이기홍
박기선
황선환
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

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Abstract

PURPOSE: A nonvolatile memory device with aluminium nitride and a method for fabricating the same is provided to prevent the formation of a parasitic oxide on the interface between a charge block layer and a gate electrode by inserting a buffer layer into the charge block layer and the gate electrode. CONSTITUTION: A charge block layer(103) is interposed between a charge trap layer(102) and a gate electrode(105). The buffer layer(104) is interposed between the charge block layer and the gate electrode. The buffer layer is formed between the charge trap layer and the charge block layer. The buffer is formed with a material having a higher crystallization temperature than the charge block layer. The buffer layer has a crystallization temperature of at least 800°C.

Description

알루미늄질화막을 구비하는 비휘발성메모리장치 및 그 제조 방법{NON VOLATILE MEMORY DEVICE WITH ALUMINIUM NITRIDE AND METHOD FOR FABRICATING THE SAME}Non-volatile memory device having an aluminum nitride film and a manufacturing method thereof {NON VOLATILE MEMORY DEVICE WITH ALUMINIUM NITRIDE AND METHOD FOR FABRICATING THE SAME}

본 발명은 비휘발성메모리장치에 관한 것으로서, 특히 전하트랩형 비휘발성메모리장치에 관한 것이다.The present invention relates to a nonvolatile memory device, and more particularly to a charge trap type nonvolatile memory device.

비휘발성메모리장치는 전하저장막의 종류에 따라 부유게이트(Floating Gate; FG)형과 전하트랩(Charge Trap)형으로 구분되며, 부유게이트형은 부유게이트 내에 자유전하의 형태로 전하를 저장하고, 전하 트랩형은 전하저장막 내에서 공간적으로 격리된 트랩에 전하를 저장한다.A nonvolatile memory device is classified into a floating gate (FG) type and a charge trap type according to the type of charge storage layer, and the floating gate type stores charges in the form of free charge in the floating gate. The trap type stores charge in traps spatially isolated within the charge storage film.

도 1은 종래기술에 따른 전하트랩형 비휘발성메모리장치를 도시한 도면이다.1 is a view showing a charge trap type nonvolatile memory device according to the prior art.

도 1에 도시된 바와 같이, 전하트랩형 비휘발성메모리장치는 기판(11) 상에 터널절연막(12)이 형성되고, 터널절연막(12) 상에 전하트랩막(Charge trap layer, 13)이 형성된다. 전하트랩막(13) 상에는 전하차단막(Charge Blocking layer, 14)이 형성되고, 전하차단막(14) 상에는 게이트전극(15)이 형성된다.As shown in FIG. 1, in the charge trap type nonvolatile memory device, a tunnel insulating layer 12 is formed on a substrate 11, and a charge trap layer 13 is formed on the tunnel insulating layer 12. do. A charge blocking layer 14 is formed on the charge trap layer 13, and a gate electrode 15 is formed on the charge blocking layer 14.

도 1에서 전하차단막(14)은 터널절연막(12)을 통과한 전자들이 전하트랩막(13)에 트랩되는 과정에서 게이트전극(15)으로 이동하는 것을 차단하는 역할을 한다. 전하차단막(14)은 알루미늄산화막(Al2O3)을 이용하고 있다.In FIG. 1, the charge blocking film 14 blocks the electrons passing through the tunnel insulating film 12 from moving to the gate electrode 15 while being trapped by the charge trap film 13. The charge blocking film 14 uses an aluminum oxide film (Al 2 O 3 ).

그러나, 종래기술은 게이트전극으로 사용되는 물질 증착시 게이트전극(15)과 전하차단막(14)의 계면(interface)에 게이트전극으로 사용된 물질에 의한 기생산화막(16)이 형성되고, 후속하여 열공정이 수반되는 경우에는 기생산화막이 추가로 더 생성되는 문제가 발생한다.However, in the prior art, the vaporization film 16 made of the material used as the gate electrode is formed at the interface between the gate electrode 15 and the charge blocking film 14 during the deposition of the material used as the gate electrode, and subsequently the thermal hole is formed. In the case of accompanying tablets, a problem arises in that an additional production film is further generated.

또한, 종래기술은 전하차단막(14) 위에 게이트전극(15)을 직접 증착하는 경우 전하차단막(14)의 상변화가 발생하는 문제가 있다. 즉, 전하차단막(14)으로 사용된 알루미늄산화막의 경우 증착상태에서는 비정질상태이나 후속 열공정(600 ℃ 이상)에 의해서 결정질로 바뀌게 된다. 즉, 알루미늄산화막은 결정화온도가 600℃ 이하로 매우 낮기 때문에 후속하여 600℃ 이상의 고온 열공정이 수반되면 결정화가 쉽게 일어난다.In addition, the prior art has a problem that a phase change of the charge blocking film 14 occurs when the gate electrode 15 is directly deposited on the charge blocking film 14. That is, in the case of the aluminum oxide film used as the charge blocking film 14, it is changed to a crystalline state in the deposition state by an amorphous state or a subsequent thermal process (600 ° C. or more). That is, since the aluminum oxide film has a very low crystallization temperature of 600 ° C. or lower, crystallization easily occurs when a high temperature thermal process of 600 ° C. or higher is subsequently performed.

이와 같이 결정질로 상변화가 발생하면 알루미늄산화막의 내부에는 많은 결정립계(grain boundary)가 존재하게 되고, 이러한 많은 결정립계에 의해 게이트전극 증착시 사용되는 여러 화학종(chemical species)이 빠르게 알루미늄산화막 내부로 확산되어(도면부호 '17' 참조) 막 자체를 열화(degradation)시키거나 하부 막(즉 전하트랩막)에도 영향을 미칠 수 있다.As such, when a phase change occurs due to crystalline, many grain boundaries exist inside the aluminum oxide film, and many chemical species used for deposition of the gate electrode rapidly diffuse into the aluminum oxide film due to the many grain boundaries. (See reference numeral 17) may degrade the film itself or affect the underlying film (ie charge trap film).

상술한 바와 같이 전하차단막과 게이트전극의 계면에 형성되는 기생산화막이나 후속 열공정에서 화학종의 확산이 발생되면 비휘발성메모리장치의 데이터유지특성, 프로그램 및 소거특성이 저하된다.As described above, when chemical species is diffused in the pre-production film formed at the interface between the charge blocking film and the gate electrode or in a subsequent thermal process, data retention, program and erase characteristics of the nonvolatile memory device are degraded.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 전하차단막과 게이트전극의 계면에서 기생산화막이 형성되는 것을 방지할 수 있는 비휘발성메모리장치 및 그 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a nonvolatile memory device and a method of manufacturing the same, which can prevent formation of a pre-production film at an interface between a charge blocking film and a gate electrode. .

또한, 본 발명의 다른 목적은 후속 게이트전극 증착시에 화학종이 전하차단막으로 확산하는 것을 방지할 수 있는 비휘발성메모리장치 및 그 제조 방법을 제공하는데 있다.Another object of the present invention is to provide a nonvolatile memory device and a method of manufacturing the same, which can prevent chemical species from diffusing into the charge blocking layer during subsequent gate electrode deposition.

상기 목적을 달성하기 위한 본 발명의 비휘발성메모리장치는 전하차단막과 게이트전극 사이에 형성된 버퍼막을 포함하는 것을 특징으로 하고, 상기 전하트랩막과 전하차단막 사이에 형성된 버퍼막을 더 포함하는 것을 특징으로 한다. 상기 버퍼막은 상기 전하차단막보다 결정화온도가 높은 물질이고, 상기 버퍼막은 결정화온도가 적어도 800℃ 이상인 물질이며, 상기 버퍼막은 비정질인 것을 특징으로 한다. 상기 버퍼막은 알루미늄질화막(AlN)을 포함하고, 상기 전하차단막은 알루미늄산화막(Al2O3) 또는 실리콘산화막(SiO2)을 포함하는 것을 특징으로 한다.A nonvolatile memory device of the present invention for achieving the above object comprises a buffer film formed between the charge blocking film and the gate electrode, characterized in that it further comprises a buffer film formed between the charge trap film and the charge blocking film. . The buffer film is a material having a higher crystallization temperature than the charge blocking film, the buffer film is a material having a crystallization temperature of at least 800 ℃ or more, the buffer film is characterized in that the amorphous. The buffer layer may include an aluminum nitride layer (AlN), and the charge blocking layer may include an aluminum oxide layer (Al 2 O 3 ) or a silicon oxide layer (SiO 2 ).

그리고, 본 발명의 비휘발성메모리장치 제조 방법은 기판 상에 터널절연막을 형성하는 단계; 상기 터널절연막 상에 전하트랩막을 형성하는 단계; 상기 전하트랩 막 상에 전하차단막을 형성하는 단계; 상기 전하차단막 상에 버퍼막을 형성하는 단계; 및 상기 버퍼막 상에 게이트전극을 형성하는 단계를 포함하고, 상기 전하트랩막과 전하차단막 사이에 버퍼막을 더 형성하는 것을 특징으로 한다.In addition, the method of manufacturing a nonvolatile memory device of the present invention comprises the steps of forming a tunnel insulating film on a substrate; Forming a charge trap film on the tunnel insulating film; Forming a charge blocking film on the charge trap film; Forming a buffer film on the charge blocking film; And forming a gate electrode on the buffer film, and further forming a buffer film between the charge trap film and the charge blocking film.

상술한 본 발명은 전하차단막과 게이트전극 사이에 버퍼막을 삽입하므로써 후속 열공정시에 전하차단막과 게이트전극의 계면에서 기생산화막이 형성되는 것을 방지할 수 있다. 아울러, 게이트전극 증착시 화학종이 확산하는 것을 방지할 수 있다.In the present invention described above, by inserting the buffer film between the charge blocking film and the gate electrode, it is possible to prevent the formation of the pre-production film at the interface between the charge blocking film and the gate electrode during the subsequent thermal process. In addition, it is possible to prevent the chemical species from spreading during the deposition of the gate electrode.

결국, 본 발명은 비휘발성메모리장치의 데이터유지특성, 프로그램 및 소거특성을 향상시킬 수 있는 효과가 있다.As a result, the present invention has the effect of improving data retention characteristics, programs and erase characteristics of the nonvolatile memory device.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

본 발명에서는 전하차단막과 게이트전극 사이에 버퍼막(Buffer layer)을 삽입한다. 버퍼막을 삽입하므로써 후속 열공정시에 전하차단막과 게이트전극의 계면에서 기생산화막이 형성되는 것을 방지할 수 있다. 아울러, 버퍼막은 화학종의 확산방지막으로 기능하여 게이트전극 증착시 화학종이 확산하는 것을 방지할 수 있 다.In the present invention, a buffer layer is inserted between the charge blocking film and the gate electrode. By inserting the buffer film, it is possible to prevent the formation of the pre-production film at the interface between the charge blocking film and the gate electrode during the subsequent thermal process. In addition, the buffer film may function as a diffusion barrier of the chemical species to prevent the chemical species from diffusing during the deposition of the gate electrode.

이하 실시예들에서 버퍼막은 비정질 물질을 사용한다. 바람직하게, 버퍼막은 비정질이면서도 고온 열공정시에도 결정화가 쉽게 일어나지 않는 물질을 사용한다. 즉, 버퍼막은 비정질이면서 결정화온도가 높은 물질을 사용한다. 바람직하게, 버퍼막은 알루미늄질화막(AlN)을 포함한다.In the following embodiments, the buffer layer uses an amorphous material. Preferably, the buffer film is made of an amorphous material that does not easily crystallize even at a high temperature thermal process. That is, the buffer film is made of an amorphous material with a high crystallization temperature. Preferably, the buffer film includes an aluminum nitride film (AlN).

알루미늄산화막(Al2O3)은 600℃ 이상의 고온 열공정에서 결정화가 일어나지만, 알루미늄질화막(AlN)은 600℃ 이상의 고온 열공정에 의해서도 결정화가 쉽게 일어나지 않는다. 알루미늄질화막은 800℃ 이상의 높은 결정화온도를 갖는다.Crystallization of the aluminum oxide film (Al 2 O 3 ) occurs at a high temperature thermal process of 600 ° C. or higher, but crystallization of the aluminum nitride film (AlN) does not occur easily even at the high temperature thermal process of 600 ° C. or higher. The aluminum nitride film has a high crystallization temperature of 800 deg.

알루미늄질화막은 비정질이기 때문에 결정립계가 존재하지 않고, 이에 따라 확산경로가 없으므로 화학종의 확산을 방지할 수 있다.Since the aluminum nitride film is amorphous, there is no grain boundary, and thus there is no diffusion path, thereby preventing the diffusion of chemical species.

도 2는 본 발명의 제1실시예에 따른 비휘발성메모리장치의 구조를 도시한 도면이다.2 is a diagram showing the structure of a nonvolatile memory device according to the first embodiment of the present invention.

도 2를 참조하면, 기판(100) 상에 터널절연막(101)이 형성된다. 터널절연막(101) 상에 전하트랩막(102)이 형성되며, 전하트랩막(102) 상에 전하차단막(103)이 형성된다. 전하차단막(103) 상에 버퍼막(104)이 형성되고, 버퍼막(104) 상에 게이트전극(105)이 형성된다. 따라서, 전하차단막(103)과 게이트전극(105) 사이에 버퍼막(104)이 존재하는 구조가 된다.Referring to FIG. 2, a tunnel insulating film 101 is formed on the substrate 100. The charge trapping film 102 is formed on the tunnel insulating film 101, and the charge blocking film 103 is formed on the charge trapping film 102. The buffer film 104 is formed on the charge blocking film 103, and the gate electrode 105 is formed on the buffer film 104. Therefore, the buffer film 104 is present between the charge blocking film 103 and the gate electrode 105.

기판(100)은 실리콘기판을 포함하며, 실리콘기판은 P형 도전형 또는 N형 도전형의 불순물이 도핑될 수 있다. 바람직하게는 붕소(Boron)와 같은 P형 도전형 불 순물이 도핑되어 있을 수 있다. 또한, 기판(100)은 채널영역과 채널영역 양측에 형성된 소스영역과 드레인영역이 형성되어 있을 수 있다.The substrate 100 may include a silicon substrate, and the silicon substrate may be doped with impurities of a P-type conductivity or an N-type conductivity. Preferably, the P-type impurity such as boron may be doped. In addition, the substrate 100 may include a source region and a drain region formed at both sides of the channel region and the channel region.

게이트전극(105)은 TiN, WN 또는 TaN 중에서 선택된 적어도 어느 하나의 금속질화막을 포함할 수 있다. 또한 게이트전극(105)은 폴리실리콘막을 포함할 수도 있다. 게이트전극(105)이 금속질화막인 경우에는 MANOS(Metal Al2O3 Nitride Oxide Silicon) 구조가 되고, 폴리실리콘막인 경우에는 SONOS(Silicon Oxide Nitride Oxide Silicon) 구조가 된다. 게이트전극(105) 위에는 저항을 낮추기 위한 저저항 금속막(Low resistive metal)으로서 텅스텐실리사이드막 또는 텅스텐막이 더 형성될 수 있다. The gate electrode 105 may include at least one metal nitride film selected from TiN, WN or TaN. In addition, the gate electrode 105 may include a polysilicon film. In the case where the gate electrode 105 is a metal nitride film, the metal oxide film is MANOS (Metal Al 2 O 3 Nitride Oxide Silicon) structure, and in the case of the polysilicon film, the silicon electrode nitride Nitride Oxide Silicon (SONOS) structure is used. A tungsten silicide film or a tungsten film may be further formed on the gate electrode 105 as a low resistive metal for lowering the resistance.

터널절연막(101)은 기판(100) 및 전하트랩막(102)보다 에너지밴드갭이 큰 물질을 포함한다. 바람직하게, 터널절연막(101)은 산화막 또는 질소가 혼합된 산화막을 포함할 수 있는데, 예를 들어, 실리콘산화막(SiO2) 또는 실리콘산화질화막(SiON)을 포함한다. 이와 같이, 터널절연막(101)이 에너지밴드갭이 크면 프로그램되어 전하트랩막(102)에 저장되어 있는 전하가 쉽게 이동하지 못한다. 터널절연막(101)은 20Å 이상의 두께로 형성한다. 터널절연막(101)은 열산화 공정이나 라디칼산화(radical oxidation) 공정 등을 통해서 형성할 수 있다.The tunnel insulating film 101 includes a material having a larger energy band gap than the substrate 100 and the charge trap film 102. Preferably, the tunnel insulating film 101 may include an oxide film or an oxide film containing nitrogen, for example, a silicon oxide film (SiO 2 ) or a silicon oxynitride film (SiON). As such, when the tunnel insulation layer 101 has a large energy band gap, the charge stored in the charge trap layer 102 cannot be easily moved. The tunnel insulating film 101 is formed to a thickness of 20 kPa or more. The tunnel insulation film 101 may be formed through a thermal oxidation process or a radical oxidation process.

전하트랩막(102)은 터널절연막(101)을 통해 주입된 전자(Electron)이나 정공(Hole)을 트랩(trap)하는 기능을 갖는 막으로서, '전하축적층' 또는 '전하저장층'이라고도 한다. 전하트랩막(102)은 트랩사이트 밀도(Trap site density)가 높도 록 질소가 혼합된 물질을 포함하는데, 예를 들어, 실리콘질화막(Si3N4)을 포함할 수 있다. 전하트랩막(102)은 원자층증착법(Atomic Layer Deposition; ALD)이나 화학기상증착법(Chemical Vapor Deposition; CVD)으로 증착한다. The charge trap film 102 is a film having a function of trapping electrons or holes injected through the tunnel insulating film 101 and is also referred to as a charge storage layer or a charge storage layer. . The charge trap layer 102 may include a material in which nitrogen is mixed so that a trap site density is high. For example, the charge trap layer 102 may include a silicon nitride layer (Si 3 N 4 ). The charge trap film 102 is deposited by atomic layer deposition (ALD) or chemical vapor deposition (CVD).

전하트랩막(102) 상에 형성된 전하차단막(103)은 터널절연막(101)을 통과한 전자들이 전하트랩막(102)에 트랩되는 과정에서 게이트전극(105)으로 이동하는 것을 차단하는 역할을 한다. 전하차단막(103)은 알루미늄산화막 또는 실리콘산화막을 포함할 수 있다. 여기서, 알루미늄산화막(Al2O3)은 화학기상증착법(CVD) 또는 원자층증착법(ALD)에 의해 형성되고, 실리콘산화막(SiO2)은 화학기상증착법(CVD)에 형성된 것이다. 알루미늄산화막을 형성한 후에는 급속열처리(Rapid Thermal Process; RTP)가 진행될 수 있다. 급속열처리(RTP)에 의해 알루미늄산화막은 치밀화되어 막질이 향상되고, 이에 따라 전하차단막으로서의 기능이 증대될 수 있다.The charge blocking film 103 formed on the charge trap film 102 serves to block the electrons passing through the tunnel insulating film 101 from moving to the gate electrode 105 while being trapped by the charge trap film 102. . The charge blocking film 103 may include an aluminum oxide film or a silicon oxide film. Here, the aluminum oxide film (Al 2 O 3 ) is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the silicon oxide film (SiO 2 ) is formed by chemical vapor deposition (CVD). After the aluminum oxide film is formed, a rapid thermal process (RTP) may be performed. By rapid heat treatment (RTP), the aluminum oxide film is densified to improve film quality, thereby increasing the function as a charge blocking film.

버퍼막(104)은 후속 열공정시에 전하차단막(103)과 게이트전극(105)의 계면에서 기생산화막이 형성되는 것을 방지하는 역할을 한다. 아울러, 버퍼막(104)은 화학종의 확산방지막으로 기능하여 게이트전극(105) 증착시 화학종이 확산하는 것을 방지하는 역할도 한다. 버퍼막(104)은 결정립계가 없는 비정질 물질을 사용한다. 바람직하게, 버퍼막(104)은 비정질이면서도 고온 열공정시에도 상변화(Phase change)가 없는 물질을 사용한다. 고온열공정시에도 상변화가 없는 물질이란 결정화온도가 높은 물질을 의미한다. 따라서, 버퍼막(104)은 비정질이면서도 결정화온도가 높은 물질을 포함한다. 여기서, 버퍼막(104)의 결정화온도는 전하차단막(103) 의 결정화온도보다 높은 것이 바람직하다. 전하차단막(103)으로 사용된 물질이 알루미늄산화막인 경우, 버퍼막(104)은 알루미늄산화막보다 결정화온도가 높은 물질을 포함할 수 있다. 버퍼막(104)은 알루미늄질화막(AlN)을 포함한다. 알루미늄산화막(Al2O3)은 600℃ 이상의 고온 열공정에서 결정화가 일어나지만, 알루미늄질화막(AlN)은 600℃ 이상의 고온 열공정에 의해서도 결정화가 쉽게 일어나지 않는다. 알루미늄질화막은 적어도 800℃ 이상(800∼1000℃)의 높은 결정화온도를 갖는다. 게이트전극(105)으로 사용된 물질은 주로 500∼650℃의 범위에서 증착하기 때문에, 알루미늄질화막(AlN)은 결정화되지 않고 비정질을 유지할 수 있다.The buffer film 104 serves to prevent formation of the pre-production film at the interface between the charge blocking film 103 and the gate electrode 105 during the subsequent thermal process. In addition, the buffer film 104 serves as a diffusion barrier of the chemical species to prevent the chemical species from diffusing when the gate electrode 105 is deposited. The buffer film 104 uses an amorphous material having no grain boundary. Preferably, the buffer film 104 is made of a material that is amorphous and does not have a phase change even in a high temperature thermal process. A material without phase change even at a high temperature heat process means a material having a high crystallization temperature. Accordingly, the buffer film 104 includes an amorphous material and a high crystallization temperature. Here, the crystallization temperature of the buffer film 104 is preferably higher than the crystallization temperature of the charge blocking film 103. When the material used as the charge blocking film 103 is an aluminum oxide film, the buffer film 104 may include a material having a higher crystallization temperature than the aluminum oxide film. The buffer film 104 includes an aluminum nitride film (AlN). Crystallization of the aluminum oxide film (Al 2 O 3 ) occurs at a high temperature thermal process of 600 ° C. or higher, but crystallization of the aluminum nitride film (AlN) does not occur easily even at the high temperature thermal process of 600 ° C. or higher. The aluminum nitride film has a high crystallization temperature of at least 800 ° C or more (800 to 1000 ° C). Since the material used for the gate electrode 105 is mainly deposited in the range of 500 to 650 ° C., the aluminum nitride film AlN can remain amorphous without being crystallized.

또한, 알루미늄질화막은 비정질이기 때문에 결정립계가 존재하지 않고, 이에 따라 확산경로가 없으므로 화학종의 확산을 방지할 수 있다.In addition, since the aluminum nitride film is amorphous, there is no grain boundary, and accordingly, there is no diffusion path, thereby preventing the diffusion of chemical species.

도 3은 본 발명의 제2실시예에 따른 비휘발성메모리장치의 구조를 도시한 도면이다.3 is a diagram illustrating a structure of a nonvolatile memory device according to a second embodiment of the present invention.

도 3을 참조하면, 기판(200) 상에 터널절연막(201)이 형성된다. 터널절연막(201) 상에 전하트랩막(202)이 형성되며, 전하트랩막(202) 상에 제1버퍼막(204A), 전하차단막(203) 및 제2버퍼막(204B)의 적층구조가 형성된다. 제2버퍼막(204B) 상에는 게이트전극(205)이 형성된다. 따라서, 전하차단막(203)과 게이트전극(205) 사이에 제1버퍼막(204A), 전하차단막(203) 및 제2버퍼막(204B)의 3층 구조가 존재한다.Referring to FIG. 3, a tunnel insulating film 201 is formed on the substrate 200. A charge trap film 202 is formed on the tunnel insulating film 201, and a stacked structure of the first buffer film 204A, the charge blocking film 203, and the second buffer film 204B is formed on the charge trap film 202. Is formed. The gate electrode 205 is formed on the second buffer film 204B. Therefore, a three-layer structure exists between the charge blocking film 203 and the gate electrode 205, which is the first buffer film 204A, the charge blocking film 203, and the second buffer film 204B.

기판(200)은 실리콘기판을 포함하며, 실리콘기판은 P형 도전형 또는 N형 도 전형의 불순물이 도핑될 수 있다. 바람직하게는 붕소(Boron)와 같은 P형 도전형 불순물이 도핑되어 있을 수 있다. 또한, 기판(200)은 채널영역과 채널영역 양측에 형성된 소스영역과 드레인영역이 형성되어 있을 수 있다.The substrate 200 may include a silicon substrate, and the silicon substrate may be doped with an impurity of P-type conductivity or N-type conductivity. Preferably, P-type conductive impurities such as boron may be doped. In addition, the substrate 200 may include a source region and a drain region formed at both sides of the channel region and the channel region.

게이트전극(205)은 TiN, WN 또는 TaN 중에서 선택된 적어도 어느 하나의 금속질화막을 포함할 수 있다. 또한 게이트전극(205)은 폴리실리콘막을 포함할 수도 있다. 게이트전극(205)이 금속질화막인 경우에는 MANOS(Metal Al2O3 Nitride Oxide Silicon) 구조가 되고, 폴리실리콘막인 경우에는 SONOS(Silicon Oxide Nitride Oxide Silicon) 구조가 된다. 게이트전극(205) 위에는 저항을 낮추기 위한 저저항 금속막(Low resistive metal)으로서 텅스텐실리사이드막 또는 텅스텐막이 더 형성될 수 있다. The gate electrode 205 may include at least one metal nitride film selected from TiN, WN or TaN. In addition, the gate electrode 205 may include a polysilicon film. In the case where the gate electrode 205 is a metal nitride film, it has a MANOS (Metal Al 2 O 3 Nitride Oxide Silicon) structure, and in the case of a polysilicon film, it has a silicon oxide nitride oxide (SONOS) structure. A tungsten silicide film or a tungsten film may be further formed on the gate electrode 205 as a low resistive metal for lowering the resistance.

터널절연막(201)은 기판(200) 및 전하트랩막(202)보다 에너지밴드갭이 큰 물질을 포함한다. 바람직하게, 터널절연막(201)은 산화막 또는 질소가 혼합된 산화막을 포함할 수 있는데, 예를 들어, 실리콘산화막(SiO2) 또는 실리콘산화질화막(SiON)을 포함한다. 이와 같이, 터널절연막(201)이 에너지밴드갭이 크면 프로그램되어 전하트랩막(202)에 저장되어 있는 전하가 쉽게 이동하지 못한다.The tunnel insulating film 201 includes a material having a larger energy band gap than the substrate 200 and the charge trap film 202. Preferably, the tunnel insulating film 201 may include an oxide film or an oxide film mixed with nitrogen. For example, the tunnel insulating film 201 may include a silicon oxide film (SiO 2 ) or a silicon oxynitride film (SiON). As such, when the tunnel insulating layer 201 has a large energy band gap, the charge stored in the charge trap layer 202 may not be easily moved.

전하트랩막(202)은 터널절연막(201)을 통해 주입된 전자(Electron)이나 정공(Hole)을 트랩(trap)하는 기능을 갖는 막으로서, 전하축적층이라고도 한다. 전하트랩막(202)은 트랩사이트 밀도(Trap site density)가 높도록 질소가 혼합된 물질을 포함하는데, 예를 들어, 실리콘질화막(Si3N4)을 포함할 수 있다. 터널절연 막(201)은 20Å 이상의 두께로 형성한다. 터널절연막(201)은 열산화 공정이나 라디칼산화(radical oxidation) 공정 등을 통해서 형성할 수 있다.The charge trap film 202 has a function of trapping electrons or holes injected through the tunnel insulating film 201 and is also called a charge storage layer. The charge trap film 202 may include a material in which nitrogen is mixed such that a trap site density is high. For example, the charge trap film 202 may include a silicon nitride film (Si 3 N 4 ). The tunnel insulating film 201 is formed to a thickness of 20 kPa or more. The tunnel insulating film 201 may be formed through a thermal oxidation process or a radical oxidation process.

전하차단막(203)은 터널절연막(201)을 통과한 전자들이 전하트랩막(202)에 트랩되는 과정에서 게이트전극(205)으로 이동하는 것을 차단하는 역할을 한다. 전하차단막(203)은 알루미늄산화막 또는 실리콘산화막을 포함할 수 있다. 여기서, 알루미늄산화막은 화학기상증착법(CVD) 또는 원자층증착법(ALD)에 의해 형성되고, 실리콘산화막은 화학기상증착법(CVD)에 형성된 것이다. 알루미늄산화막을 형성한 후에는 급속열처리(Rapid Thermal Process)가 진행될 수 있다. 급속열처리(RTP)에 의해 알루미늄산화막은 치밀화되어 막질이 향상되고, 이에 따라 전하차단막으로서의 기능이 증대될 수 있다.The charge blocking film 203 blocks electrons passing through the tunnel insulating film 201 from moving to the gate electrode 205 while being trapped by the charge trap film 202. The charge blocking film 203 may include an aluminum oxide film or a silicon oxide film. Here, the aluminum oxide film is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the silicon oxide film is formed by chemical vapor deposition (CVD). After the aluminum oxide film is formed, a rapid thermal process may be performed. By rapid heat treatment (RTP), the aluminum oxide film is densified to improve film quality, thereby increasing the function as a charge blocking film.

제2버퍼막(204B)은 후속 열공정시에 전하차단막(203)과 게이트전극(205)의 계면에서 기생산화막이 형성되는 것을 방지하는 역할을 한다. 아울러, 제2버퍼막(204B)은 화학종의 확산방지막으로 기능하여 게이트전극(205) 증착시 화학종이 확산하는 것을 방지하는 역할도 한다.The second buffer film 204B serves to prevent the pre-production film from being formed at the interface between the charge blocking film 203 and the gate electrode 205 during the subsequent thermal process. In addition, the second buffer layer 204B serves as a diffusion barrier of the chemical species to prevent the chemical species from diffusing when the gate electrode 205 is deposited.

제1버퍼막(204A)은 화학종이 전하차단막(203)을 관통하여 전하트랩막(202)으로 확산하는 것을 방지하는 역할을 한다. 이와 같이 제1버퍼막(204A)을 전하트랩막(202)과 전하차단막(203) 사이에 형성하면, 화학종의 확산을 더욱 방지할 수 있다.The first buffer film 204A serves to prevent chemical species from penetrating through the charge blocking film 203 and diffusing to the charge trap film 202. In this way, if the first buffer film 204A is formed between the charge trap film 202 and the charge blocking film 203, diffusion of chemical species can be further prevented.

제1 및 제2버퍼막(204A, 204B)은 결정립계가 없는 비정질 물질을 사용한다. 바람직하게, 제1 및 제2버퍼막(204A, 204B)은 비정질이면서도 고온 열공정시에도 상변화(Phase change)가 없는 물질을 사용한다. 즉, 제1 및 제2버퍼막(204A, 204B)은 비정질이면서도 결정화온도가 높은 물질을 포함한다. 여기서, 결정화온도가 높은 물질이란 전하차단막(203)의 결정화온도보다 높은 물질이다. 전하차단막(203)으로 사용된 물질이 알루미늄산화막인 경우, 제1 및 제2버퍼막(204A, 204B)은 알루미늄산화막보다 결정화온도가 높은 물질을 포함할 수 있다. 제1 및 제2버퍼막(204A, 204B)은 알루미늄질화막(AlN)을 포함한다. 알루미늄산화막(Al2O3)은 600℃ 이상의 고온 열공정에서 결정화가 일어나지만, 알루미늄질화막(AlN)은 600℃ 이상의 고온 열공정에 의해서도 결정화가 쉽게 일어나지 않는다. 알루미늄질화막은 적어도 800℃ 이상의 높은 결정화온도(800∼1000℃)를 갖는다. 게이트전극(205)으로 사용된 물질은 주로 500∼650℃의 범위에서 증착하기 때문에, 알루미늄질화막(AlN)은 결정화되지 않고 비정질을 유지할 수 있다.The first and second buffer films 204A and 204B use an amorphous material having no grain boundary. Preferably, the first and second buffer films 204A and 204B use an amorphous material that does not have a phase change even in a high temperature thermal process. That is, the first and second buffer films 204A and 204B include an amorphous material and a high crystallization temperature. Here, the material having a high crystallization temperature is a material higher than the crystallization temperature of the charge blocking film 203. When the material used as the charge blocking film 203 is an aluminum oxide film, the first and second buffer films 204A and 204B may include a material having a higher crystallization temperature than the aluminum oxide film. The first and second buffer films 204A and 204B include aluminum nitride film AlN. Crystallization of the aluminum oxide film (Al 2 O 3 ) occurs at a high temperature thermal process of 600 ° C. or higher, but crystallization of the aluminum nitride film (AlN) does not occur easily even at the high temperature thermal process of 600 ° C. or higher. The aluminum nitride film has a high crystallization temperature (800-1000 ° C) of at least 800 ° C. Since the material used for the gate electrode 205 is mainly deposited in the range of 500 to 650 ° C., the aluminum nitride film AlN can remain amorphous without crystallization.

또한, 알루미늄질화막은 비정질이기 때문에 결정립계가 존재하지 않고, 이에 따라 확산경로가 없으므로 화학종의 확산을 방지할 수 있다.In addition, since the aluminum nitride film is amorphous, there is no grain boundary, and accordingly, there is no diffusion path, thereby preventing the diffusion of chemical species.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

도 1은 종래기술에 따른 전하트랩형 비휘발성메모리장치를 도시한 도면이다.1 is a view showing a charge trap type nonvolatile memory device according to the prior art.

도 2는 본 발명의 제1실시예에 따른 비휘발성메모리장치의 구조를 도시한 도면.2 is a diagram showing the structure of a nonvolatile memory device according to the first embodiment of the present invention;

도 3은 본 발명의 제2실시예에 따른 비휘발성메모리장치의 구조를 도시한 도면.3 is a diagram showing the structure of a nonvolatile memory device according to a second embodiment of the present invention;

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

100 : 기판 101 : 터널절연막100 substrate 101 tunnel insulating film

102 : 전하트랩막 103 : 전하차단막102: charge trapping film 103: charge blocking film

104 : 버퍼막 105 : 게이트전극104: buffer film 105: gate electrode

Claims (17)

전하트랩막과 게이트전극 사이에 전하차단막을 구비하는 비휘발성메모리장치에 있어서,A nonvolatile memory device comprising a charge blocking film between a charge trap film and a gate electrode. 상기 전하차단막과 게이트전극 사이에 형성된 버퍼막을 포함하는 비휘발성메모리장치.And a buffer film formed between the charge blocking film and the gate electrode. 제1항에 있어서,The method of claim 1, 상기 전하트랩막과 전하차단막 사이에 형성된 버퍼막을 더 포함하는 비휘발성메모리장치.And a buffer layer formed between the charge trap layer and the charge blocking layer. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 버퍼막은 상기 전하차단막보다 결정화온도가 높은 물질인 비휘발성메모리장치.And the buffer layer is a material having a higher crystallization temperature than the charge blocking layer. 제3항에 있어서,The method of claim 3, 상기 버퍼막은 결정화온도가 적어도 800℃ 이상인 물질인 비휘발성메모리장 치.The buffer film is a non-volatile memory device of a material having a crystallization temperature of at least 800 ℃ or more. 제3항에 있어서,The method of claim 3, 상기 버퍼막은 비정질인 비휘발성메모리장치.And the buffer layer is amorphous. 제3항에 있어서,The method of claim 3, 상기 버퍼막은 알루미늄질화막(AlN)을 포함하는 비휘발성메모리장치.The buffer layer includes an aluminum nitride layer (AlN). 제3항에 있어서,The method of claim 3, 상기 전하차단막은 알루미늄산화막(Al2O3) 또는 실리콘산화막(SiO2)을 포함하는 비휘발성메모리장치.The charge blocking layer includes an aluminum oxide layer (Al 2 O 3 ) or a silicon oxide layer (SiO 2 ). 제1항에 있어서,The method of claim 1, 상기 게이트전극은 금속질화막 또는 폴리실리콘막을 포함하는 비휘발성메모리장치.The gate electrode includes a metal nitride film or a polysilicon film. 기판 상에 터널절연막을 형성하는 단계;Forming a tunnel insulating film on the substrate; 상기 터널절연막 상에 전하트랩막을 형성하는 단계;Forming a charge trap film on the tunnel insulating film; 상기 전하트랩막 상에 전하차단막을 형성하는 단계;Forming a charge blocking film on the charge trap film; 상기 전하차단막 상에 버퍼막을 형성하는 단계; 및Forming a buffer film on the charge blocking film; And 상기 버퍼막 상에 게이트전극을 형성하는 단계Forming a gate electrode on the buffer layer 를 포함하는 비휘발성메모리장치 제조 방법.Nonvolatile memory device manufacturing method comprising a. 제9항에 있어서,The method of claim 9, 상기 전하트랩막과 전하차단막 사이에 버퍼막을 더 형성하는 비휘발성메모리장치 제조 방법.And forming a buffer film between the charge trap film and the charge blocking film. 제9항 또는 제10항에 있어서,The method of claim 9 or 10, 상기 버퍼막은 상기 전하차단막보다 결정화온도가 높은 물질로 형성하는 비휘발성메모리장치 제조 방법.And the buffer film is formed of a material having a higher crystallization temperature than the charge blocking film. 제11항에 있어서,The method of claim 11, 상기 버퍼막은 결정화온도가 적어도 800℃ 이상인 물질로 형성하는 비휘발성메모리장치 제조 방법.And the buffer film is formed of a material having a crystallization temperature of at least 800 ° C or higher. 제11항에 있어서,The method of claim 11, 상기 버퍼막은 비정질 물질로 형성하는 비휘발성메모리장치 제조 방법.And the buffer layer is formed of an amorphous material. 제11항에 있어서,The method of claim 11, 상기 버퍼막은 알루미늄질화막(AlN)으로 형성하는 비휘발성메모리장치 제조 방법.And the buffer layer is formed of an aluminum nitride layer (AlN). 제11항에 있어서,The method of claim 11, 상기 전하차단막은 알루미늄산화막(Al2O3) 또는 실리콘산화막(SiO2)을 포함하는 비휘발성메모리장치 제조 방법.The charge blocking layer may include an aluminum oxide layer (Al 2 O 3 ) or a silicon oxide layer (SiO 2 ). 제9항에 있어서,The method of claim 9, 상기 게이트전극은 금속질화막 또는 폴리실리콘막을 포함하는 비휘발성메모리장치 제조 방법.The gate electrode includes a metal nitride film or a polysilicon film. 제9항에 있어서,The method of claim 9, 상기 전하차단막을 형성한 후에, 급속열처리(RTP)를 진행하는 비휘발성메모리장치 제조 방법.And a rapid thermal processing (RTP) is performed after the charge blocking film is formed.
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Publication number Priority date Publication date Assignee Title
US9812448B2 (en) 2014-12-17 2017-11-07 Samsung Electronics Co., Ltd. Semiconductor devices and methods for fabricating the same

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9812448B2 (en) 2014-12-17 2017-11-07 Samsung Electronics Co., Ltd. Semiconductor devices and methods for fabricating the same

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