KR20100001127A - Method for forming metal line of semiconductor device - Google Patents

Method for forming metal line of semiconductor device Download PDF

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KR20100001127A
KR20100001127A KR1020080060926A KR20080060926A KR20100001127A KR 20100001127 A KR20100001127 A KR 20100001127A KR 1020080060926 A KR1020080060926 A KR 1020080060926A KR 20080060926 A KR20080060926 A KR 20080060926A KR 20100001127 A KR20100001127 A KR 20100001127A
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film
titanium nitride
pattern
layer
etching process
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KR101037485B1 (en
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유미현
김세진
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

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Abstract

PURPOSE: A method for forming a metal line of a semiconductor device is provided to prevent a fail interfering with an etch profile by using a titanium nitride film instead of silicon oxynitride film. CONSTITUTION: A metal layer(116), diffusion barrier layer, a titanium nitride(126) and a reflection barrier layer are laminated on the semiconductor substrate having a lower structure. A photoresist pattern(130) is formed on the reflection barrier layer. A titanium nitride pattern is formed by etching the lamination structure of titanium nitride film and reflection barrier layer through an etching process. A hard mask film pattern is formed by etching hard mask with the titanium nitride film pattern through a second etch process.

Description

반도체 소자의 금속 배선 형성 방법{Method for Forming Metal Line of Semiconductor Device}Method for forming metal wiring of semiconductor device {Method for Forming Metal Line of Semiconductor Device}

본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 더욱 상세하게는 금속 배선 형성 공정시 폴리머 발생을 억제하여 파티클 소스(particle source)를 줄임으로써, 식각 프로파일에 영향을 주는 페일을 방지할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and more particularly, by suppressing the generation of polymer during the metal wiring forming process to reduce particle sources, it is possible to prevent a failure affecting the etching profile. A metal wiring formation method of a semiconductor element.

디램의 개발에 따른 소자의 발달에 기인하여 라인 패턴의 크기가 감소하게 되고, 이로 인해 포토레지스트 마진이 감소하여 패턴이 붕괴되며, 식각 타깃(target)의 부족으로 인해 브릿지(bridge)가 발생하게 된다.Due to the development of the device according to the development of the DRAM, the size of the line pattern is reduced, which causes the photoresist margin to decrease and the pattern is collapsed, resulting in a bridge due to the lack of an etching target. .

상기한 문제를 해결하기 위해 일반적으로 하드마스크막을 배리어로 사용하는 공정을 적용하게 되었는데, 일반적으로 비정질 탄소막을 하드마스크막으로 선택하게 되었다.In order to solve the above problems, a process using a hard mask film as a barrier is generally applied, and an amorphous carbon film is generally selected as a hard mask film.

이때, 노광 공정을 위해 실리콘산화질화막이 증착되는데, 이러한 실리콘산화질화막은 식각 공정시 사용되는 식각 용액과 화학적으로 반응하여 폴리머를 형성하게 된다. 그런데, 상기 폴리머는 하드마스크막인 비정질 탄소막을 식각한 후에 비 정질 탄소막의 측벽에 증착하여 하부의 알루미늄과 같은 금속 식각시에 배리어로 작용하게 되므로, 식각 프로파일에 영향을 준다.In this case, a silicon oxynitride layer is deposited for the exposure process, and the silicon oxynitride layer chemically reacts with an etching solution used in the etching process to form a polymer. However, since the polymer is etched after the amorphous carbon film, which is a hard mask film, is deposited on the sidewalls of the amorphous carbon film, the polymer acts as a barrier during metal etching, such as aluminum, thereby affecting the etching profile.

상기한 문제점을 갖는 종래기술에 따른 반도체 소자의 금속 배선 형성 방법을 도 1a 내지 도 1d를 통해 살펴보면 다음과 같다.Looking at the metal wiring formation method of the semiconductor device according to the prior art having the above problem as follows through Figures 1a to 1d.

도 1a를 참조하면, 소정의 하부 구조를 구비하는 반도체 기판(미도시) 상에 3000Å 내지 4000Å 두께의 절연막(10), 90Å 내지 110Å 두께의 티타늄막(12), 190Å 내지 210Å 두께의 티타늄나이트라이드막(14), 3900Å 내지 4100Å 두께의 알루미늄 재질의 금속막(16), 90Å 내지 110Å 두께의 티타늄막(18), 190Å 내지 210Å 두께의 티타늄나이트라이드막(20), 290Å 내지 310Å 두께의 실리콘산화질화막(22), 2850Å 내지 3150Å 두께의 비정질 탄소 재질의 하드마스크막(24), 390Å 내지 410Å 두께의 실리콘산화질화막(26) 및 290Å 내지 310Å 두께의 반사방지막(28)의 적층 구조를 형성한다.Referring to FIG. 1A, an insulating film 10 having a thickness of 3000 Å to 4000 티타늄, a titanium film 12 having a thickness of 90 Å to 110 ,, a titanium nitride having a thickness of 190 Å to 210 Å on a semiconductor substrate (not shown) having a predetermined substructure is illustrated. Film 14, a metal film 16 made of aluminum having a thickness of 3900 kPa to 4100 kPa, a titanium film 18 having a thickness of 90 kPa to 110 kPa, a titanium nitride film 20 having a thickness of 190 kPa to 210 kPa, a silicon oxide having a thickness of 290 kPa to 310 kPa A laminated structure of a nitride film 22, a hard mask film 24 made of amorphous carbon material having a thickness of 2850 kPa to 3150 kPa, a silicon oxynitride film 26 having a thickness of 390 kPa to 410 kPa, and an antireflection film 28 having a thickness of 290 kPa to 310 kPa is formed.

상기 금속막(16) 하부의 티타늄막(12)/티타늄나이트라이드막(14) 및 금속막(16) 상부의 티타늄막(18)/티타늄나이트라이드막(20)은 확산방지막으로서의 역할을 한다.The titanium film 12 / titanium nitride film 14 under the metal film 16 and the titanium film 18 / titanium nitride film 20 on the metal film 16 serve as diffusion barrier films.

다음, 반사방지막(28) 상에 포토레지스트 조성물을 도포하여 포토레지스트막(미도시)을 형성한 다음, 노광 및 현상 공정을 수행하여 포토레지스트 패턴(30)을 형성한다.Next, a photoresist composition is coated on the antireflection film 28 to form a photoresist film (not shown), and then a photoresist pattern 30 is formed by performing an exposure and development process.

도 1b를 참조하면, 포토레지스트 패턴(30)을 마스크로 실리콘산화질화막(26) 및 반사방지막(28)의 적층 구조에 제1식각 공정을 수행하여 실리콘산화질화막 패 턴(미도시)을 형성한다.Referring to FIG. 1B, a silicon oxynitride layer pattern (not shown) is formed by performing a first etching process on the stacked structure of the silicon oxynitride layer 26 and the anti-reflection layer 28 using the photoresist pattern 30 as a mask. .

다음, 상기 실리콘산화질화막 패턴을 마스크로 하여 산소 가스 및 질소 가스를 식각 가스로 이용하여 하드마스크막(24)에 제2식각 공정을 수행함으로써, 하드마스크막 패턴(24a)을 형성하는데, 이때 하드마스크막 패턴(24a)의 측벽에는 실리콘 계열의 폴리머층(40)이 형성된다.Next, a second etching process is performed on the hard mask layer 24 using the oxygen oxynitride layer pattern as a mask and oxygen gas and nitrogen gas as an etching gas, thereby forming the hard mask layer pattern 24a. A silicon-based polymer layer 40 is formed on the sidewall of the mask film pattern 24a.

상기 실리콘 계열의 폴리머층(40)은 상기 실리콘산화질화막 패턴이 식각 용액과 화학적으로 반응함으로 인해 발생하는 것이다.The silicon-based polymer layer 40 is generated by chemically reacting the silicon oxynitride layer pattern with an etching solution.

도 1c를 참조하면, 하드마스크막 패턴(24a)은 손실시키지 않으면서 하드마스크막 패턴(24a) 측벽의 실리콘 계열의 폴리머층(40)만을 선택적으로 제거하기 위해 BOE (buffered oxide etcher, HF + H20) 용액을 이용한 세정 공정을 수행한다.Referring to FIG. 1C, a buffered oxide etcher (BOE) HF + H may be used to selectively remove only the silicon-based polymer layer 40 on the sidewall of the hard mask layer pattern 24a without losing the hard mask layer pattern 24a. 20 ) A cleaning process using a solution is performed.

그러나, 상기 세정 공정 후에도 폴리머는 실리콘산화질화막(22)의 가장 자리에 부분적으로 남아 있게 된다.However, even after the cleaning process, the polymer remains partially at the edge of the silicon oxynitride film 22.

도 1d를 참조하면, 하드마스크막 패턴(24)을 마스크로 실리콘산화질화막(22), 티타늄나이트라이드막(20), 티타늄막(18) 및 금속막(16)에 제3식각 공정을 수행하여 실리콘산화질화막 패턴(22a), 티타늄나이트라이드막 패턴(20a), 티타늄막 패턴(18a) 및 금속막 패턴(16a)을 형성한다.Referring to FIG. 1D, a third etching process is performed on the silicon oxynitride layer 22, the titanium nitride layer 20, the titanium layer 18, and the metal layer 16 using the hard mask layer pattern 24 as a mask. The silicon oxynitride film pattern 22a, the titanium nitride film pattern 20a, the titanium film pattern 18a and the metal film pattern 16a are formed.

상기 제3식각 공정 및 상기 제2식각 공정은 엑스-시튜(ex-situ)로 수행해야 하는데, 그 이유는 제2식각 공정을 수행한 후 실리콘 계열의 폴리머층(40)을 제거하기 위해 BOE 용액을 이용한 세정 공정을 수행하므로, 인-시튜(in-situ)로 수행하 는 것이 불가능하다.The third etching process and the second etching process should be performed by ex-situ, because the BOE solution to remove the silicon-based polymer layer 40 after performing the second etching process Since the cleaning process using the, it is impossible to perform in-situ (in-situ).

그런 다음, 금속막 패턴(16a)을 마스크로 티타늄나이트라이드막(14) 및 티타늄막(12)에 제4식각 공정을 수행하여 티타늄나이트라이드막 패턴(14a) 및 티타늄막 패턴(12a)을 형성한다.Then, a fourth etching process is performed on the titanium nitride film 14 and the titanium film 12 using the metal film pattern 16a as a mask to form the titanium nitride film pattern 14a and the titanium film pattern 12a. do.

상기한 바와 같이, 종래기술에 따른 반도체 소자의 금속 배선 형성 방법에 따르면, 실리콘산화질화막이 식각 용액과 화학적으로 반응하여 형성된 폴리머층이 세정 공정에 의해 전부 제거되지 않고 남아 후속 공정에서 파티클 소스로서 작용하기 때문에 수율 손실의 주원인이 된다.As described above, according to the method for forming metal wirings of the semiconductor device according to the prior art, the polymer layer formed by the silicon oxynitride film chemically reacting with the etching solution is not completely removed by the cleaning process and remains as a particle source in a subsequent process. This is the main cause of yield loss.

또한, 상기 제3식각 공정 및 상기 제2식각 공정을 엑스-시튜(ex-situ)로 수행해야 하므로, 공정 시간의 증가로 인해 디램 원가 상승의 주원인이 된다.In addition, since the third etching process and the second etching process must be performed ex-situ, the increase of the process time is a main cause of the increase in DRAM cost.

또한, 티타늄나이트라이드막(20)의 결정 입계(grain-boundary) 사이의 실리콘산화질화막(22)의 식각 타겟 부족으로 인해 금속막(16)의 브릿지가 유발되었다.In addition, the bridge of the metal film 16 is induced due to the lack of an etching target of the silicon oxynitride film 22 between grain-boundary of the titanium nitride film 20.

본 발명은 금속 배선 형성 공정시 폴리머 발생을 억제하여 파티클 소스를 줄이기 위해, 폴리머의 주원인이라 할 수 있는 실리콘산화질화막 대신에 티타늄나이트라이드막을 사용함으로써, 식각 프로파일에 영향을 주는 페일을 방지할 수 있는 방법을 제공하는 것을 목적으로 한다.According to the present invention, a titanium nitride film is used instead of a silicon oxynitride film, which is the main cause of the polymer, in order to reduce the generation of particles by suppressing the polymer generation during the metal wiring formation process, thereby preventing a fail affecting the etching profile. It is an object to provide a method.

상기 목적을 달성하기 위한 본 발명의 반도체 소자 금속 배선 형성 방법은The semiconductor device metal wiring forming method of the present invention for achieving the above object

소정의 하부 구조를 구비하는 반도체 기판 상에 금속막, 확산방지막, 산화막, 하드마스크막, 티타늄나이트라이드막 및 반사방지막의 적층 구조를 형성하는 단계;Forming a stacked structure of a metal film, a diffusion barrier film, an oxide film, a hard mask film, a titanium nitride film and an antireflection film on a semiconductor substrate having a predetermined substructure;

상기 반사방지막 상에 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern on the anti-reflection film;

상기 포토레지스트 패턴을 마스크로 상기 티타늄나이트라이드막 및 반사방지막의 적층 구조에 제1식각 공정을 수행하여 티타늄나이트라이드막 패턴을 형성하는 단계;Forming a titanium nitride film pattern by performing a first etching process on the laminated structure of the titanium nitride film and the anti-reflection film using the photoresist pattern as a mask;

상기 티타늄나이트라이드막 패턴을 마스크로 상기 하드마스크막에 제2식각 공정을 수행하여 하드마스크막 패턴을 형성하는 단계; 및Forming a hard mask layer pattern by performing a second etching process on the hard mask layer using the titanium nitride layer pattern as a mask; And

상기 하드마스크막 패턴을 마스크로 금속막, 확산방지막 및 산화막의 적층 구조에 제3식각 공정을 수행하여 금속 배선 패턴을 형성하는 단계. Forming a metal wiring pattern by performing a third etching process on the stacked structure of the metal layer, the diffusion barrier layer, and the oxide layer using the hard mask layer pattern as a mask.

상기 티타늄나이트라이드막은 580Å 내지 620Å의 두께로 형성된다.The titanium nitride film is formed to a thickness of 580 kPa to 620 kPa.

상기 산화막은 테트라에틸옥시실리케이트(TEOS) 산화막이 400Å 내지 800Å의 두께로 형성된다.The oxide film is a tetraethyloxysilicate (TEOS) oxide film having a thickness of 400 kPa to 800 kPa.

상기 금속막은 알루미늄막으로, 상기 하드마스크막은 비정질 탄소층으로 형성된다.The metal film is an aluminum film, and the hard mask film is formed of an amorphous carbon layer.

상기 확산방지막은 티타늄막 및 티타늄나이트라이드막을 차례로 적층하여 형성한다.The diffusion barrier layer is formed by sequentially stacking a titanium film and a titanium nitride film.

상기 제1식각 공정은 산소 가스, 염소 가스, 사불화탄소 가스, 수소불화탄소 및 이들의 조합으로 이루어진 군으로부터 선택된 하나의 식각 가스를 이용한다.The first etching process uses one etching gas selected from the group consisting of oxygen gas, chlorine gas, carbon tetrafluoride gas, hydrogen fluorocarbon, and a combination thereof.

상기 제2식각 공정은 질소 가스, 산소 가스 및 이들의 조합으로 이루어진 군으로부터 선택된 하나의 식각 가스를 이용한다.The second etching process uses one etching gas selected from the group consisting of nitrogen gas, oxygen gas, and combinations thereof.

상기 제3식각 공정은 상기 제2식각 공정에서 사용된 것과 동일한 장비를 사용하여 동일 챔버 내에서 인-시튜(in-situ)로 수행된다.The third etching process is performed in-situ in the same chamber using the same equipment as used in the second etching process.

상기 티타늄나이트라이드막 패턴을 형성하는 단계 이후, 동일 장비내 다른 챔버에서 메탄 가스 및 질소 가스를 첨가하고 포토레지스트 패턴을 스트립하는 단계를 더 포함한다.After the forming of the titanium nitride film pattern, the method may further include adding methane gas and nitrogen gas in another chamber in the same equipment and stripping the photoresist pattern.

본 발명에서는 하드마스크막 상부의 실리콘산화질화막 대신에 티타늄 나이트라이드막을 사용함으로써, 폴리머 제거를 위한 세정 공정을 수행할 필요가 없어, 제2식각 공정 및 제3식각 공정을 인-시튜(in-situ)로 수행할 수 있으므로 공정 시간이 감소될 뿐만 아니라, 폴리머가 존재하지 않으므로 수율 증가 효과도 볼 수 있 다.In the present invention, since the titanium nitride film is used instead of the silicon oxynitride film on the hard mask film, it is not necessary to perform the cleaning process for removing the polymer, and thus the second and third etching processes are in-situ. In addition, the process time is reduced, and since the polymer is not present, the yield increase effect can be seen.

또한, 본 발명에서는 티타늄나이트라이드막 상부에 실리콘산화질화막 대신 TEOS 산화막을 형성하는 것이므로, 티타늄나이트라이드막(120)의 결정 입계(grain-boundary) 사이로의 증착이 용이하고, 티타늄나이트라이드막과 TEOS 산화막간의 식각 선택비가 크다. 따라서, 티타늄나이트라이드막(120)의 결정 입계 사이의 TEOS 산화막의 식각 타겟을 충분하게 가할 수 있는 이점이 있어, 식각 타겟의 부족으로 인해 발생하는 브릿지를 미연에 방지할 수 있다.In addition, in the present invention, since the TEOS oxide film is formed on the titanium nitride film instead of the silicon oxynitride film, the titanium nitride film 120 is easily deposited between grain-boundaries, and the titanium nitride film and the TEOS are easily deposited. The etching selectivity between the oxide films is large. Therefore, there is an advantage that the etching target of the TEOS oxide film between the grain boundaries of the titanium nitride film 120 can be sufficiently applied, thereby preventing the bridge generated due to the lack of the etching target.

이하, 첨부된 도면을 참고로 하여 본 발명의 바람직한 실시예를 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 도시하는 공정 단면도이다.2A to 2D are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

도 2a를 참조하면, 소정의 하부 구조를 구비하는 반도체 기판(미도시) 상에 3000Å 내지 4000Å 두께의 절연막(110), 90Å 내지 110Å 두께의 티타늄막(112), 190Å 내지 210Å 두께의 티타늄나이트라이드막(114), 3900Å 내지 4100Å 두께의 금속막(116), 90Å 내지 110Å 두께의 티타늄막(118), 190Å 내지 210Å 두께의 티타늄나이트라이드막(120), 400Å 내지 800Å 두께의 산화막(122), 2850Å 내지 3150Å 두께의 하드마스크막(124), 580Å 내지 620Å 두께의 티타늄나이트라이드막(126) 및 290Å 내지 310Å 두께의 반사방지막(128)의 적층 구조를 형성한다.Referring to FIG. 2A, an insulating film 110 having a thickness of 3000 Å to 4000 티타늄, a titanium film 112 having a thickness of 90 Å to 110 ,, a titanium nitride having a thickness of 190 Å to 210 상 에 on a semiconductor substrate (not shown) having a predetermined substructure is illustrated. Film 114, a metal film 116 having a thickness of 3900 kPa to 4100 kPa, a titanium film 118 having a thickness of 90 kPa to 110 kPa, a titanium nitride film 120 having a thickness of 190 kPa to 210 kPa, an oxide film 122 having a thickness of 400 kPa to 800 kPa, A stacked structure of a hard mask film 124 having a thickness of 2850 kPa to 3150 kPa, a titanium nitride film 126 having a thickness of 580 kPa to 620 kPa, and an antireflection film 128 having a thickness of 290 kPa to 310 kPa is formed.

바람직하게는 상기 반도체 기판 상에 3500Å 두께의 절연막(110), 100Å 두 께의 티타늄막(112), 200Å 두께의 티타늄나이트라이드막(114), 4000Å 두께의 금속막(116), 100Å 두께의 티타늄막(118), 200Å 두께의 티타늄나이트라이드막(120), 600Å 두께의 산화막(122), 3000Å 두께의 하드마스크막(124), 600Å 두께의 티타늄나이트라이드막(126) 및 300Å 두께의 반사방지막(128)의 적층 구조를 형성한다.Preferably, the insulating film 110 having a thickness of 3500 Å, the titanium film 112 having a thickness of 100 ,, the titanium nitride film 114 having a thickness of 200 ,, the metal film 116 having a thickness of 4,000 ,, the titanium film having a thickness of 100 상 에 are formed on the semiconductor substrate. (118), 200 ns thick titanium nitride film 120, 600 ns thick oxide film 122, 3000 ns hard mask 124, 600 ns thick titanium nitride film 126, and 300 ns thick antireflection film ( 128) to form a laminated structure.

산화막(122)은 테트라에틸옥시실리케이트(TEOS) 산화막이고, 금속막(116)은 알루미늄막이며, 하드마스크막(124)은 비정질 탄소층인 것이 바람직하다.The oxide film 122 is a tetraethyloxysilicate (TEOS) oxide film, the metal film 116 is an aluminum film, and the hard mask film 124 is an amorphous carbon layer.

또한, 금속막(116) 하부의 티타늄막(112)/티타늄나이트라이드막(114) 및 금속막(116) 상부의 티타늄막(118)/티타늄나이트라이드막(120)은 확산방지막으로서의 역할을 한다.In addition, the titanium film 112 / titanium nitride film 114 under the metal film 116 and the titanium film 118 / titanium nitride film 120 on the metal film 116 serve as diffusion barrier films. .

다음, 반사방지막(128) 상에 포토레지스트 조성물을 도포하여 포토레지스트막(미도시)을 형성한 다음, 노광 및 현상 공정을 수행하여 포토레지스트 패턴(130)을 형성한다.Next, the photoresist composition is coated on the anti-reflection film 128 to form a photoresist film (not shown), and then a photoresist pattern 130 is formed by performing an exposure and development process.

도 2b를 참조하면, 포토레지스트 패턴(130)을 마스크로 티타늄나이트라이드막(126) 및 반사방지막(128)의 적층 구조에 제1식각 공정을 수행하여 티타늄나이트라이드막 패턴(미도시)을 형성한다.Referring to FIG. 2B, a titanium nitride layer pattern (not shown) is formed by performing a first etching process on a stacked structure of the titanium nitride layer 126 and the antireflection layer 128 using the photoresist pattern 130 as a mask. do.

상기 제1식각 공정은 산소 가스, 염소 가스, 사불화탄소 가스, 수소불화탄소 및 이들의 조합으로 이루어진 군으로부터 선택된 하나의 식각 가스를 이용하는 수행하는 것이 바람직히다.The first etching process is preferably performed using one etching gas selected from the group consisting of oxygen gas, chlorine gas, carbon tetrafluoride gas, hydrogen fluorocarbon, and combinations thereof.

또한, 상기 티타늄나이트라이드막 패턴을 형성하는 단계 이후, 마스크로 사 용된 포토레지스트 패턴(130)을 제거하기 위해, 동일 장비내 다른 챔버에서 메탄 가스 및 질소 가스를 첨가하고 포토레지스트 패턴(130)을 스트립하는 단계를 더 수행함으로써, 금속막(116), 특히 알루미늄막의 노칭을 보완하도록 할 수 있다.In addition, after the forming of the titanium nitride film pattern, in order to remove the photoresist pattern 130 used as a mask, methane gas and nitrogen gas are added in another chamber in the same equipment and the photoresist pattern 130 is removed. By performing the step of stripping further, it is possible to compensate for the notching of the metal film 116, especially the aluminum film.

다음, 상기 티타늄나이트라이드막 패턴을 마스크로 하드마스크막(124)에 제2식각 공정을 수행하여 하드마스크막 패턴(미도시)을 형성한다.Next, a hard mask layer pattern (not shown) is formed by performing a second etching process on the hard mask layer 124 using the titanium nitride layer pattern as a mask.

상기 제2식각 공정은 질소 가스, 산소 가스 및 이들의 조합으로 이루어진 군으로부터 선택된 하나의 식각 가스를 이용하여 수행하는 것이 바람직하다.The second etching process is preferably performed using one etching gas selected from the group consisting of nitrogen gas, oxygen gas and combinations thereof.

도 2c를 참조하면, 하드마스크막 패턴(124)을 마스크로 산화막(122), 티타늄나이트라이드막(120), 티타늄막(118) 및 금속막(116)에 제3식각 공정을 수행하여 산화막 패턴(122a), 티타늄나이트라이드막 패턴(120a), 티타늄막 패턴(118a) 및 금속막 패턴(116a)을 형성한다.Referring to FIG. 2C, an oxide layer pattern is formed by performing a third etching process on the oxide layer 122, the titanium nitride layer 120, the titanium layer 118, and the metal layer 116 using the hard mask layer pattern 124 as a mask. 122a, titanium nitride film pattern 120a, titanium film pattern 118a, and metal film pattern 116a are formed.

상기 제3식각 공정은 상기 제2식각 공정에서 사용된 것과 동일한 장비를 사용하여 동일 챔버내에서 인-시튜(in-situ)로 수행하는 것이 바람직하다.The third etching process is preferably performed in-situ in the same chamber using the same equipment as used in the second etching process.

다음, 금속막 패턴(116a)을 마스크로 티타늄나이트라이드막(114) 및 티타늄막(112)에 제4식각 공정을 수행하여 티타늄나이트라이드막 패턴(114a) 및 티타늄막 패턴(112a)을 형성한다.Next, a fourth etching process is performed on the titanium nitride film 114 and the titanium film 112 using the metal film pattern 116a as a mask to form the titanium nitride film pattern 114a and the titanium film pattern 112a. .

상기 제4식각 공정은 과도 식각(over etch) 공정을 수행하는데, 이는 티타늄나이트라이드막(114) 및 티타늄막(112)을 완전하게 제거함으로써 금속막 패턴(116a)의 페일의 주원인인 브릿지를 방지하기 위함이다. The fourth etching process performs an overetch process, which completely removes the titanium nitride film 114 and the titanium film 112 to prevent the bridge which is the main cause of the failing of the metal film pattern 116a. To do this.

상기한 바와 같이, 본 발명에서는 폴리머 발생의 주원이이라 할 수 있는 실 리콘산화질화막 대신에 티타늄 나이트라이드막(126)을 사용함으로써, 폴리머 제거를 위한 세정 공정을 수행할 필요가 없어, 제2식각 공정 및 제3식각 공정을 인-시튜(in-situ)로 수행할 수 있으므로 공정 시간이 감소될 뿐만 아니라, 폴리머가 존재하지 않으므로 수율 증가 효과도 볼 수 있다.As described above, in the present invention, since the titanium nitride film 126 is used instead of the silicon oxynitride film, which is a main source of polymer generation, it is not necessary to perform the cleaning process for removing the polymer, thereby performing the second etching. Since the process and the third etching process can be performed in-situ, not only the process time is reduced, but also the increase in yield can be seen because the polymer is not present.

또한, 본 발명에서는 티타늄나이트라이드막(120) 상부에 실리콘산화질화막 대신 TEOS 산화막(122)을 형성하는 것이므로, 티타늄나이트라이드막(120)의 결정 입계(grain-boundary) 사이로의 증착이 용이하고, 티타늄나이트라이드막(120)과 TEOS 산화막(122) 간의 식각 선택비가 크다. 따라서, 티타늄나이트라이드막(120)의 결정 입계 사이의 TEOS 산화막(122)의 식각 타겟을 충분하게 가할 수 있는 이점이 있어, 식각 타겟의 부족으로 인해 발생하는 브릿지를 미연에 방지할 수 있다.Further, in the present invention, since the TEOS oxide film 122 is formed on the titanium nitride film 120 instead of the silicon oxynitride film, the titanium nitride film 120 is easily deposited between grain-boundary grains. The etching selectivity between the titanium nitride film 120 and the TEOS oxide film 122 is large. Therefore, there is an advantage that the etching target of the TEOS oxide film 122 between the grain boundaries of the titanium nitride film 120 can be sufficiently applied, thereby preventing the bridge generated due to the lack of the etching target.

한편, 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 및 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.On the other hand, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be possible to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are as follows It should be regarded as belonging to the claims.

도 1a 내지 도 1d는 종래기술에 따른 반도체 소자의 금속 배선 형성 방법을 도시하는 공정 단면도.1A to 1D are cross-sectional views showing a method for forming a metal wiring of a semiconductor device according to the prior art.

도 2a 내지 도 2c는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 도시하는 공정 단면도.2A to 2C are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

< 도면의 주요 부분에 대한 간단한 설명 ><Brief description of the main parts of the drawing>

10, 110: 절연막 12, 18, 112, 118, 126: 티타늄막10, 110: insulating film 12, 18, 112, 118, 126: titanium film

12a, 18a, 112a, 118a, 126a: 티타늄막 패턴12a, 18a, 112a, 118a, 126a: titanium film pattern

14, 20, 114, 120: 티타늄나이트라이드막14, 20, 114, and 120: titanium nitride film

14a, 20a, 114a, 120a: 티타늄나이트라이드막 패턴14a, 20a, 114a, and 120a: titanium nitride film pattern

16, 116: 금속막 16a, 116a: 금속 배선 패턴16, 116: metal film 16a, 116a: metal wiring pattern

22, 26: 실리콘산화질화막 22a, 26a: 실리콘산화질화막22, 26: silicon oxynitride film 22a, 26a: silicon oxynitride film

24, 124: 하드마스크막 24a, 124a: 하드마스크막 패턴24, 124: hard mask film 24a, 124a: hard mask film pattern

28, 128: 반사방지막 28a, 128a: 반사방지막 패턴28, 128: antireflection film 28a, 128a: antireflection film pattern

30, 130: 포토레지스트 패턴 122: 산화막30, 130 photoresist pattern 122: oxide film

122a: 산화막 패턴 40 : 실리콘 계열의 폴리머층122a: oxide film pattern 40: silicon-based polymer layer

Claims (11)

소정의 하부 구조를 구비하는 반도체 기판 상에 금속막, 확산방지막, 산화막, 하드마스크막, 티타늄나이트라이드막 및 반사방지막의 적층 구조를 형성하는 단계;Forming a stacked structure of a metal film, a diffusion barrier film, an oxide film, a hard mask film, a titanium nitride film and an antireflection film on a semiconductor substrate having a predetermined substructure; 상기 반사방지막 상에 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern on the anti-reflection film; 상기 포토레지스트 패턴을 마스크로 상기 티타늄나이트라이드막 및 반사방지막의 적층 구조에 제1식각 공정을 수행하여 티타늄나이트라이드막 패턴을 형성하는 단계;Forming a titanium nitride film pattern by performing a first etching process on the laminated structure of the titanium nitride film and the anti-reflection film using the photoresist pattern as a mask; 상기 티타늄나이트라이드막 패턴을 마스크로 상기 하드마스크막에 제2식각 공정을 수행하여 하드마스크막 패턴을 형성하는 단계;Forming a hard mask layer pattern by performing a second etching process on the hard mask layer using the titanium nitride layer pattern as a mask; 상기 하드마스크막 패턴을 마스크로 상기 금속막, 상기 확산방지막 및 상기 산화막의 적층 구조에 제3식각 공정을 수행하여 금속막 패턴을 형성하는 단계를 포함하는 반도체 소자의 금속 배선 형성 방법.And forming a metal layer pattern by performing a third etching process on the stacked structure of the metal layer, the diffusion barrier layer, and the oxide layer using the hard mask layer pattern as a mask. 청구항 1에 있어서,The method according to claim 1, 상기 티타늄나이트라이드막은 580Å 내지 620Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The titanium nitride film is a metal wiring forming method of the semiconductor element, characterized in that formed in a thickness of 580Å to 620Å. 청구항 1에 있어서,The method according to claim 1, 상기 산화막은 400Å 내지 800Å의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The oxide film is a metal wiring forming method of a semiconductor device, characterized in that formed in a thickness of 400 ~ 800Å. 청구항 1에 있어서,The method according to claim 1, 상기 산화막은 테트라에틸옥시실리케이트(TEOS) 산화막인 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And said oxide film is a tetraethyloxysilicate (TEOS) oxide film. 청구항 1에 있어서,The method according to claim 1, 상기 금속막은 알루미늄막으로 형성되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the metal film is formed of an aluminum film. 청구항 1에 있어서The method according to claim 1 상기 확산방지막은 티타늄막 및 티타늄나이트라이드막을 차례로 적층하여 형성하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.The diffusion barrier layer is a metal wiring formation method of a semiconductor device, characterized in that formed by sequentially stacking a titanium film and titanium nitride film. 청구항 1에 있어서,The method according to claim 1, 상기 하드마스크막은 비정질 탄소층으로 형성되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the hard mask layer is formed of an amorphous carbon layer. 청구항 1에 있어서,The method according to claim 1, 상기 제1식각 공정은 산소 가스, 염소 가스, 사불화탄소 가스, 수소불화탄소 및 이들의 조합으로 이루어진 군으로부터 선택된 하나의 식각 가스를 이용하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the first etching process uses one etching gas selected from the group consisting of oxygen gas, chlorine gas, carbon tetrafluoride gas, hydrogen fluorocarbon, and combinations thereof. 청구항 1에 있어서,The method according to claim 1, 상기 제2식각 공정은 질소 가스, 산소 가스 및 이들의 조합으로 이루어진 군으로부터 선택된 하나의 식각 가스를 이용하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the second etching process uses one etching gas selected from the group consisting of nitrogen gas, oxygen gas, and combinations thereof. 청구항 1에 있어서,The method according to claim 1, 상기 제3식각 공정은 상기 제2식각 공정에서 사용된 것과 동일한 장비를 사용하여 동일 챔버내에서 인-시튜(in-situ)로 수행되는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.And the third etching process is performed in-situ in the same chamber using the same equipment as used in the second etching process. 청구항 1에 있어서,The method according to claim 1, 상기 티타늄나이트라이드막 패턴을 형성하는 단계 이후, 동일 장비내 다른 챔버에서 메탄 가스 및 질소 가스를 첨가하고 포토레지스트 패턴을 스트립하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 금속 배선 형성 방법.After the forming of the titanium nitride film pattern, further comprising the step of adding methane gas and nitrogen gas in another chamber in the same equipment and stripping the photoresist pattern.
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KR20120050827A (en) * 2010-11-11 2012-05-21 에스케이하이닉스 주식회사 Manufacturing method of metal line of semiconductor device
KR20120138474A (en) * 2011-06-15 2012-12-26 삼성전자주식회사 Method for fabricating of semiconductor device

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KR100704470B1 (en) * 2004-07-29 2007-04-10 주식회사 하이닉스반도체 Method for fabrication of semiconductor device using amorphous carbon layer to sacrificial hard mask

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KR20120050827A (en) * 2010-11-11 2012-05-21 에스케이하이닉스 주식회사 Manufacturing method of metal line of semiconductor device
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