KR20090124574A - Method manufactruing of flash memory device - Google Patents

Method manufactruing of flash memory device Download PDF

Info

Publication number
KR20090124574A
KR20090124574A KR1020080050862A KR20080050862A KR20090124574A KR 20090124574 A KR20090124574 A KR 20090124574A KR 1020080050862 A KR1020080050862 A KR 1020080050862A KR 20080050862 A KR20080050862 A KR 20080050862A KR 20090124574 A KR20090124574 A KR 20090124574A
Authority
KR
South Korea
Prior art keywords
oxide film
flash memory
line pattern
memory device
nitride
Prior art date
Application number
KR1020080050862A
Other languages
Korean (ko)
Inventor
선종원
Original Assignee
주식회사 동부하이텍
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 동부하이텍 filed Critical 주식회사 동부하이텍
Priority to KR1020080050862A priority Critical patent/KR20090124574A/en
Publication of KR20090124574A publication Critical patent/KR20090124574A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

Abstract

PURPOSE: A method manufacturing of flash memory device is provided to form the spacer using the nitride oxide film and to reduce data loss in the device formation. CONSTITUTION: The tunnel oxide film(110), the floating gate(120), and the oxide-nitride-oxide film(140) and control gate(160) are formed successively on the semiconductor substrate(100) and the line pattern is formed. The gate oxidation process is processed to form the line pattern and the sidewall oxide layer. The nitride oxide film(200) is formed on the semiconductor substrate including the sidewall oxide layer through the anneal process. The spacer is formed in the side wall of the line pattern including the nitride oxide film. The nitride oxide film is formed through the anneal process of using the NO gas. The gate oxidation process is performed in 800~900°C.

Description

플래시 메모리 소자의 제조방법{Method Manufactruing of Flash Memory Device} Manufacturing method of flash memory device {Method Manufactruing of Flash Memory Device}

본 발명은 플래시 메모리 소자의 제조방법에 관한 것으로, 특히 데이터 로스(Date Loss)를 감소시킬 수 있는 플래시 메모리 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device capable of reducing data loss.

플래시 메모리 소자는 정보를 쓰기, 소거 및 읽기를 할 수 있는 일종의 PROM(Programable ROM)이다. Flash memory devices are a type of programmable ROM (PROM) capable of writing, erasing, and reading information.

플래시 메모리 소자는 셀 어레이 체계에 따라, 비트 라인과 접지 사이에 셀이 병렬로 배치된 NOR형 구조와, 직렬로 배치된 NAND형 구조로 나눌 수 있다. Flash memory devices may be divided into NOR-type structures in which cells are disposed in parallel between bit lines and ground, and NAND-type structures arranged in series, according to a cell array scheme.

NOR형 플래시 메모리 소자는 읽기 동작을 수행할 때 고속 랜덤 액세스가 가능하므로 보통 휴대폰 부팅용으로 널리 사용되고 있다. NAND형 플래시 메모리 소자는 읽기 속도는 느리지만 쓰기 속도가 빨라 보통 데이터 저장용에 적합하고 또한 소형화에 유리하다는 장점을 가지고 있다.NOR flash memory devices are commonly used for booting mobile phones because they allow high-speed random access when performing read operations. NAND-type flash memory devices have a slow read speed but a fast write speed, and are suitable for data storage and small size.

또한, 플래시 메모리 소자는 단위 셀의 구조에 따라, 스택 게이트형과 스플릿트 게이트형으로 나뉠 수 있으며, 전하 저장층의 형태에 따라 플로팅 게이트 소자 및 SONOS(Silicon-Oxide-Nitride-Oxide-Silicon) 소자로 구분될 수 있다. 이 중 에서 플로팅 게이트 소자는 통상 그 주위가 절연체로 둘러 싸여진 다결정 실리콘으로 형성된 플로팅 게이트를 포함하고, 이 플로팅 게이트에 채널 핫 캐리어 주입(Channel Hot Carrier Injection) 또는 F-N 터널링(Fowler-Nordheim Tunneling)에 의해 전하가 주입 또는 방출됨으로써 데이터의 저장 및 소거가 이루어진다.In addition, the flash memory device may be classified into a stack gate type and a split gate type according to the unit cell structure, and a floating gate device and a silicon-oxide-nitride-oxide-silicon (SONOS) device according to the shape of the charge storage layer. It can be divided into. Among them, the floating gate device usually includes a floating gate formed of polycrystalline silicon surrounded by an insulator, and is connected to the floating gate by channel hot carrier injection or FN tunneling (Fowler-Nordheim Tunneling). The charge is injected or released to store and erase the data.

도 1a 내지 1c는 종래의 플래시 메모리 소자의 제조공정을 나타낸 단면도이다. 1A to 1C are cross-sectional views illustrating a manufacturing process of a conventional flash memory device.

먼저, 도 1a에 도시된 바와 같이, 반도체 기판(10)에 소정의 거리만큼 이격된 복수의 소자분리막(미도시)을 형성한다. 이 소자분리막들은 활성 소자 영역을 정의하며, 비트 라인 방향으로 서로 나란하게 형성된다. 그리고, 활성 소자 영역의 기판 내부에 웰(Well)을 형성한다. 예를 들어, P형 기판인 경우, 깊은 N웰을 형성한 다음, 포켓 P 웰을 형성한다. 그 후 임플란트 공정을 통해 셀 문턱 전압을 결정한다. 이후, 반도체 기판(10)의 활성 소자 영역에 터널산화막(12) 및 플로팅게이트(14)를 형성한다. 이어서, 반도체 기판(10)의 전면에 ONO(oxide/nitride/oxide)막(16) 및 콘트롤게이트(18)를 차례로 형성한다. First, as shown in FIG. 1A, a plurality of device isolation layers (not shown) spaced apart by a predetermined distance from the semiconductor substrate 10 are formed. The device isolation layers define an active device region and are formed in parallel with each other in the bit line direction. Then, a Well is formed in the substrate of the active element region. For example, in the case of a P-type substrate, deep N wells are formed, followed by pocket P wells. The cell threshold voltage is then determined through an implant process. Thereafter, the tunnel oxide film 12 and the floating gate 14 are formed in the active device region of the semiconductor substrate 10. Subsequently, the ONO (oxide / nitride / oxide) film 16 and the control gate 18 are sequentially formed on the entire surface of the semiconductor substrate 10.

그리고 나서, 도 1b에 도시된 바와 같이, 반도체 기판(10) 위에 형성된 터널산화막(12), 플로팅게이트(14), ONO(oxide/nitride/oxide)막(16) 및 콘트롤게이트(18)의 일부를 소자 분리막에 수직한 방향으로 소정의 폭만큼 제거한다. 이 패터닝 공정을 거치면, 터널산화막(12), 플로팅게이트(14), ONO(oxide/nitride/oxide)막(16) 및 콘트롤게이트(18)가 적층된 복수의 스택이 형성되는데, 이하에서는 이 스택들을 라인 패턴이라고 칭한다. 라인 패턴을 형성한 후, 라인 패턴에 게이트 산 화 공정(Gate Side Wall Oxidation)을 진행하여 게이트의 측면 산화막(13)을 형성한다.Then, as shown in FIG. 1B, a portion of the tunnel oxide film 12, the floating gate 14, the ONO (oxide / nitride / oxide) film 16 and the control gate 18 formed on the semiconductor substrate 10 are shown. Is removed by a predetermined width in the direction perpendicular to the device isolation film. Through this patterning process, a plurality of stacks in which the tunnel oxide film 12, the floating gate 14, the ONO (oxide / nitride / oxide) film 16, and the control gate 18 are stacked are formed. These are called line patterns. After forming the line pattern, a gate oxidation process (Gate Side Wall Oxidation) is performed on the line pattern to form the side oxide layer 13 of the gate.

다음으로, 도 1c에 도시된 바와 같이, 라인 패턴 및 측면 산화막(13)을 포함한 반도체 기판(10) 전면에 산화물(HTO) 및 실리콘나이트라이드(SiN)을 차례대로 증착하고 이를 에치백 공정을 통해 선택적으로 제거하여 라인 패턴의 양측면에 라인 패턴을 분리 및 보호하기 위한 스페이서(20)를 형성한다. Next, as shown in FIG. 1C, an oxide (HTO) and silicon nitride (SiN) are sequentially deposited on the entire surface of the semiconductor substrate 10 including the line pattern and the side oxide layer 13 and then etched back through the etch back process. It is selectively removed to form a spacer 20 for separating and protecting the line pattern on both sides of the line pattern.

이후, 공지된 후속 공정을 통해 플래시 메모리 소자를 완성한다. Thereafter, the flash memory device is completed through a known subsequent process.

하지만, 종래의 플래시 메모리 소자의 제조방법은 소자의 집적율이 높아짐에 유지 실패(Retention Fail) 및 HTOL에 취약한 구조가 된다. 이로 인해, 스페이서의 두께가 얇아지므로 스페이서를 통한 데이터 로스가 발생하는 문제점이 있다.However, the conventional method of manufacturing a flash memory device has a structure vulnerable to retention failure and HTOL due to the high integration rate of the device. As a result, since the thickness of the spacer becomes thin, there is a problem that data loss occurs through the spacer.

따라서, 상기와 같은 문제점을 해결하기 위하여, 본 발명은 데이터 로스(Date Loss)를 감소시킬 수 있는 플래시 메모리 소자의 제조방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device capable of reducing data loss.

본 발명에 따른 플래시 메모리 소자의 제조방법은 반도체 기판 상에 터널산화막, 플로팅게이트, ONO막 및 콘트롤게이트를 순차적으로 형성하여 라인패턴을 형성하는 단계와, 상기 라인 패턴에 게이트 산화 공정을 수행하여 측면 산화막을 형성하는 단계와, 상기 측면 산화막을 포함한 반도체 기판 상에 어닐 공정을 통해 질화산화막을 형성하는 단계와, 상기 질화산화막을 포함한 라인 패턴의 양측벽에 스페이서를 형성하는 단계를 포함하는 것을 특징으로 한다.In the method of manufacturing a flash memory device according to the present invention, a tunnel pattern, a floating gate, an ONO layer, and a control gate are sequentially formed on a semiconductor substrate to form a line pattern, and a gate oxidation process is performed on the line pattern to form a side surface. Forming an oxide film through the annealing process on the semiconductor substrate including the side oxide film, and forming spacers on both sidewalls of the line pattern including the nitride oxide film. do.

이상에서 설명한 바와 같이, 본 발명에 따른 플래시 메모리 소자의 제조방법은 산화질화막을 이용한 스페이서를 형성함으로써 유지 실패(Retention Fail)의 원인 전자들을 차단하여 소자 구현시 데이터 로스를 감소시킬 수 있다. As described above, the method of manufacturing a flash memory device according to the present invention may reduce the data loss when the device is implemented by blocking electrons causing retention failure by forming a spacer using an oxynitride film.

이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

도 2a 내지 도 2d는 본 발명에 따른 플래시 메모리 소자의 제조 공정을 도시한 단면도이다.2A to 2D are cross-sectional views illustrating a manufacturing process of a flash memory device according to the present invention.

먼저 도 2a에 도시된 바와 같이, 반도체 기판(100)에 소정의 거리만큼 이격된 복수의 소자분리막(미도시)을 형성한다. 이 소자분리막들은 활성 소자 영역을 정의하며, 비트 라인 방향으로 서로 나란하게 형성된다. 그리고, 활성 소자 영역의 기판 내부에 웰(Well)을 형성한다. 예를 들어, P형 기판인 경우, 깊은 N웰을 형성한 다음, 포켓 P 웰을 형성한다. 그 후 임플란트 공정을 통해 셀 문턱 전압을 결정한다. 이후, 반도체 기판(100)의 활성 소자 영역에 터널산화막(110) 및 플로팅게이트(120)을 형성한다. 여기서, 플로팅게이트(120)는 불순물이 도핑된 폴리실리콘으로 형성된다. 이어서, 반도체 기판(100)의 전면에 ONO(oxide/nitride/oxide)막(140) 및 콘트롤게이트(160)를 차례로 형성한다. 여기서, 콘트롤게이트(160)는 실리콘산화막으로 형성된다. First, as shown in FIG. 2A, a plurality of device isolation layers (not shown) spaced apart by a predetermined distance are formed on the semiconductor substrate 100. The device isolation layers define an active device region and are formed in parallel with each other in the bit line direction. Then, a Well is formed in the substrate of the active element region. For example, in the case of a P-type substrate, deep N wells are formed, followed by pocket P wells. The cell threshold voltage is then determined through an implant process. Thereafter, the tunnel oxide film 110 and the floating gate 120 are formed in the active device region of the semiconductor substrate 100. Here, the floating gate 120 is formed of polysilicon doped with impurities. Subsequently, the ONO (oxide / nitride / oxide) film 140 and the control gate 160 are sequentially formed on the entire surface of the semiconductor substrate 100. Here, the control gate 160 is formed of a silicon oxide film.

그리고 나서, 도 2b에 도시된 바와 같이, 반도체 기판(100) 위에 형성된 터널산화막(110), 플로팅게이트(120), ONO(oxide/nitride/oxide)막(140) 및 콘트롤게이트(160)의 일부를 소자 분리막에 수직한 방향으로 소정의 폭만큼 제거한다. 이 패터닝 공정을 거치면, 터널산화막(110), 플로팅게이트(120), ONO(oxide/nitride/oxide)막(140) 및 콘트롤게이트(160)가 적층된 복수의 스택이 형성되는데, 이하에서는 이 스택들을 라인 패턴이라고 칭한다. 라인 패턴을 형성한 후, 라인 패턴에 게이트 산화 공정(Gate Side Wall Oxidation)을 진행하여 게이트의 측면 산화막(SiO2)(180)을 형성한다. 여기서, 게이트 산화 공정은 800~900℃에서 실시하는 것이 바람직하다. Then, as shown in FIG. 2B, part of the tunnel oxide film 110, the floating gate 120, the oxide / nitride / oxide (ONO) film 140, and the control gate 160 formed on the semiconductor substrate 100. Is removed by a predetermined width in the direction perpendicular to the device isolation film. Through this patterning process, a plurality of stacks in which the tunnel oxide film 110, the floating gate 120, the ONO (oxide / nitride / oxide) film 140, and the control gate 160 are stacked are formed. These are called line patterns. After forming the line pattern, a gate oxidation process (Gate Side Wall Oxidation) is performed on the line pattern to form a gate side oxide layer (SiO 2) 180. Here, it is preferable to perform a gate oxidation process at 800-900 degreeC.

다음으로, 도 2c에 도시된 바와 같이, 라인 패턴 및 측면 산화막(180)을 포 함한 반도체 기판(100) 전면에 NO 가스를 이용한 어닐(Anneal) 공정을 수행함으로써 질화산화막(SiON)(200)을 형성한다. 여기서, 질화산화막(200) 형성은 800~900℃에서 실시하는 것이 바람직하다. 이때, NO 가스를 이용한 어닐 공정은 종래의 LDD 어닐 공정과 동일 온도에서 진행하기 때문에 본 발명에 따른 플래시 메모리 소자의 제조방법은 LDD 어닐 공정 없이 NO 가스를 이용한 어닐 공정으로 LDD 영역의 이온들을 대신하여 확산(Diffusion)시킬 수 있다. Next, as shown in FIG. 2C, the nitride oxide film (SiON) 200 is formed by performing an annealing process using NO gas on the entire surface of the semiconductor substrate 100 including the line pattern and the side oxide film 180. Form. Here, the nitride oxide film 200 is preferably formed at 800 to 900 ° C. At this time, the annealing process using the NO gas proceeds at the same temperature as the conventional LDD annealing process, so the flash memory device manufacturing method according to the present invention is an annealing process using the NO gas without the LDD annealing process, instead of the ions in the LDD region. Diffusion can be achieved.

이후, 도 2d에 도시된 바와 같이, 반도체 기판(100) 전면에 실리콘나이트라이드(SiN)를 증착하고 이를 에치백 공정을 통해 선택적으로 제거하여 라인 패턴의 양측면에 라인 패턴을 분리 및 보호하기 위한 스페이서(220)를 형성한다. Thereafter, as shown in FIG. 2D, silicon nitride (SiN) is deposited on the entire surface of the semiconductor substrate 100 and selectively removed through an etch back process to separate and protect the line patterns on both sides of the line pattern. To form 220.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여 져야만 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

도 1a 내지 1c는 종래의 플래시 메모리 소자의 제조공정을 나타낸 단면도.1A to 1C are cross-sectional views illustrating a manufacturing process of a conventional flash memory device.

도 2a 내지 도 2d는 본 발명에 따른 플래시 메모리 소자의 제조 공정을 도시한 단면도.2A to 2D are cross-sectional views illustrating a manufacturing process of a flash memory device according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100: 반도체기판 110: 터널산화막100: semiconductor substrate 110: tunnel oxide film

120: 플로팅게이트 140: ONO막120: floating gate 140: ONO film

160: 콘트롤게이트 180: 측면산화막160: control gate 180: side oxide film

200: 질화산화막 220: 스페이서200: nitride oxide film 220: spacer

Claims (5)

반도체 기판 상에 터널산화막, 플로팅게이트, ONO막 및 콘트롤게이트를 순차적으로 형성하여 라인패턴을 형성하는 단계와, Forming a line pattern by sequentially forming a tunnel oxide film, a floating gate, an ONO film, and a control gate on a semiconductor substrate; 상기 라인 패턴에 게이트 산화 공정을 수행하여 측면 산화막을 형성하는 단계와, Performing a gate oxidation process on the line pattern to form a side oxide film; 상기 측면 산화막을 포함한 반도체 기판 상에 어닐 공정을 통해 질화산화막을 형성하는 단계와, Forming a nitride oxide film through an annealing process on the semiconductor substrate including the side oxide film; 상기 질화산화막을 포함한 라인 패턴의 양측벽에 스페이서를 형성하는 단계를 포함하는 것을 특징으로 하는 플래시 메모리 소자의 제조방법. And forming spacers on both sidewalls of the line pattern including the nitride oxide film. 제 1항에 있어서, The method of claim 1, 상기 질화산화막은 NO 가스를 이용한 어닐 공정을 통해 형성되는 것을 특징으로 하는 플래시 메모리 소자의 제조방법.The nitride oxide film is a method of manufacturing a flash memory device, characterized in that formed through an annealing process using NO gas. 제 1항에 있어서,The method of claim 1, 상기 라인 패턴의 양측벽에 스페이서를 형성하는 단계는 Forming spacers on both side walls of the line pattern 상기 반도체 기판 전면에 실리콘나이트라이드(SiN)를 증착하는 단계와,Depositing silicon nitride (SiN) on the entire surface of the semiconductor substrate; 상기 실리콘나이트라이드를 에치백 공정을 통해 선택적으로 제거하는 단계를 포함하는 것을 특징하는 플래시 메모리 소자의 제조방법.And selectively removing the silicon nitride through an etch back process. 제 1항에 있어서, The method of claim 1, 상기 게이트 산화 공정은 800~900℃에서 수행하는 것을 특징으로 하는 플래시 메모리 소자의 제조방법.The gate oxidation process is a method of manufacturing a flash memory device, characterized in that performed at 800 ~ 900 ℃. 제 2항에 있어서, The method of claim 2, 상기 NO 가스를 이용한 어닐 공정은 800~900℃에서 수행하는 것을 특징으로 하는 플래시 메모리 소자의 제조방법.The annealing process using the NO gas is a manufacturing method of a flash memory device, characterized in that performed at 800 ~ 900 ℃.
KR1020080050862A 2008-05-30 2008-05-30 Method manufactruing of flash memory device KR20090124574A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020080050862A KR20090124574A (en) 2008-05-30 2008-05-30 Method manufactruing of flash memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020080050862A KR20090124574A (en) 2008-05-30 2008-05-30 Method manufactruing of flash memory device

Publications (1)

Publication Number Publication Date
KR20090124574A true KR20090124574A (en) 2009-12-03

Family

ID=41686495

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080050862A KR20090124574A (en) 2008-05-30 2008-05-30 Method manufactruing of flash memory device

Country Status (1)

Country Link
KR (1) KR20090124574A (en)

Similar Documents

Publication Publication Date Title
US8890232B2 (en) Methods and apparatus for non-volatile memory cells with increased programming efficiency
US20040256661A1 (en) Nonvolatile memory capable of storing multibits binary information and the method of forming the same
KR20090046155A (en) Method manufacturing of flash memory device
KR100654560B1 (en) Flash memory device and manufacturing method thereof
KR100654559B1 (en) Nor-type flash memory cell array and manufacturing method thereof
KR100806787B1 (en) Method of Manufacturing Flash Semiconductor Device
KR20080009422A (en) Methode for forming three-demention flash memory cell
US20070108504A1 (en) Non-volatile memory and manufacturing method and operating method thereof
KR20110068769A (en) Flash memory device and method for manufacturing flash memory device
KR100788371B1 (en) Methode for menufacturing flash memory device
KR100660718B1 (en) Method for forming floating gate array of flash memory device
KR20100079329A (en) Method manufactruing of flash memory device
KR100660282B1 (en) Method for forming common source line in nor-type flash memory device
KR100649308B1 (en) Flash memory device and manufacturing method of self-aligned floating gate array
KR20090124574A (en) Method manufactruing of flash memory device
US7883984B2 (en) Method of manufacturing flash memory device
KR100731077B1 (en) Method for forming common source line in nor-type flash memory device
US20180151585A1 (en) Method for manufacturing embedded non-volatile memory
KR100917816B1 (en) Method Manufactruing of Flash Memory Device
KR100992783B1 (en) Method for manufacturing a flash semiconductor device
KR100884979B1 (en) Method manufactruing of flash memory device
KR20090124570A (en) Method manufactruing of flash memory device
KR101033402B1 (en) Flash memory device and manufacturing method the same
KR20090072022A (en) Method manufactruing of flash memory device
KR20110065892A (en) Flash memory device and method manufactruing of the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application