KR20090072022A - Method manufactruing of flash memory device - Google Patents

Method manufactruing of flash memory device Download PDF

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KR20090072022A
KR20090072022A KR1020070139991A KR20070139991A KR20090072022A KR 20090072022 A KR20090072022 A KR 20090072022A KR 1020070139991 A KR1020070139991 A KR 1020070139991A KR 20070139991 A KR20070139991 A KR 20070139991A KR 20090072022 A KR20090072022 A KR 20090072022A
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film
oxide film
gate
flash memory
floating gate
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KR1020070139991A
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Korean (ko)
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남상우
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주식회사 동부하이텍
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Publication of KR20090072022A publication Critical patent/KR20090072022A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A manufacturing method of a flash memory device is provided to remove a floating charge by using an additive in a process for forming a side surface oxide film of a gate. A tunnel oxide film(115), a floating gate(117), an ONO(Oxide Nitride Oxide) film(119), and a control gate(121) are successively formed on a semiconductor substrate(110). The tunnel oxide film, the floating gate, the ONO film, and the control gate are removed as a fixed width into a vertical direction about an isolation film. A side surface oxide film(130) is formed through an oxidation process using an additive in both side walls of the tunnel oxide film, the floating gate, the ONO film, and the control gate. A first side wall spacer and a second side wall spacer are formed in both side walls of the tunnel oxide film, the floating gate, the ONO film, and the control gate including the side surface oxide film. The additive is HCL. The first side wall spacer and the second side wall spacer are made of HTO and SiN.

Description

플래시 메모리 소자의 제조방법{Method Manufactruing of Flash Memory Device} Manufacturing method of flash memory device {Method Manufactruing of Flash Memory Device}

본 발명은 플래시 메모리 소자에 관한 것으로, 특히, 유동전하를 제거할 수 있는 플래시 메모리 소자의 제조방법에 관한 것이다. The present invention relates to a flash memory device, and more particularly, to a method of manufacturing a flash memory device that can remove the flow charge.

플래시 메모리 소자는 정보를 쓰기, 소거 및 읽기를 할 수 있는 일종의 PROM(Programable ROM)이다. Flash memory devices are a type of programmable ROM (PROM) capable of writing, erasing, and reading information.

플래시 메모리 소자는 셀 어레이 체계에 따라, 비트 라인과 접지 사이에 셀이 병렬로 배치된 NOR형 구조와, 직렬로 배치된 NAND형 구조로 나눌 수 있다. Flash memory devices may be divided into NOR-type structures in which cells are disposed in parallel between bit lines and ground, and NAND-type structures arranged in series, according to a cell array scheme.

NOR형 플래시 메모리 소자는 읽기 동작을 수행할 때 고속 랜덤 액세스가 가능하므로 보통 휴대폰 부팅용으로 널리 사용되고 있다. NAND형 플래시 메모리 소자는 읽기 속도는 느리지만 쓰기 속도가 빨라 보통 데이터 저장용에 적합하고 또한 소형화에 유리하다는 장점을 가지고 있다.NOR flash memory devices are commonly used for booting mobile phones because they allow high-speed random access when performing read operations. NAND-type flash memory devices have a slow read speed but a fast write speed, and are suitable for data storage and small size.

또한, 플래시 메모리 소자는 단위 셀의 구조에 따라, 스택 게이트형과 스플릿트 게이트형으로 나뉠 수 있으며, 전하 저장층의 형태에 따라 플로팅 게이트 소자 및 SONOS(Silicon-Oxide-Nitride-Oxide-Silicon) 소자로 구분될 수 있다. 이 중 에서 플로팅 게이트 소자는 통상 그 주위가 절연체로 둘러 싸여진 다결정 실리콘으로 형성된 플로팅 게이트를 포함하고, 이 플로팅 게이트에 채널 핫 캐리어 주입(Channel Hot Carrier Injection) 또는 F-N 터널링(Fowler-Nordheim Tunneling)에 의해 전하가 주입 또는 방출됨으로써 데이터의 저장 및 소거가 이루어진다.In addition, the flash memory device may be classified into a stack gate type and a split gate type according to the unit cell structure, and a floating gate device and a silicon-oxide-nitride-oxide-silicon (SONOS) device according to the shape of the charge storage layer. It can be divided into. Among them, the floating gate device usually includes a floating gate formed of polycrystalline silicon surrounded by an insulator, and is connected to the floating gate by channel hot carrier injection or FN tunneling (Fowler-Nordheim Tunneling). The charge is injected or released to store and erase the data.

이하, 첨부된 도면을 참조하여 종래의 플래시 메모리 소자를 설명하면 다음과 같다.Hereinafter, a conventional flash memory device will be described with reference to the accompanying drawings.

도 1은 종래의 플래시 메모리 소자를 나타낸 단면도이다. 1 is a cross-sectional view of a conventional flash memory device.

도 1에 도시된 바와 같이, 종래의 플래시 메모리 소자는 반도체 기판(11)의 활성 소자 영역에 차례대로 형성된 터널산화막(15), 플로팅게이트(17), ONO(oxide/nitride/oxide)막(19) 및 콘트롤게이트(21)와, 터널산화막(15), 플로팅게이트(17), ONO(oxide/nitride/oxide)막(19) 및 콘트롤게이트(20)의 양 측벽에 형성되는 측면 산화막(21)과, 측면 산화막(21)을 포함한 게이트의 양측면에 형성되는 사이드월 스페이서(23)를 포함하여 구성된다. As shown in FIG. 1, a conventional flash memory device includes a tunnel oxide film 15, a floating gate 17, and an ONO (oxide / nitride / oxide) film 19 sequentially formed in an active device region of a semiconductor substrate 11. ) And side gate oxide films 21 formed on both sidewalls of the control gate 21, the tunnel oxide film 15, the floating gate 17, the ONO (oxide / nitride / oxide) film 19, and the control gate 20. And sidewall spacers 23 formed on both side surfaces of the gate including the side oxide film 21.

여기서, 사이드월 스페이서(23)는 각각 HTO, TEOS(Tetra-Ethyl-Ortho-Silicate) 및 SiN으로 차례대로 형성된 제 1, 2 및 3 사이드월 스페이서(23a, 23b, 23c)를 포함하여 구성된다. Here, the sidewall spacers 23 include first, second and third sidewall spacers 23a, 23b and 23c sequentially formed of HTO, TEOS (Tetra-Ethyl-Ortho-Silicate) and SiN, respectively.

하지만, 종래의 플래시 메모리 소자의 제조방법은 사이드월 스페이서에서 전하(Charge)가 로스(Loss)된 후, 트랩된 전하가 전하 게인(Gain)을 유발하는 문제점이 있다. However, a conventional method of manufacturing a flash memory device has a problem in that after the charge is lost in the sidewall spacer, the trapped charge causes the charge gain.

따라서, 상기와 같은 문제점을 해결하기 위하여, 본 발명은 유동전하를 제거할 수 있는 플래시 메모리 소자의 제조방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a flash memory device capable of removing the flow charge.

본 발명에 따른 플래시 메모리 소자의 제조방법은 반도체 기판 상에 터널산화막, 플로팅게이트, ONO막 및 콘트롤게이트를 순차적으로 형성하는 단계와, 상기 터널산화막, 플로팅게이트, ONO막 및 콘트롤게이트을 소자 분리막에 수직한 방향으로 소정의 폭만큼 제거하는 단계와, 상기 터널산화막, 플로팅게이트, ONO막 및 콘트롤게이트의 양측벽에 첨가제를 사용한 산화공정을 통해 측면 산화막을 형성하는 단계와, 상기 측면 산화막을 포함한 상기 터널산화막, 플로팅게이트, ONO막 및 콘트롤게이트의 양측벽에 제 1 및 제 2 사이드월 스페이서를 형성하는 단계를 포함하는 것을 특징으로 한다.A method of manufacturing a flash memory device according to the present invention includes the steps of sequentially forming a tunnel oxide film, a floating gate, an ONO film, and a control gate on a semiconductor substrate, and perpendicularly to the device isolation layer. Forming a side oxide film by a predetermined width in one direction, through an oxidation process using additives on both sidewalls of the tunnel oxide film, the floating gate, the ONO film, and the control gate, and the tunnel including the side oxide film. And forming first and second sidewall spacers on both sidewalls of the oxide film, the floating gate, the ONO film, and the control gate.

이상에서 설명한 바와 같이, 본 발명에 따른 플래시 메모리 소자의 제조방법은 게이트의 측면 산화막 형성 공정 시 첨가제 적용으로 유동전하를 제거할 수 있다. As described above, the method of manufacturing the flash memory device according to the present invention may remove the flow charge by applying an additive during the side oxide film forming process of the gate.

이하, 첨부된 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

도 2a 내지 도 2e는 본 발명에 따른 플래시 메모리 소자의 제조 공정을 도시 한 단면도이다.2A to 2E are cross-sectional views illustrating a manufacturing process of a flash memory device according to the present invention.

먼저, 도 2a에 도시된 바와 같이, 반도체 기판(110)에 소정의 거리만큼 이격된 복수의 소자분리막(미도시)을 형성한다. 그리고, 활성 소자 영역의 기판 내부에 웰(Well)을 형성한 후, 터널산화막(115), 플로팅게이트(117), ONO(oxide/nitride/oxide)막(119) 및 콘트롤게이트(121)를 차례로 형성한다. 여기서, 콘트롤게이트(121)는 실리콘산화막으로 형성된다. First, as shown in FIG. 2A, a plurality of device isolation layers (not shown) spaced apart by a predetermined distance are formed on the semiconductor substrate 110. After forming a well in the substrate of the active element region, the tunnel oxide film 115, the floating gate 117, the ONO (oxide / nitride / oxide) film 119, and the control gate 121 are sequentially formed. Form. Here, the control gate 121 is formed of a silicon oxide film.

이어서, 도 2b에 도시된 바와 같이, 반도체 기판(110) 상에 형성된 터널산화막(115), 플로팅게이트(117), ONO(oxide/nitride/oxide)막(119) 및 콘트롤게이트(121)의 일부를 포토리소그래피(Photo Lithography) 공정 및 반응성 이온 에칭(Reactive Ion Etching; RIE) 공정으로 소자 분리막에 수직한 방향으로 소정의 폭만큼 제거한다. 이러한 공정을 거치면, 터널산화막(115), 플로팅게이트(117), ONO(oxide/nitride/oxide)막(119) 및 콘트롤게이트(121)가 적층된 복수의 스택이 형성된다. Subsequently, as shown in FIG. 2B, a portion of the tunnel oxide film 115, the floating gate 117, the oxide / nitride / oxide (ONO) film 119 and the control gate 121 formed on the semiconductor substrate 110 are formed. Is removed by a photolithography process and reactive ion etching (RIE) process by a predetermined width in a direction perpendicular to the device isolation layer. Through this process, a plurality of stacks in which the tunnel oxide film 115, the floating gate 117, the ONO (oxide / nitride / oxide) film 119, and the control gate 121 are stacked are formed.

그리고나서, 도 2c에 도시된 바와 같이, 게이트 산화 공정(Gate Side Wall Oxidation)을 진행하여 게이트의 측면 산화막(130)을 형성한다. 이때, 게이트 산화 공정시 첨가제(HCL(2~5%))를 사용한다. 이러한 첨가제(HCL)의 사용으로 인하여 유동전하가 제거된다. Then, as shown in FIG. 2C, the gate side wall oxidation is performed to form the side oxide layer 130 of the gate. At this time, an additive (HCL (2-5%)) is used in the gate oxidation process. The use of this additive (HCL) removes the flow charge.

다음으로, 도 2d에 도시된 바와 같이, 측면 산화막(21)을 포함한 게이트의 양측면에 게이트를 분리 및 보호하기 위해 사이드월 스페이서(140)를 형성한다. 여기서, 사이드월 스페이서(140)는 전면에 HTO 및 SiN을 증착하고 선택적으로 제거하 여 형성된 제 1 및 2 사이드월 스페이서(140a,140b)를 포함하여 구성된다. 한편, HTO는 60~150Å의 두께로 형성되는 것이 바람직하다. Next, as shown in FIG. 2D, sidewall spacers 140 are formed on both sides of the gate including the side oxide layer 21 to separate and protect the gate. Here, the sidewall spacers 140 include first and second sidewall spacers 140a and 140b formed by depositing and selectively removing HTO and SiN on the entire surface. On the other hand, HTO is preferably formed to a thickness of 60 ~ 150 60.

이와 같이, 종래의 사이드월 스페이서와 다르게 TEOS로 이루어진 사이드월 스페이서를 제거하여 두께를 감소시킴으로써 트랩(Trap)되는 볼륨(Volume)을 최소화할 수 있다.As such, unlike the conventional sidewall spacers, the trapped volume can be minimized by removing the sidewall spacers made of TEOS to reduce the thickness.

이후, 층간절연막 형성, 콘택홀 형성 및 드레인 콘택 형성 등과 같은 공지된 후속공정을 통해 플래시 메모리 소자를 완성한다. Thereafter, the flash memory device is completed through a known subsequent process such as forming an interlayer insulating film, forming a contact hole, and forming a drain contact.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여 져야만 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

도 1은 종래의 플래시 메모리 소자를 나타낸 단면도.1 is a cross-sectional view showing a conventional flash memory device.

도 2a 내지 도 2d는 본 발명에 따른 플래시 메모리 소자의 제조 공정을 도시한 단면도.2A to 2D are cross-sectional views illustrating a manufacturing process of a flash memory device according to the present invention.

Claims (3)

반도체 기판 상에 터널산화막, 플로팅게이트, ONO막 및 콘트롤게이트를 순차적으로 형성하는 단계와, Sequentially forming a tunnel oxide film, a floating gate, an ONO film, and a control gate on the semiconductor substrate; 상기 터널산화막, 플로팅게이트, ONO막 및 콘트롤게이트을 소자 분리막에 수직한 방향으로 소정의 폭만큼 제거하는 단계와,Removing the tunnel oxide film, the floating gate, the ONO film, and the control gate by a predetermined width in a direction perpendicular to the device isolation film; 상기 터널산화막, 플로팅게이트, ONO막 및 콘트롤게이트의 양측벽에 첨가제를 사용한 산화공정을 통해 측면 산화막을 형성하는 단계와,Forming a side oxide film through an oxidation process using additives on both sidewalls of the tunnel oxide film, the floating gate, the ONO film, and the control gate; 상기 측면 산화막을 포함한 상기 터널산화막, 플로팅게이트, ONO막 및 콘트롤게이트의 양측벽에 제 1 및 제 2 사이드월 스페이서를 형성하는 단계를 포함하는 것을 특징으로 하는 플래시 메모리 소자의 제조방법.And forming first and second sidewall spacers on both sidewalls of the tunnel oxide film, the floating gate, the ONO film, and the control gate including the side oxide film. 제 1항에 있어서, The method of claim 1, 상기 첨가제는 HCL인 것을 특징으로 하는 플래시 메모리 소자의 제조방법.The additive is a method of manufacturing a flash memory device, characterized in that the HCL. 제 1항에 있어서,The method of claim 1, 상기 제 1 및 제 2 사이드월 스페이서는 HTO 및 SiN으로 형성되는 것을 특징으로 하는 플래시 메모리 소자의 제조방법.The first and second sidewall spacers are formed of HTO and SiN.
KR1020070139991A 2007-12-28 2007-12-28 Method manufactruing of flash memory device KR20090072022A (en)

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