KR100917816B1 - Method Manufactruing of Flash Memory Device - Google Patents

Abstract

The present invention relates to a method of manufacturing a flash memory device that can improve the coupling ratio,

A method of manufacturing a flash memory device according to the present invention includes forming a plurality of device isolation films spaced apart by a predetermined distance and parallel to each other on a semiconductor substrate, and including a tunnel oxide film, a first floating gate, on a semiconductor substrate including the device isolation film. Sequentially forming a second floating gate, an ONO film, and a control gate; forming insulating spacers on both sidewalls of the tunnel oxide film, the first floating gate, the second floating gate, the ONO film, and the control gate; Forming a source / drain region on the semiconductor substrate at both sides of the insulating spacer, forming a poly-silicon metal dielectric (PMD) on the entire surface of the semiconductor substrate including the source / drain region, and selectively selecting the PMD Patterning the contact hole to form a contact hole, and forming a drain contact in the contact hole. The.

Floating Gate, Coupling Ratio

Description

Manufacturing method of flash memory device {Method Manufactruing of Flash Memory Device}

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device that can improve the coupling ratio.

Flash memory devices are a type of programmable ROM (PROM) capable of writing, erasing, and reading information.

Flash memory devices may be divided into NOR-type structures in which cells are disposed in parallel between bit lines and ground, and NAND-type structures arranged in series, according to a cell array scheme.

NOR flash memory devices are commonly used for booting mobile phones because they allow high-speed random access when performing read operations. NAND-type flash memory devices have a slow read speed but a fast write speed, and are suitable for data storage and small size.

In addition, the flash memory device may be classified into a stack gate type and a split gate type according to the unit cell structure, and a floating gate device and a silicon-oxide-nitride-oxide-silicon (SONOS) device according to the shape of the charge storage layer. It can be divided into. Among them, the floating gate device usually includes a floating gate formed of polycrystalline silicon surrounded by an insulator, and is connected to the floating gate by channel hot carrier injection or FN tunneling (Fowler-Nordheim Tunneling). The charge is injected or released to store and erase the data.

1A to 1D are cross-sectional views illustrating a manufacturing process of a conventional flash memory device.

First, as shown in FIG. 1A, a plurality of device isolation layers 13 spaced apart by a predetermined distance from the semiconductor substrate 11 are formed. The device isolation layers 13 define an active device region and are formed to be parallel to each other in the bit line direction. Then, a Well is formed in the substrate of the active element region. For example, in the case of a P-type substrate, deep N wells are formed, followed by pocket P wells. The cell threshold voltage is then determined through an implant process. Thereafter, the tunnel oxide film 15 and the floating gate 17 are formed in the active element region of the semiconductor substrate 11. Here, the floating gate 17 is formed of polysilicon doped with impurities. Subsequently, an ONO (oxide / nitride / oxide) film 19 and a control gate 21 are sequentially formed on the entire surface of the semiconductor substrate 11. Here, the control gate 21 is formed of a silicon oxide film.

Then, as shown in FIG. 1B, part of the tunnel oxide film 15, the floating gate 17, the ONO (oxide / nitride / oxide) film 19 and the control gate 21 formed on the semiconductor substrate 11. Is removed by a predetermined width in the direction perpendicular to the device isolation film. Through this patterning process, a plurality of stacks in which the tunnel oxide film 15, the floating gate 17, the ONO (oxide / nitride / oxide) film 19, and the control gate 21 are stacked are formed. These are called line patterns. After the line pattern is formed, an insulating film is formed over the entire semiconductor substrate 11, and an insulating spacer 23 is formed through an etch back process. An insulating spacer 23 is formed on the sidewalls of each of the line patterns.

Subsequently, as shown in FIG. 1C, an ion implantation process is performed using the insulating spacers 23 and the control gates 21 as masks, so that source / drain regions are formed on the semiconductor substrates 11 on both sides of the insulating spacers 23. 30 is formed. The source / drain regions 30 are regions in which ions are implanted by an ion implantation process and are conductive.

Next, as shown in FIG. 1D, a poly-silicon metal dielectric (PMD) 32 is formed on the entire surface of the semiconductor substrate 11 including the source / drain regions 30 using an insulating material, and the PMD 32 ) Is selectively patterned to form contact holes. A conductive material such as tungsten is formed in the contact hole to form the drain contact 34. Thereafter, a metal wire (not shown) that is electrically connected to the drain contact 34 may be formed.

However, the conventional method of manufacturing a flash memory device does not scale in the vertical direction, so a gap fill problem occurs when PMD is deposited. As a result, the coupling ratio is reduced, thereby improving performance of the flash memory device. There is a problem that is reduced.

Accordingly, in order to solve the above problems, an object of the present invention is to provide a method of manufacturing a flash memory device that can improve the coupling ratio.

A method of manufacturing a flash memory device according to the present invention includes the steps of forming a plurality of device isolation films on a semiconductor substrate, a tunnel oxide film, a first floating gate, a second floating gate, an ONO film and a control on a semiconductor substrate including the device isolation film. Forming gates sequentially, forming insulating spacers on both sidewalls of the tunnel oxide film, the first floating gate, the second floating gate, the ONO film, and the control gate, and forming the gate on the semiconductor substrate on both sides of the insulating spacer. Forming a source / drain region in the semiconductor substrate, forming a poly-silicon metal dielectric (PMD) on the entire surface of the semiconductor substrate including the source / drain region, forming a contact hole in the PMD, and forming a drain in the contact hole And forming a contact, wherein the second floating gate is formed by depositing a metal.

As described above, in the method of manufacturing the flash memory device according to the present invention, since the floating gate has a stack structure of polysilicon and metal, the overall thickness of the floating gate can be lowered and the resistance of the floating gate can be reduced. The performance of the memory device can be improved. In addition, the gap fill problem that may occur during PMD deposition may be solved.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2A to 2E are cross-sectional views illustrating a manufacturing process of a flash memory device according to the present invention.

First, as shown in FIG. 2A, a plurality of device isolation layers 113 spaced apart by a predetermined distance from the semiconductor substrate 110 are formed. The device isolation layers 113 define an active device region and are formed to be parallel to each other in the bit line direction. Then, a Well is formed in the substrate of the active element region. For example, in the case of a P-type substrate, deep N wells are formed, followed by pocket P wells. The cell threshold voltage is then determined through an implant process. Thereafter, the tunnel oxide film 115 and the first floating gate 117a are formed in the active device region of the semiconductor substrate 110. Here, the first floating gate 117a is a polysilicon doped with an N-type dopant such as phosphorous (Phosphorous) to form a thickness of 30nm ~ 50nm by applying the LPCVD process, the doping concentration is very high concentration of 1e20 ~ 3e20 To have.

Thereafter, as shown in FIG. 2B, metal is deposited on the first floating gate 117a to form the second floating gate 117b. Here, as the metal forming the second floating gate 117b, a metal such as TaN, TiN, or the like is applied. Therefore, the flash memory device according to the present invention has a stack structure of the first floating gate 117a and the second floating gate 117b, whereby the overall thickness of the floating gates 117a and 117b is lowered, thereby causing the floating gate. The resistance of 117a and 117b can be reduced.

Then, the ONO (oxide / nitride / oxide) film 119 and the control gate 121 are sequentially formed on the floating gates 117a and 117b. Here, the control gate 121 is formed of a silicon oxide film.

Subsequently, as shown in FIG. 2C, the tunnel oxide film 115, the floating gates 117a and 117b, the ONO (oxide / nitride / oxide) film 119 and the control gate 121 formed on the semiconductor substrate 110 are formed. A part is removed by a predetermined width in the direction perpendicular to the device isolation film. Through this patterning process, a plurality of stacks in which the tunnel oxide film 115, the floating gates 117a and 117b, the oxide / nitride / oxide (ONO) film 119 and the control gate 121 are stacked are formed. These stacks are called line patterns. After the line pattern is formed, an insulating film is formed over the entire semiconductor substrate 110, and an insulating spacer 123 is formed through an etch back process. The insulating spacer 123 is formed on sidewalls of each of the line patterns.

Next, as shown in FIG. 2D, an ion implantation process is performed by using the insulating spacer 123 and the control gate 121 as a mask so as to provide a source / drain on the semiconductor substrate 110 on both sides of the insulating spacer 123. Area 130 is formed. The source / drain regions 130 are regions in which ions are implanted by an ion implantation process so as to have conductivity.

Thereafter, as shown in FIG. 2E, a poly-silicon metal dielectric (PMD) 132 is formed on the entire surface of the semiconductor substrate 110 including the source / drain regions 130 using an insulating material, and the PMD 132 is formed. Is selectively patterned to form contact holes. A conductive material such as tungsten is formed in the contact hole to form the drain contact 134. Thereafter, a metal wire (not shown) that is electrically connected to the drain contact 134 may be formed. At this time, the flash memory device according to the present invention has a stack structure of the first floating gate 117a and the second floating gate 117b to solve the gap fill problem that may occur when the PMD 132 is deposited and to reduce the coupling ratio. Can be improved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1A to 1D are cross-sectional views illustrating a manufacturing process of a conventional flash memory device.

2A to 2E are cross-sectional views illustrating a manufacturing process of a flash memory device according to the present invention.

Claims (4)

Forming a plurality of device isolation layers on the semiconductor substrate, Sequentially forming a tunnel oxide film, a first floating gate, a second floating gate, an ONO film, and a control gate on a semiconductor substrate including the device isolation film; Forming insulating spacers on both sidewalls of the tunnel oxide film, the first floating gate, the second floating gate, the ONO film, and the control gate; Forming a source / drain region on the semiconductor substrate on both sides of the insulating spacer; Forming a poly-silicon metal dielectric (PMD) on the entire surface of the semiconductor substrate including the source / drain regions; Forming a contact hole in the PMD, and forming a drain contact in the contact hole, The second floating gate is a method of manufacturing a flash memory device, characterized in that formed by depositing a metal. The method of claim 1, The first floating gate is polysilicon, the method of manufacturing a flash memory device, characterized in that formed in a thickness of 30nm ~ 50nm. The method of claim 2, Wherein the polysilicon is doped with phosphorous (Phosphorous) at a doping concentration of 1e20 to 3e20. The method of claim 1, And the second floating gate is formed of TaN or TiN.

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