KR20090123244A - Phase change memory device and write method thereof - Google Patents

Abstract

PURPOSE: A phase change memory device and a writing method thereof are provided to increase durability by preventing characteristic deterioration of a phase-change memory cell irrespective of repetitive writing of reset data. CONSTITUTION: It is determined whether write data to be written in a selected phase-change memory cell is set data or reset data(S10). Write data corresponding to the set data offers a pulse for writing the set data to the phase-change memory cell. A write operation of the set data having no write verification operation is performed(S50). Write data corresponding to the reset data performs a write-write verification loop. A level of a pulse corresponding to an initial reset status is offered at a level lower than a pulse for writing general reset data(S20). A write verification operation for the reset data is performed(S30). A pulse having a level increased more than a previously applied pulse is provided to the selected phase-change memory cell(S40).

Description

Phase change memory device and its writing method {PHASE CHANGE MEMORY DEVICE AND WRITE METHOD THEREOF}

The present invention relates to a semiconductor memory device, and more particularly, to a phase change memory device and a write method thereof.

The demand for semiconductor memory devices capable of random access and high integration and large capacity is increasing day by day. As such a semiconductor memory device, a flash memory mainly used for portable electronic devices and the like is typical. In addition, semiconductor memory devices that replace a DRAM capacitor with a nonvolatile material are emerging. Phase change memory devices (Phase) using ferroelectric RAM (FRAM) using ferroelectric capacitors, magnetic RAM (MRAM) using TMR (tunneling magneto-resistive) films, and chalcogenide alloys change memory device). In particular, the phase change memory device is a nonvolatile memory device, and its manufacturing process is relatively simple, and a large capacity memory can be implemented at low cost.

Phase change memory cells use a material that can be electrically switched between different structured states exhibiting different electrical readout characteristics. For example, memory devices made of a chalcogenide material (hereinafter referred to as a "GST material") which is a germanium antimony-tellurium mixture (GST) are known. GST materials have an amorphous state exhibiting relatively high resistivity and a crystalline state exhibiting relatively low resistivity. That is, in the phase change memory cell, data corresponding to each of the crystalline state or the amorphous state is written by heating the GST material. The size and duration of the heating determine whether the GST material remains in an amorphous or crystalline state. High and low resistivity represent the written logic values '1' and '0', which can be sensed by measuring the resistivity of the GST material. Therefore, the phase change memory device is also called a variable resistance memory device.

In a typical phase change memory device, a memory cell is composed of a resistance element and a switching element. 1 and 2 show memory cells of a phase change memory device. Referring to FIG. 1, a memory cell 10 of a phase change memory device includes a variable resistor 11 as a resistance element and an access transistor 12 as a switching element. The variable resistor 11 is connected to the bit line BL. The access transistor 12 is connected between the variable resistor 11 and ground. The word line WL is connected to the gate of the access transistor 12. When a predetermined voltage is applied to the word line WL, the access transistor 12 is turned on. When the access transistor 12 is turned on, the variable resistor 11 receives the current Ic through the bit line BL.

2 shows a memory cell 20 of another type of phase change memory device. Another type of memory cell 20 includes a variable resistor 21, which is a resistance element, and a diode 22, which is a switching element. The diode 22 is turned on or turned off according to the word line WL voltage.

3 and 4 are diagrams illustrating cell structures and physical properties of the above-described phase change memory device, respectively. FIG. 3 briefly shows a cross section of a phase change memory cell, and FIG. 4 shows the endurance characteristics of the phase change material.

First, referring to FIG. 3, the memory cell 30 includes a variable resistor and an access transistor NT. The variable resistor consists of an upper electrode 31, a phase change material 32, a contact plug 33, and a lower electrode 34. The upper electrode 31 is connected to the bit line BL. The lower electrode 34 is connected between the contact plug 33 and the access transistor NT. The contact plug 33 is formed of a conductive material (for example, TiN, etc.) and is also called a heater plug. The phase change material 32 is formed between the upper electrode 31 and the contact plug 33. The phase (Phase) of the phase change material 32 is changed according to the amplitude (Amplitude), the width (Duration), the fall time (Fall time) of the supplied current pulse. The phase of the phase change material corresponding to Set or Reset is determined by the amorphous volume 35 as shown. In general, the amorphous phase corresponds to the reset state and the crystal phase corresponds to the set state. As the process proceeds from the amorphous state to the crystal state, the amount of amorphous becomes smaller. The phase change material 32 has a resistance that varies depending on the amorphous volume 35 formed. That is, the data to be written is determined according to the amorphous amount 35 of the phase change material 32 formed according to different current pulses.

4 is a graph showing electrical characteristics of the phase change material 32 of FIG. 3. Referring to FIG. 4, a set-stuck failure phenomenon caused by repeatedly writing data corresponding to a reset state (hereinafter, reset data) is illustrated. In order to write the reset data, a relatively larger current must be applied than when writing data corresponding to the set state (hereinafter, set data). However, repetitive write operation of the reset data changes the properties of the phase change material 32. In other words, in response to the write operation of the reset data repeatedly exceeding the limit number of times, the phase change material 32 can no longer reach the resistance value corresponding to the reset state at the same write current. That is, assume that the write pulse voltage for supplying the write current is the voltage V1. When the reset data is repeatedly written to the memory cell by the write pulse voltage V1, the characteristic curve of the phase change material moves from the curve 41 to the curve 45 while the number of times of writing the reset data increases. As a result, when writing the reset data with the write pulse voltage V1, the reset resistance of the phase change material having the characteristic of the curve 45 is no longer changed to a magnitude corresponding to the reset. That is, even when the reset data is written, the resistance of the memory cell is inevitably detected as the size of the set data. The change in the characteristics of the phase change material that occurs as the number of writes increases is referred to as set-stuck failure.

One of the basic characteristics of a memory device is endurance, in which normal read and write functions are maintained even if data is repeatedly written. In particular, in a phase change memory device, sufficient write counts must be supported to support various uses such as random access memory, a semiconductor disk device (SSD), and a storage device of a mobile device, such as a DRAM. However, such problems as the set-stuck failure described above are a major obstacle in the practical use of the phase change memory device. Therefore, there is an urgent need for a technology that can dramatically increase the endurance of a phase change memory device.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a phase change memory device and a write method thereof capable of reducing the deterioration in durability caused by repeatedly writing the reset data.

According to another aspect of the present invention, a method of writing a variable resistance memory device includes: (a) providing a write current to a selected memory cell; And (b) performing a write verify operation according to the type of the write current.

According to another aspect of the present invention, there is provided a data writing method of a variable resistance memory device, the method including: (a) applying a first reset write current to a selected memory cell;

(b) performing a write verify operation on the selected memory cell; And (c) applying a second reset write current to the selected memory cell according to a result of the write verify operation.

A variable resistance memory device of the present invention for achieving the above object, the memory cell array having a plurality of memory cells; A write driver for providing a write current to the selected memory cell; A sense amplifier for reading data of the selected memory cell; And a controller for controlling the write driver to perform a write operation on the selected memory cell, wherein the controller controls the sense amplifier to perform a write verify operation on the selected memory cell according to the type of the write current. do.

A variable resistance memory device of the present invention for achieving the above object, the memory cell array having a plurality of memory cells; Sense amplifiers for reading data stored in selected memory cells; A write driver for writing write data to the selected memory cell; And a controller for controlling the sense amplifier and the write driver, wherein the controller controls the sense amplifier to perform a write verify operation on the selected memory cell according to the type of the write data.

A portable electronic system for achieving the above object includes a variable resistance memory device; And a memory controller for controlling the variable resistance memory device, wherein the variable resistance memory device comprises: a memory cell array having a plurality of memory cells; A write driver for providing a write current to the selected memory cell; A sense amplifier for reading data of a memory cell provided with the write current; And a controller configured to control the write driver and the sense amplifier to perform a write operation and a write verify operation on the selected memory cell, wherein the controller performs the write verify operation according to the type of the write current.

According to the phase change memory device and the write method thereof according to the present invention as described above, it is possible to prevent deterioration of the characteristics of the phase change memory cell in spite of repetitive writing of reset data, thereby improving endurance of the phase change memory device. Can be increased.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and that additional explanations of the claimed invention are provided. Reference numerals are shown in detail in preferred embodiments of the invention, examples of which are shown in the reference figures. In any case, like reference numerals are used in the description and the drawings to refer to the same or like parts.

In the following, a phase change memory device as a variable resistance memory device is used as an example for explaining the features and functions of the present invention. However, one of ordinary skill in the art will readily appreciate the other advantages and performances of the present invention in accordance with the teachings herein. The present invention may be implemented or applied through other embodiments as well. In addition, the detailed description may be modified or changed according to aspects and applications without departing from the scope, technical spirit and other objects of the present invention. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a flowchart briefly illustrating a writing method of a phase change memory device of the present invention. Referring to FIG. 5, in the write method of the phase change memory device of the present invention, it is determined whether to perform a write verify operation according to data written to a memory cell. According to the write method of the present invention, write verification is performed during the write operation of the reset data, and write verification is not performed during the write operation of the set data. In more detail,

When write data is provided, it is determined whether the write data to be written to the selected phase change memory cell is set data or reset data (S10). When write data is set data, a pulse for writing the set data is provided to the phase change memory cell. However, the write operation of the set data does not include a write verify operation for writing or not. The write operation of the set data without the write verify operation is performed (S50).

On the other hand, if the write data is reset data, the procedure moves to the step of performing the write operation of the present invention. That is, a write-write verify loop, which consists of writing reset data and a write verify operation on the written reset data, is performed. The write operation of the reset data begins by applying a pulse corresponding to the reset state to the selected phase change memory cell. Here, the level of the pulse corresponding to the initial reset state is provided at a level lower than the pulse for writing normal reset data (S20). A write verification operation on the reset data is continued (S30). If it is determined that the resistance value of the phase change memory cell is changed to the resistance value corresponding to the reset data, the write operation is terminated. On the other hand, if the resistance of the selected phase change memory cell does not reach the resistance of the size corresponding to the reset state, the procedure goes to step S40 for re-write (Re-write). That is, in the rewriting step S40, a pulse having an increased level than the pulse (current or voltage) previously applied is provided to the selected phase change memory cell. Then, the procedure moves to the write verify step S30. Therefore, the verify step S30 and the rewrite step S40 form a write-write verify loop.

By the above-described method of writing a phase change memory cell, a write-write verify loop will be constructed starting from a low level write current to write reset data. After the resistance of the memory cell reaches the reset resistance value corresponding to the reset state, the supply of the write current is no longer supplied. Therefore, it is possible to suppress the occurrence of set-stuck failure due to a relatively large write current during the write operation of the reset data.

FIG. 6 is a block diagram illustrating a phase change memory device 100 capable of performing a write operation on reset data according to the above-described writing method of FIG. 5. Referring to FIG. 6, the phase change memory device 100 of the present invention may write pulses P_SET and P_RST and bias signals DCBL_SET to write reset or set data according to a verification result of a memory cell to which reset data is written. And a control unit for generating DCBL_RST). The control unit includes a verification comparator 175, a control logic 180, and a write pulse generator 190.

The cell array 110 includes memory cells that each store N-bit data information (N is an integer greater than or equal to 1). In the cell array 110, although not shown, a plurality of memory cells will be arranged in rows (or word lines) and columns (or bit lines). Each memory cell will consist of a switching element and a resistive element. The switching device may be implemented using various devices such as MOS transistors, diodes, and the like. The resistive element will be configured to include a variable resistor made of the GST material described above.

The address decoder 120 decodes an address input from the outside. Here, the address includes a row address and a column address. The address decoder 120 selects a word line WL by a row address, and selects a bit line BL by a column address. To this end, the address decoder 120 provides a column select signal Yi to the column decoder 130.

The column decoder 130 is connected to the memory cell array 110 through the bit line BL and to the write driver circuit 140 through the data line DL. The column decoder 130 electrically connects the data line and the selected bit line in response to the column select signal Yi.

The write driver 140 provides a write current for writing write data to the selected memory cell. The write driver 140 responds to the bias signals DCBL_SET and DCBL_RST provided from the write pulse generator 190, the set pulse P_SET, the reset pulse P_RST, and the write data in response to the write current I_SET or I_RST) is output. The output write current I_SET or I_RST is transferred to the bit line of the selected memory cell through the data line DL and the column decoder 130. When writing the reset data, the write driver 140 may provide the selected memory cell with a step pulse current that gradually increases as a write current upon loop repetition. In the case of writing the reset data, the write driver 140 may provide the reset write current I_RST lower than the normal level in the first loop in response to the bias signal DCBL_RST and the reset pulse P_RST. When the loop is repeated, the gradually increasing stepped reset write current is supplied to the selected memory cell. The write driver 140 continues to supply an increasing reset write current until a verify pass occurs due to a verify operation on the selected memory cell. The interval of a write-write verify loop in which a reset write current corresponding to one pulse is supplied and a verify operation is performed may be performed within a period in which one set pulse P_SET is supplied. Alternatively, a plurality of write-write verify loops may be performed within a period corresponding to one set pulse P_SET.

The verify sense amplifier 150 is controlled by the control logic 180 and is provided to detect whether the write data is normally written through the write driver 140. The verify sense amplifier 150 of the present invention sense-amplifies and amplifies data of a selected memory cell in response to control of the control logic 180. The verify sense amplifier 150 senses and latches data through the bit line of the selected memory cell in response to control signals nPSA and PMUX from the control logic 180. The latched data is provided to the verification comparator 175 as verification data Vfy_data.

The sense amplifier 160 senses data written to a memory cell through a bit line selected by the column decoder 130 in a normal read operation. The sense amplifier 160 transfers the sensed data to the data input / output buffer 170.

The data input / output buffer 170 provides input data DI provided from the outside to the write driver 140 and the verification comparator 175. The data input / output buffer 170 provides data read by the sense amplifier 160 to the outside.

The verify comparator 175 compares the verify data Vfy_data provided from the verify sense amplifier 150 with the input data DI provided from the input / output buffer 170. The verification comparator 175 outputs a pass / fail signal P / F indicating whether the write data is normally written according to the comparison result of the verification data Vfy_data and the input data DI. If the verification data Vfy_data and the input data DI are detected to be the same, the verification comparator 175 may output a verification pass. On the other hand, when the verification data Vfy_data and the input data DI are not the same, the verification comparator 175 may output a verify fail.

The control logic 180 performs various control operations for the data writing operation. In particular, during a write operation of the reset data, the control logic 180 controls the write pulse generator 190 to generate reset pulses P_RST for the plurality of write-write verify loops. At the same time, the control logic 180 controls the verify sense amplifier 150 to perform a verify operation on the data written in synchronization with the reset pulses P_RST. That is, when writing reset data, the control logic 180 controls the write pulse generator 190 to generate step pulses for forming a plurality of loops. In order to write the reset data within the Max loop, the control logic 180 includes a loop counter 185 for counting the number of loops. In the write loop of the reset data, if the control logic 180 determines that the verify fail of the result of one write loop, then the write pulse to rewrite the reset data using the increased reset write current in the subsequent write loop. Generator 190 is controlled. The control logic 180 generates control signals nPAS and PMUX for activating a sensing operation of the verification sense amplifier 150 in synchronization with one write pulse. In the write operation of the reset data, the control logic 180 performs write-write verification until the verification result is provided in the verify pass or until the count value of the number of loops reaches the maximum loop. You will iterate through the (Write-Write verify) loop.

The write pulse generator 190 generates a set pulse P_SET or a reset pulse P_RST under the control of the control logic 180 and provides it to the write driver 140. In addition, the write pulse generator 190 provides the write driver 140 with the bias signals DCBL_SET and DCBL_RST for controlling the levels of the write currents I_SET and I_RST under the control of the control logic 180. The write pulse generator 190 generates a reset pulse P_RST and a reset bias signal DCBL_RST to generate a reset write current I_RST having a gradually increasing level during a write operation of the reset data under the control of the control logic 180. ) The write pulse generator 190 may provide one reset pulse P_RST in one set pulse P_SET period. Alternatively, the write pulse generator 190 may generate a plurality of reset pulses P_RST during one set pulse P_SET period. In this case, during a timing period corresponding to one period of the set write current I_SET, the reset write current I_RST may be provided to the memory cell as a plurality of gradually increasing pulses.

In the above configuration, the verification comparator 175, the control logic 180, and the write pulse generator 190 are collectively referred to as a controller that controls the write driver 140 and the verification sense amplifier 150 to perform the general write operation of the present invention. can do.

The phase change memory device 100 of the present invention is provided to a memory cell starting from a reset write current I_RST of a relatively low level when writing reset data. If the resistance value of the memory cell selected by the provided reset write current I_RST does not reach the target level, the reset reset current I_RST is supplied again. The write loop of the reset data is repeated until the resistance of the selected memory cell reaches the target level. Therefore, it is possible to effectively suppress the occurrence of set-stuck failure due to excessive write current through the supply of the reset write current I_RST starting gradually at the initial low level.

FIG. 7 is a block diagram illustrating a simplified configuration of the write pulse generator 190 of FIG. 6. Referring to FIG. 7, the write pulse generator 190 generates a set pulse P_SET or a reset pulse P_RST under the control of the control logic 180. In addition, the write pulse generator 190 generates bias signals DCBL_SET and DCBL_RST for controlling the level of the write current under the control of the control logic 180.

The set bias driver 191 generates a set bias signal DCBL_SET that determines a waveform of the set write current I_SET. In general, the size and waveform of the set write current I_SET are determined according to the set bias signal DCBL_SET. The phase change material of the memory cell is changed to a crystal phase by the set write current I_SET. Therefore, the waveform of the set bias signal DCBL_SET has a shape similar to or the same as the set write current I_SET applied to the memory cell.

The reset bias driver 192 generates a reset bias signal DCBL_RST for generating a reset write current I_RST according to the present invention. The reset bias driver 192 generates a reset bias signal DCBL_RST in synchronization with the reset pulse P_RST generated by the pulse driver 193. The reset write signal I_RST, which increases with the number of loops, will be generated by the reset bias signal DCBL_RST.

The pulse driver 193 generates a set pulse P_SET and a reset pulse P_RST and provides them to the write driver 140. The pulse driver 193 may generate the reset pulse P_RST to have the same period as the set pulse P_SET. Alternatively, the pulse driver 193 may generate a reset pulse P_RST having a plurality of periods during one period of the set pulse P_SET. The pulse width of one set pulse P_SET is generally longer than the pulse width of the reset pulse P_RST. Therefore, when a plurality of cycles of the reset pulse (P_RST) occurs during one period of the set pulse (P_SET), it is possible to prevent a decrease in the write speed due to the repetition of the write-write verify loop for the reset data Can be.

According to the write pulse generator 190 including the above configuration, it is possible to generate a reset write current I_RST of a gradually increasing level. The write pulse generator 190 may control the write driver 140 to generate the reset write current I_RST of one period during one period of the set write current I_SET. Alternatively, the write pulse generator 190 may control the write driver 140 to generate the reset write current I_RST of a plurality of periods during one period of the set write current I_SET. Here, the write pulse generator 190 may provide the reset bias signal DCBL_RST such that the reset write current I_RST is provided at a value lower than the normal reset write current in the first loop. In addition, the write pulse generator 190 may provide the reset bias signal DCBL_RST such that the reset write current I_RST is provided as a stepping current pulse that gradually increases as the number of loops increases.

8 is a circuit diagram illustrating an example of the write driver 140 shown in FIG. 6. Referring to FIG. 8, the write driver 140 includes a pulse selection circuit 141, a current control circuit 142, and a current driving circuit 143. The pulse selection circuit 141 selects one of the set pulse P_SET and the reset pulse P_RST based on the input data DI. By the selected pulse, the current control circuit 142 activates the set bias signal DCBL_SET or the reset bias signal DCBL_RST, and controls the output current level of the current driving circuit 143. The pulse select circuit 141 includes first and second transfer gates TG1 and TG2 and first to second inverters INV1 to INV2. The current control circuit 142 includes first to seventh transistors TR1 to TR7. Here, the first to fifth transistors TR1 to TR5 are NMOS transistors, and the sixth and seventh transistors TR6 and TR7 are PMOS transistors. The current driving circuit 143 includes a pull up transistor PUTR and a pull down transistor PDTR.

First, the case where the write data DI is '0' will be described. When the write data DI is '0', the first transfer gate TG1 of the pulse select circuit 141 is turned on and the second transfer gate TG2 is turned off. The output of the second logic gate G2 is fixed to a logic '0' by the write data '0', and the fourth transistor TR4 is turned off. The second transistor TR2 is switched by the set pulse P_SET provided through the first logic gate G1. Therefore, the current magnitudes of the first and second transistors are controlled by the set bias signal DCBL_SET synchronized with the set pulse P_SET. Therefore, the fifth transistor TR5 is turned on by the set pulse P_SET, and the seventh transistor TR7 and the pull-down transistor PDTR are turned off. At this time, due to the current mirror effect, current flowing through the transistors TR6, TR1, TR2, and TR5 forming the first current path flows through the pull-up transistor PUTR. The current flowing through the pull-up transistor PUTR is provided to the data line DL as the set write current I_SET.

Next, the case where the write data DI is '1' will be described. When the write data DI is '1', the second transfer gate TG2 of the pulse select circuit 141 is turned on and the first transfer gate TG1 is turned off. The second transistor TR2 of the current control circuit 142 is turned off. The fifth transistor TR5 is turned on by the reset pulse P_RST, and the seventh transistor TR7 and the pull-down transistor PDTR are turned off. At this time, the current flowing through the transistors TR6, TR3, TR4, and TR5 forming the second current path flows through the pull-up transistor PUTR by the current mirror effect. The current flowing through the pull-up transistor PUTR is the reset write current I_RST, which is provided to the data line DL. The reset bias signal DCBL_RST for controlling the reset current has a value higher than that of the set bias signal DCBL_SET, and therefore, the reset write current I_RST has a larger value than the set write current I_SET. On the other hand, the reset pulse P_RST has a pulse width smaller than that of the set pulse P_SET. Therefore, the reset write current I_RST has a larger current value than the set write current I_SET and has a small pulse width. The selected memory cell is changed into a reset state or a set state by the reset write current I_RST or the set write current I_SET, respectively.

Here, the write driver 140 illustrated in FIG. 8 responds to the bias signals DCBL_SET and DCBL_RST and the pulses P_SET and P_RST provided from the write pulse generator 190 to the write currents I_SET and I_RST of the present invention. It is merely an example circuit for generating However, this form is merely exemplary, and as mentioned, it is apparent to those skilled in the art that the functions provided by the write driver 140 of the present invention can be achieved through various design modifications.

9 is a circuit diagram exemplarily illustrating the verification sense amplifier 150 shown in FIG. 6. Referring to FIG. 9, the verify sense amplifier 150 includes a sensing circuit 151 and a latch circuit 152.

The sensing circuit 151 includes a differential amplifier 1511 and an equalizer 1512. The sensing circuit 151 includes first to third PMOS transistors P1 to P3 and first to fifth NMOS transistors N1 to N5. The differential amplifier 1511 receives the boosted voltage VSA in response to the sensing enable signal nPSA, and senses and amplifies a difference between the sensing line voltage VSL and the reference voltage Vref. Meanwhile, the equalizer 1512 equalizes the output nodes Na and Nb of the differential amplifier 1511 in response to the sensing enable signal nPSA. The operating principle of the differential amplifier 1511 and equalizer 1512 is well known to those skilled in the art, and thus detailed description thereof will be omitted.

The latch circuit 152 outputs sensing data in response to the latch enable signal PMUX. The latch circuit 152 includes an inverting portion 1521 and a latching portion 1522. The inverter 1521 includes sixth and seventh PMOS transistors P6 and P7, sixth and seventh NMOS transistors N6 and N7, and a first inverter IN1. When the latch enable signal PMUX is at a high level, the inverter 1521 inverts the voltage of the output node Na of the sensing circuit 151. The latch unit 1522 includes second and third inverters IN2 and IN3 and latches output data. The latched data is then provided as verification data Vfy_data. The latch enable signal PMUX is provided from the control logic 180 as described above.

In FIG. 6, the verification sense amplifier 150 and the sense amplifier 160 are illustrated in separate configurations, but the function of the verification sense amplifier 150 may be achieved through the sense amplifier 160. It is self-evident to those who have acquired knowledge.

10 is a flowchart showing the writing method of the present invention in more detail. Referring to FIG. 10, a procedure for performing a write-write verify loop performed during a write operation of reset data may be described in detail. For a detailed operation description, the write operation will be described with reference to the configurations of FIG. 6.

When a data write command is applied, the phase change memory device 100 receives write data (S110). The input write data is stored in the input / output data buffer 170 and provided to the write driver 140 for a write operation. The write data loaded in the write driver 140 branches to another operation procedure depending on whether the reset data is set data or the set data (S120).

If the write data is set data, a data write operation in which a write verify operation is not performed is performed (S190). On the other hand, when the write data is reset data, the write operation of the reset data including the write verify operation is performed. Initialization of the write loop (j = 0) is performed to provide a stepping reset current having a level that sequentially increases starting from a level lower than the normal reset write current (S130). Subsequently, a verify operation for confirming data of the selected memory cell is performed. When the reset data is already written as a result of the verify operation, the entire write operation will be terminated. On the other hand, if the verification operation result determines that the reset data is not written, the procedure moves to the step for executing the write-write verify loop of the reset data of the present invention (S135). The write-write verify loop of the present invention starts with an operation of applying a reset write current corresponding to the loop number j to the selected memory cell (S140). In operation S150, a verification read operation is performed to determine whether the resistance of the selected memory cell reaches the target level. As a result of the verify read operation, when it is determined that the resistance of the selected memory cell has reached the target level, the write operation of all reset data is terminated. However, if it is determined that the resistance value of the selected memory cell does not reach the target level as a result of the verify read, the procedure moves to the steps for providing the reset write current I_RST and writing the reset data again (S160). Even if the resistance of the selected memory cell does not reach the target level, the write-write verify loop cannot be repeated indefinitely. Thus, determining whether the current loop has reached a predetermined maximum loop to limit the number of maximum write verify loops is included. If the current number of loops is equal to the maximum number of loops, the write operation of the reset data is stopped and it is determined that the write has failed. However, if the current number of loops is smaller than the maximum number of loops, the process proceeds to the step of counting up the current number of loops (S170). The loop counter 185 included in the control logic 180 adds 1 to the current loop number to provide a reset write current of an increased level than the reset write current applied in the current loop (S180). The procedure then returns to the write step S140 for supplying the reset write current I_RST of the level corresponding to the increased number of loops to the selected memory cell.

According to the write method of the present invention described above, the number of times of applying the reset write current and the level of the reset write current applied to the phase change memory cell can be minimized. Therefore, deterioration of endurance due to the reset write current can be effectively suppressed.

11 is a timing diagram showing the first embodiment of the method for writing the reset data of the present invention. Referring to FIG. 11, the waveforms of the signals for the case where the set data and the reset data are written to the selected memory cell are shown.

First, when set data is written, the write pulse generator 190 provides the set pulse P_SET, the reset pulse P_RST, and the set bias signal DCBL_SET to the write driver 140. The write driver 140 selects the set pulse P_SET in response to the set data and supplies the set write current I_SET synchronized with the set pulse P_SET to the selected memory cell as shown. At this time, the write verify operation through the verify sense amplifier 150 is inactivated.

When the reset data is written, the write pulse generator 190 provides the set pulse P_SET, the reset pulse P_RST, and the reset bias signal DCBL_RST to the write driver 140. The reset bias signal DCBL_RST synchronized with the reset pulse P_RST is activated by the reset data input to the write driver 140. In addition, the reset write current I_RST is provided at an increased level in the next loop of the loop determined to fail as a result of the write verification. This write-write verify loop continues until the resistance of the selected memory cell has reached the target level by the write verify operation within a maximum loop (ie, determined as a pass). do.

In the first embodiment, during the period in which one set pulse P_SET is provided, the reset data is set to be written to the selected memory cell in such a manner that one reset pulse P_RST is provided. However, as the write operation of the reset data is repeated in the first embodiment, the time required for the write operation may increase and a decrease in the write speed may occur. Solving this problem is the second embodiment of the present invention, which will be described in detail later in FIG.

12 is a timing diagram for explaining a second embodiment of the present invention. Referring to FIG. 12, the waveforms of the signals for each of the cases where set data and reset data are written to one selected memory cell are illustrated.

First, when set data is written, the write pulse generator 190 provides the set pulse P_SET and the reset pulse P_RST to the write driver 140. However, a reset pulse P_RST of a period different from the pulse period shown in FIG. 11 is provided. That is, in the second embodiment, a plurality of periods of reset pulses P_RST are provided during the period of one set pulse P_SET. The pulse width ΔT _R of the reset pulse P_RST is relatively narrow compared to the pulse width ΔT _S of the set pulse P_SET. The write driver 140 selects the set pulse P_SET in response to the set data and supplies the set write current I_SET synchronized with the set pulse P_SET to the selected memory cell as shown. At this time, the write verify operation through the verify sense amplifier 150 is inactivated.

When the reset data is written, the write pulse generator 190 provides the set pulse P_SET, the reset pulse P_RST, and the reset bias signal DCBL_RST to the write driver 140. The pulse width ΔT _R of the reset pulse P_RST is relatively narrow compared to the pulse width ΔT _S of the set pulse P_SET. Therefore, during one period of the set write current I_SET, the reset write current I_RST of a plurality of cycles may be supplied. The reset bias signal DCBL_RST gradually increases as the number of loops increases. Therefore, the reset write current I_RST of the current loop is increased by the step current ΔI compared to the reset write current I_RST of the previous loop. As each reset write current I_RST pulse is supplied, the sensing enable signal nPAS is activated, and a write verify operation is performed. The write-write verify loop described above continues until it is determined that the resistance of the selected memory cell has reached the target level (ie, passes) within the maximum loop. .

In the second embodiment, during the period in which one set pulse P_SET is provided, the reset data is set to be written to the selected memory cell in such a manner that the reset pulse P_RST having a plurality of periods is provided. Then, the level of the reset write current I_RST provided is set to increase gradually starting from a low level. Therefore, during the write operation of the reset data, a decrease in the write speed does not occur despite the execution of a plurality of write-write verify loops.

13 is a graph briefly showing the effect of the write operation of the present invention. Referring to FIG. 13, it is possible to confirm a significantly increased endurance according to a write-write verify operation of reset data according to the present invention. When the write-write verify operation is not performed on the reset data, the change of the reset resistance indicating the endurance characteristic may be represented by a curve 210. After more than 10 ⁷ writes, the size of the reset resistor begins to decrease. However, according to the write-write verify operation for the reset data of the present invention, the change in the magnitude of the reset resistor may be represented by the curve 220. According to the write method of the present invention, since the reset write current is provided smaller than the curve 210, the reset resistor of the memory cell which is caused by the write pass has a value slightly smaller than the resistance value R2 defining the reset state. Is over. Further, the write count of the reset data in more than 10 ⁸ times, the characteristics of the formed reset resistance is maintained to some extent.

Therefore, the endurance of the memory cell can be significantly increased through the write-write verify operation of the reset data of the present invention.

14 is a block diagram of a portable electronic system 300 showing an application example of a phase change memory device according to another embodiment of the present invention. The phase change memory device 310 connected with the microprocessor 330 via the bus line L3 is provided as a main memory of the portable electronic system. The power supply unit 320 supplies power to the microprocessor 330, the input / output device 340, and the phase change memory device 310 through the power line L4. The microprocessor 330 and the input / output device 340 may be provided as a memory controller for controlling the phase change memory device 310.

When the received data is provided to the input / output device 340 through the line L1, the microprocessor 330 receives and processes the received data through the line L2 and then processes the phase change memory through the bus line L3. Applies the received or processed data to the device 310. The phase change memory device 310 stores data applied through the bus line L3 in a memory cell. In addition, the data stored in the memory cell is read by the microprocessor 330 and output to the outside through the input / output device 340.

Even when the power of the power supply 320 is not supplied to the power line L4, the data stored in the memory cell of the phase change memory device 310 does not disappear due to the characteristics of the phase change material. This is because the phase change memory device 310 is a nonvolatile memory unlike a DRAM. In addition, the phase change memory device 310 has an advantage of faster operating speed and lower power consumption than other memory devices.

The phase change memory device according to the present invention may be mounted using various types of packages. For example, the phase change memory device according to the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP). ), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC) , Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed It can be implemented using packages such as Stack Package (WSP), and the like.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a circuit diagram schematically showing the structure of a variable resistance memory cell;

2 is a circuit diagram schematically showing another structure of a variable resistance memory cell;

3 shows a cross section of a variable resistance memory cell;

4 is a graph briefly showing a set-stuck failure phenomenon;

5 is a flow chart briefly showing the writing method of the present invention;

6 is a block diagram showing the structure of a variable resistance memory device of the present invention;

7 is a block diagram showing the configuration of the write pulse generator of FIG. 6;

8 is a circuit diagram showing the structure of the write driver of FIG. 6;

9 is a circuit diagram showing the structure of the verify sense amplifier of FIG.

10 is a flowchart showing the detailed operation of the writing method of the present invention;

11 is a timing diagram showing a first embodiment of the writing method according to the present invention;

12 is a timing diagram showing a second embodiment of the writing method according to the present invention;

13 is a graph showing the effect of the present invention; And

FIG. 14 is a block diagram schematically illustrating a configuration of a memory system including a variable resistance memory device of the present invention. FIG.

* Description of the symbols for the main parts of the drawings *

10, 20, 30: phase change memory cells

11, 21, 32: variable resistor

12, 22: selection element 31: upper electrode

33: contact plug 34: lower electrode

110: cell array 120: address decoder

130: column decoder 140: write driver

150: verification sense amplifier 160: sense amplifier

170: data input / output buffer 175: verification comparator

180: control logic 185: loop counter

190: write pulse generator 191, 192: bias driver

193: pulse driver 310: phase change memory device

320: power supply unit 330: microprocessor

340: input and output circuit

Claims (38)

In the data writing method of a variable resistance memory device: (a) providing a write current to the selected memory cell; And and (b) performing a write verify operation according to the type of the write current. The method of claim 1, The write current includes a set write current and a reset write current, and wherein the write verify operation is performed when the reset write current is provided. The method of claim 2, And if the set write current is provided to the selected memory cell, the write verify operation is not performed. The method of claim 1, In the case of performing the write verify operation, repeating steps (a) and (b) until the resistance of the selected memory cell reaches a target resistance value. The method of claim 4, wherein When the steps (a) and (b) are repeated, the magnitude of the write current increases sequentially. In the method of writing a variable resistance memory device: (a) applying a first reset write current to the selected memory cell; (b) performing a write verify operation on the selected memory cell; And and (c) applying a second reset write current to the selected memory cell according to a result of the write verify operation. The method of claim 6, And determining whether data to be written to the selected memory cell is reset data. The method of claim 7, wherein And write data for the selected memory cell is performed before the step (a). The method of claim 8, And the write operation is terminated when the data to be written and the data read from the selected memory cell are the same as a result of the write verify operation performed before the step (a). The method of claim 7, wherein And when data to be written to the selected memory cell is set data, a write verification operation on the set data is not performed. The method of claim 6, And the second reset current is greater than the first reset current. The method of claim 7, wherein (B) and (c) comprise a write loop, wherein the write loop is repeated until the resistance of the selected memory cell reaches a target level. The method of claim 12, And when the write loop is repeated, the level of the second reset write current increases sequentially. The method of claim 6, And the selected memory cell is a phase change memory cell. A memory cell array having a plurality of memory cells; A write driver for providing a write current to the selected memory cell; A sense amplifier for reading data of the selected memory cell; And And a controller for controlling the write driver to perform a write operation on the selected memory cell. And the control unit controls the sense amplifier to perform a write verify operation on the selected memory cell according to the type of the write current. The method of claim 15, The write current may include a reset write current for writing reset data and a set write current for writing set data. The method of claim 16, And the reset write current is discontinuous current pulses having at least two different levels. The method of claim 17, And the discontinuous current pulses are sequentially provided until the resistance of the selected memory cell reaches a target level. The method of claim 18, And the control unit controls the sense amplifier to perform a verify read operation on the selected memory cell in response to the application of each of the discontinuous current pulses. The method of claim 17, And the non-continuous current pulses are step pulses having sequentially increasing levels. The method of claim 15, The control unit: A verification comparator for comparing whether the sensed data from the sense amplifier with the write data written to the selected memory cell detects whether the resistance of the selected memory cell has reached a target level; Control logic for counting the number of writes according to the detection result and enabling rewriting of the selected memory cell; And And a write pulse generator configured to control the write driver to supply a set write current or a reset write current according to the write data according to the control of the control logic. The method of claim 21, The write pulse generator provides a set pulse and a set bias signal to the write driver to generate a reset pulse and a reset bias signal to generate a reset write current for writing the reset data, and a set write current to write the set data. Variable resistance memory device. The method of claim 22, And the reset pulse and reset bias signal are provided to the write driver such that the reset write current is generated as a plurality of discontinuous step pulses whose levels increase sequentially. The method of claim 22, And one period of the set pulse corresponds to one period of the reset pulse. The method of claim 22, And one period of the set pulse corresponds to two or more periods of the reset pulse. The method of claim 25, And the control logic activates the sense amplifier to sense the selected memory cell following the provision of each of the reset pulses. The method of claim 15, And each of the plurality of memory cells is a phase change memory cell. The method of claim 27, The phase change memory cell, A variable resistor having a resistance value different in magnitude depending on the type of the write current; And And a selection element for switching to be selected in response to a selection signal provided through a word line. The method of claim 28, The variable resistor is formed of Chalcogenide alloys (Chalcogenide alloys). A memory cell array having a plurality of memory cells; Sense amplifiers for reading data stored in selected memory cells; A write driver for writing write data to the selected memory cell; And A control unit for controlling the sense amplifier and the write driver, And the control unit controls the sense amplifier to perform a write verify operation on the selected memory cell according to the type of the write data. The method of claim 30, And the control unit controls the sense amplifier to perform the write verify operation when the write data is reset data. The method of claim 31, wherein And the controller performs the write verify operation before writing the reset data to the selected memory cell when the write data is reset data. The method of claim 32, And if it is determined that a result of a write verify operation performed before the write is a verify pass, the controller terminates the write operation of the reset data. The method of claim 31, wherein The control unit controls the write driver and the sense amplifier to provide a plurality of write current pulses for writing the reset data and to perform the write verify operation whenever each of the plurality of write current pulses is provided. Memory device. The method of claim 34, wherein And the write current pulses have different sizes. 36. The method of claim 35 wherein And the write current pulses are sequentially increasing in magnitude. The method of claim 30, And the controller controls the sense amplifier to not perform the write verify operation when the write data is set data. Variable resistance memory device; And A memory controller for controlling the variable resistance memory device, The variable resistance memory device, A memory cell array having a plurality of memory cells; A write driver for providing a write current to the selected memory cell; A sense amplifier for reading data of a memory cell provided with the write current; And And a controller configured to control the write driver and the sense amplifier to perform a write operation and a write verify operation on the selected memory cell. The controller performs the write verify operation according to the type of the write current.

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