CN105304129B - Resistance-variable type memory and its wiring method - Google Patents
Resistance-variable type memory and its wiring method Download PDFInfo
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- CN105304129B CN105304129B CN201410352443.7A CN201410352443A CN105304129B CN 105304129 B CN105304129 B CN 105304129B CN 201410352443 A CN201410352443 A CN 201410352443A CN 105304129 B CN105304129 B CN 105304129B
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Abstract
The present invention provides the resistance-variable type memory and its wiring method of a kind of setting for being able to carry out high reliablity and the write-in reseted.Resistance-variable type memory of the invention includes: memory array, comprising invertibity and non-volatile variable resistor element and selection are connected in series in memory element made of between bit line (BL) and source electrode line (SL) with transistor；Row selector selects the selection transistor of line direction；Column selection portion selects the variable resistor element of column direction；And control unit, control the write-in of variable resistor element.Control unit applies the bias voltage for being used to reset variable resistor element to selected bit line and source electrode line, and applies the pulse that voltage gradually increases to the grid of selected selection transistor.Prevent the superfluous electric current that circulates in the variable resistor element through reseting.By inhibiting the excess current of the variable resistor element through reseting, the speed of variable resistor element deterioration can inhibit, and become easy the setting of variable resistor element.
Description
Technical field
The present invention is about a kind of resistance-variable type memory (variable resistance using variable resistor element
Memory), especially with respect to the write-in of a kind of resistance-variable type memory reseted (reset) and (set) is arranged.
Background technique
Nonvolatile memory has the advantages that the data of deposit will not disappear after a loss of power, therefore is that many electric appliances produce
Product maintain memory element essential to normal operating.Currently, resistance-variable type memory is that one kind that industry actively develops is non-easily
The property lost memory, write-in low with write operation voltage is erased, and the time is short, memory time is long, non-destructive is read, multimode
Memory, the advantages that structure is simple and required area is small, the great application potential on the following personal computer and electronic equipment.
Fig. 1 is to indicate that the typical of memory array (memory array) of previous resistance-variable type memory is constituted
Circuit diagram.One memory element includes variable resistor element and the selection transistor with variable resistor element series connection.m
× n (m, n are more than or equal to 1 integer) a memory element is formed as two-dimensional array shape, and wordline (word line) WL is connected to choosing
The grid (gate) with transistor is selected, a wherein electrode for selection transistor is connected to a wherein electricity for variable resistor element
Pole, another electrode are connected to source electrode line (source line) SL.Another electrode of variable resistor element is connected to bit line (bit
line)BL。
Variable resistor element includes the film an of metal oxide (such as hafnium oxide (HfOx)), can be according to being applied
Resistance value is set as low resistance state or high resistance state by the size and polarity of pulse voltage reversible and non-volatilely.It will can be changed
Resistive element sets the case where (write-in) is high resistance state referred to as setting (SET), and sets (write-in) as low resistance state
Situation is known as reseting (RESET).
Memory element can be accessed by selection wordline WL, bit line BL and source electrode line SL with bit base.For example,
In the case where born of the same parents' unit (cell unit) M11 is written, can be turned the transistors on by wordline WL1, and to bit line
BL1, source electrode line SL1 apply and are arranged or reset corresponding voltage, and variable resistor element is set as being arranged or be reseted.And
In the case where the reading for carrying out born of the same parents' unit M11, it can be turned the transistors on by wordline WL1, and bit line BL1, source electrode line SL1 are applied
Add the voltage for reading, to show the setting with variable resistor element in bit line BL1 or reset corresponding voltage or electric current, and
The voltage or electric current are detected by sensing circuit.
[background technology document]
[patent document]
[patent document 1] Japanese Patent Laid-Open 2012-64286 bulletin
[patent document 2] Japanese Patent Laid-Open 2008-41704 bulletin
As initial setting, molding (forming) step must be generally carried out to variable resistor element.In general, molding
It is to compare electricity bigger when variable resistor element is written by applying to the metal-oxide film in variable resistor element
The sense of current that film is flowed through when pressing Vf and implement, also, applying voltage can determine the polarity for being arranged and reseting.Molding is general
It is to be carried out before the factory of resistance-variable type memory.
Molding an example is indicated in Fig. 2 (A).For example, applying 4V to bit line BL, 0V is applied as molding to source electrode line SL
Voltage applies the voltage 6V needed for selection is connected with transistor T to wordline WL.As a result, in variable resistor element R, electric current from
Bit line BL flows to source electrode line SL, and is formed.When molded, variable resistor element R is high resistance state.
When reseting variable resistor element R and being set as low resistance state, as shown in Fig. 2 (B), for example, applying to bit line BL
0V, applies 2V to source electrode line SL, applies 4V to wordline WL.As a result, in variable resistor element R, electric current is flowed to from source electrode line SL
Bit line BL, and variable resistor element R setting is reseted.When variable resistor element R is arranged, as shown in Fig. 2 (C), for example, contraposition
Line BL applies 2V, applies 0V to source electrode line SL, applies 4V to wordline WL.As a result, in variable resistor element R, electric current is from bit line
BL flows to source electrode line SL, and sets and be arranged to variable resistor element R.In this way, applying SL when reseting variable resistor element R
Bias (bias) voltage of > BL applies the bias voltage of SL < BL when variable resistor element R is arranged.
However, when reseting variable resistor element, that is to say, that when generating silk between the electrode in variable resistor element R
When shape conductive path, due to Filamentous conductive path not necessarily can stable and duplicate generation, through reseting variable resistance member
Part may generate the situation of tail bit (tail bit), also that is, the electric current that the variable resistor element is circulated when reseting is greater than
Normal variable resistor element.
Fig. 3 indicates the curve graph of the current distribution characteristic of the variable resistor element through reseting, curve difference shown in figure
Be include 7nm and 5nm metal oxide variable resistor element.Herein, it will circulate in the variable resistor element through reseting big
It is considered as tail bit in the point of the electric current of 1 μ A or more.In general, there are about 3 σ to belong to normal in the variable resistor element entirety through reseting
Variable resistor element, and then will appear the variable resistor element with tail bit in remaining about 0.3%.With tail ratio
In special variable resistor element, since the electric current of its circulation is larger, the deterioration of element can be made to become faster, easily cause failure.Into
And even if wanting to set up this variable resistor element, there is also can not be normally arranged using common bias voltage.
Thus, it is desirable to inhibit the generation of tail bit.
Summary of the invention
The present invention solves institute's above-mentioned conventional problem, its purpose is to provide a kind of setting for being able to carry out high reliablity and again
If write-in resistance-variable type memory.
Resistance-variable type memory of the invention includes: memory array, comprising by invertibity and non-volatile variable
Memory element made of resistive element and selection are connected in series between bit line and source electrode line with transistor；Row selector, selection
The selection transistor of line direction；Column selection portion selects the variable resistor element of column direction；And control unit, control variable resistance
The write-in of element；And the control unit applies the bias plasma for being used to reset variable resistor element to selected bit line and source electrode line
Pressure, and the pulse that voltage gradually increases is applied to the grid of the selection transistor selected by the row selector.
The preferably described pulse is the pulse of ramp waveform.The preferably described pulse is multiple pulses that voltage becomes larger
String.The preferably described control unit include examine the variable resistor element through reseting whether He Ge portion verifying (verify), to by
The proof department is determined as underproof variable resistor element and then applies the pulse.The preferably described proof department is with wordline
Unit executes the respective verifying of multiple variable resistor elements through reseting in selected wordline.The preferably described proof department with
Wordline is that unit executes multiple respective verifyings of variable resistor element reseted and be arranged in selected wordline.
Wiring method of the invention is carried out in the resistance-variable type memory comprising memory array, the memory
Array includes by invertibity and non-volatile variable resistor element and selection with transistor are connected in series in bit line and source electrode line
Between made of memory element, and apply the bias plasma for being used to reset variable resistor element to selected bit line and source electrode line
Pressure, and the pulse that voltage becomes larger is applied to the grid of selected selection transistor.
[The effect of invention]
According to the present invention, when reseting variable resistor element, voltage is applied to the grid of selection transistor and is become larger
Pulse, therefore, can inhibit electric current moment flows to variable resistor element, to prevent stream in the variable resistor element through reseting from passing through
Surplus electric current.By the excess current of variable resistor element of the inhibition through reseting, the speed of variable resistor element deterioration can inhibit,
And become easy the setting of variable resistor element.
Detailed description of the invention
Fig. 1 is the figure for indicating the array of well known resistance-variable type memory and constituting.
The example of bias voltage when Fig. 2 (A) is molding, Fig. 2 (B) is the example of bias voltage when reseting, Fig. 2 (C)
The example of bias voltage when being setting.
Fig. 3 is the curve graph for indicating to have an example of the variable resistor element of tail bit.
Fig. 4 is the block diagram for indicating the resistance-variable type memory of one embodiment of the invention.
Fig. 5 is the figure for indicating the composition of memory element of the present embodiment.
Fig. 6 (A) indicates the waveform for being applied to the pulse of the grid of selection transistor when reseting in the past, Fig. 6 (B), Fig. 6
(C) waveform of the pulse of the grid that selection transistor is applied to when reseting of the present embodiment is indicated.
Fig. 7 is each bias when reseting, be arranged and reading for indicating the resistance-variable type memory of the embodiment of the present invention
The table (table) of an example of voltage.
Fig. 8 (A), Fig. 8 (B) are the figures for indicating the voltage waveform example in each portion when reseting of the embodiment of the present invention.
The figure of the action waveforms example in each portion when Fig. 9 is the reading for indicating the embodiment of the present invention.
Figure 10 is the process (flow) for indicating verifying when reseting multiple variable resistor elements of the embodiment of the present invention.
The process of verifying when Figure 11 is the setting multiple variable resistor elements for indicating the embodiment of the present invention.
Figure 12 (A), Figure 12 (B) are the figures for indicating other configuration examples of memory element of the embodiment of the present invention.
Wherein, the reference numerals are as follows:
100: resistance-variable type memory
110: memory array
120: inputoutput buffer
130: address register
140: data register
150: controller
160: word line selection circuit
170: column select circuit
180: sensing circuit
190: voltage generation circuit
Ax: row address information
Ay: column address information
BL、BL1、BL2、……BLm、BLn、: bit line
M11, M12 ... M1n, M21, M22 ... M2n, Mm1, Mm2 ... Mmn: memory element
P1, P2, P3: pulse
R, R1, R2: variable resistor element
SL, SL1, SL2 ... SLn: source electrode line
T, T1, T2: transistor is used in selection
Tr: period
VBL, VSL: voltage
Vg: grid voltage
WL, WL1, WL2 ... WLn: wordline
Specific embodiment
Next, referring to attached drawing, detailed description of embodiments of the present invention.It should be noted that attached drawing be for ease of
Understand and is highlighted each portion, it is different from the ratio of actual device.
Fig. 4 is the block diagram for indicating the composition of resistance-variable type memory of one embodiment of the invention.The present embodiment
Resistance-variable type memory 100 is configured to include: memory array 110, in the rectangular multiple memory elements being arranged；It is defeated
Enter output buffer 120, is connected to external input output terminal I/O, and keep inputoutput data；Address register 130, connects
Receive the address date from inputoutput buffer 120；Data register 140 keeps the data of input and output；Controller 150,
Each portion is controlled based on order data from inputoutput buffer 120 etc.；Word line selection circuit 160 will be posted from address
The row address information Ax of storage 130 is decoded, and the selection and driving of wordline are carried out based on decoding result；Column select circuit 170, will
Column address information Ay decoding from address register 130, and selection and driving based on decoding result progress bit line；Sensing electricity
The signal read from the born of the same parents' unit selected by column select circuit 170 is detected, or keeps writing to selected born of the same parents' unit in road 180
The data entered；And voltage generation circuit 190, it generates the setting of variable resistor element, reset, bias plasma needed for reading operation
Pressure, and the bias voltage is provided to word line selection circuit 160 and sensing circuit 180 etc..
As shown in Figure 1, memory array 110 include configure along the line of the column direction multiple memory element M11, M12 ...
Mmn, a memory element include that transistor is used in a variable resistor element and a selection.Variable resistor element and selection crystalline substance
Body pipe is connected in series between bit line BL and source electrode line SL, and the grid of selection transistor is connected to wordline.
The state that variable resistor element is set corresponds to any of data " 0 " or " 1 ", and variable resistor element is through weight
If state correspond to data " 0 " or " 1 " in another.Based on from external order, control write-in (is set controller 150
Set, reset) or reading operation etc..Word line selection circuit 160 selects wordline, column based on the row address information Ax being received externally
Selection circuit 170 selects bit line based on the column address information Ay being received externally.By the control of controller 150, to selected
Wordline, bit line and the source electrode line selected apply bias voltage corresponding with write-in (be arranged, reset) and reading.
The connection relationship of memory element and sensing circuit 180 is indicated in Fig. 5.One memory element includes to be connected in series in
Variable resistor element R and selection transistor T between source electrode line SL and bit line BL, and select shared with the grid of transistor T
Ground is connected to wordline WL.The memory element of n-bit is arranged along line direction in the example shown in FIG. 5, and the storage member of n-bit
Bit line BL1~bit line BLn of part is connected to sensing circuit 180.When carrying out the reading of selected memory element, sensing is utilized
The voltage or electric current that the detection of circuit 180 shows in the bit line of selected memory element.In addition, working as to selected memory element
When being written, by the write-in data transmission inputted from inputoutput buffer 120 to sensing circuit 180, sensing circuit 180 makes
Selected bit line BL or source electrode line SL are resulted from being arranged or reseting corresponding voltage to be written.
Next, the write-in (reset, be arranged) of opposite variable resistor element is illustrated.Controller 150 is responded from outside
Order etc. that input and output terminal obtains and start to be written, to control the movement in each portion.To word line selection circuit 160 provide from
The row address information Ax that inputoutput buffer 120 obtains provides column address information Ay to column select circuit 170.In addition, write-in
Data are kept via data register 140 by sensing circuit 180.In turn, voltage generation circuit 190 is according to from controller
150 instruction supplies voltage needed for write-in to word line selection circuit 160 or sensing circuit 180 etc..Sensing circuit 180 is right
Decoding result based on column select circuit 170 and the bit line BL and source electrode line SL that select are for giving data " 0 " or " 1 " corresponding electricity
Pressure.
In the present embodiment, when reseting variable resistor element R, with do not make electric current sharp flow to variable resistor element R,
That is the mode for making electric current slowly flow to variable resistor element R is controlled.If electric current sharp flow to variable resistance
Element R, that is to say, that if once applying big energy (energy), the Filamentous conductive path meeting of variable resistor element
Moment largely grows up, the electric current for thus causing circulation superfluous, and is easy to generate tail bit.Therefore, in the present embodiment, in order not to
So that big electric current moment is flow to variable resistor element R, and carries out dropping selection gradually with the impedance (impedance) of transistor T
Low control.
In a preferred embodiment, it is that voltage VSL is applied to source electrode line SL, voltage VBL (VSL > is applied to bit line BL
VBL), and to selection with the grid of transistor T apply the pulse become larger such as voltage from 0V.Fig. 6 (A) is in the past when reseting
It is applied to the waveform of the pulse P1 of the grid of selection transistor T, Fig. 6 (B) is that the present embodiment is applied to selection transistor T
Grid pulse P2 waveform.As shown in Fig. 6 (A), if rectangular-shaped pulse P1 to be applied to the grid of selection transistor T
Pole, then selection transistor T meeting transient switching, big electric current sharp flow to variable resistor element R from source electrode line SL.By
This, forms Filamentous conductive path with a high current density, to be easy to generate tail bit between electrode.In contrast, if will be as
The pulse P2 of slope (ramp) shape as shown in Fig. 6 (B) is applied to the grid of selection transistor T, then crystal is used in selection
The conductance (conductance) of pipe T can be become larger in the mode proportional to the voltage of pulse P2, thus to variable resistance member
The drain current of part R supply becomes larger.Therefore, a large amount of electric current moment can not be made to flow to variable resistor element R, and gradually increased
It is provided to the electric current of variable resistor element R, greatly to inhibit the generation of tail bit.
In addition, in another preferred embodiment of the present embodiment, it can also be as shown in Fig. 6 (C) by multiple pulses
String P3 is applied to the grid of selection transistor T.Multiple train of pulse P3 include the multiple pulses become larger such as voltage.By this
In the case that a series of train of pulse P3 of kind is applied to selection transistor, supply to the energy of the electric current of variable resistor element R
Also it can gradually increase, therefore, can inhibit the high Filamentous conductive path of moment formation density.
Next, by the setting of the variable resistor element of the present embodiment, reset and read when specific bias voltage one
Embodiment is shown in FIG. 7, and the example of action waveforms when reseting variable resistor element is indicated in Fig. 8 (A), Fig. 8 (B).
When reseting variable resistor element, as shown in Fig. 7, Fig. 8 (A), the bit line BL of selected memory element is applied
VBL=-0.5V applies VSL=2.6V to source electrode line SL.Then, Tr during about 100ns, such as the ramp pulse of Fig. 6 (B)
Apply the grid voltage (Vg=0V → 4V) that 4V is changed to from 0V to selected wordline as shown in P2.As a result, can power transformation
In resistance element R, electric current flows to bit line BL from source electrode line SL, and carries out the write-in of low resistance state reseted.In addition, using such as
In the case where multiple train of pulse P3 as shown in Fig. 6 (C), as shown in Fig. 8 (B), Tr applies voltage gradually during about 100ns
The multiple train of pulse P3 to become larger.
On the other hand, when variable resistor element is arranged, firstly, the bit line BL to selected memory element applies VBL
=2.4V applies VSL=0V to source electrode line SL.Then, apply the grid voltage (Vg=2.3V) of 2.3V to selected wordline
Pulse.Electric current flows to source electrode line SL from bit line BL as a result, and sets high resistance state for variable resistor element R.
Next, being illustrated to the reading operation of born of the same parents' unit of the resistance-variable type memory of the present embodiment.Controller
150 respond order from external input output terminal etc. and start reading out, to control the movement in each portion.Then, receive from
The address date that inputoutput buffer 120 obtains provides row address information Ax to word line selection circuit 160, to column selection electricity
Road 170 provides column address information Ay.
The example of the waveform in each portion in Fig. 9 when expression reading operation.Sensing circuit 180 is to based on column select circuit
170 decoding result and the bit line BL of memory element selected applies VBL=0.2V, VSL=0V is applied to source electrode line SL.It is preferred that
For bit line BL is pre-charged (precharge) to 0.2V.If keeping the potential difference between bit line BL and source electrode line SL excessive, greatly
Electric current can flow to variable resistor element.Therefore, potential difference is preferably small as far as possible, that is to say, that potential difference is that can pass through sense
Slowdown monitoring circuit 180 detects the size of its variation.Then, word line selection circuit 160 is selected based on row address information Ax
Wordline apply 3V grid voltage (Vg=3V).When variable resistor element R is setting, sensing circuit 180 is almost detected not
To the electric current for flowing to source electrode line SL from bit line BL.On the other hand, when variable resistor element R is to reset, sensing circuit 180 then can
Detect the electric current that source electrode line SL is flow to from bit line BL.
Next, being illustrated to the preferred embodiment of the present invention.In a preferred embodiment, when to variable resistance
When element is written and (resets, is arranged), implement determine the variable resistor element whether He Ge write verification.Resistance-variable type
The reading or write-in for the memory element that memory can access memory element with bit base, and be accessed.Cause
This when being written to a memory element, can carry out write verification to the memory element in one embodiment.In addition,
In another embodiment, when multiple memory elements simultaneously or successively into a page (page) (wordline) are written
When (be arranged, reset), simultaneously or successively implement the respective verifying of multiple memory elements in the page.For example, when external defeated
When entering the data width that output terminal has × 16, and carrying out the write-in of data of 16 bits simultaneously, or when a page is
When 2K bit (byte), in the case where such as continuously carrying out the write-in of multiple data in the page, to being carried out write-in
The memory element of the page carries out write verification.
Figure 10 is the process of verifying when indicating to reset multiple variable resistor elements in the page, and Figure 11 is in the setting page
Multiple variable resistor elements when verifying process.For convenience, it is respectively indicated in Figure 10, Figure 11 and resets, is arranged
The process of verifying, but in fact, these can be implemented simultaneously when reseting and multiple variable resistor elements in a page being arranged
Verifying.
Figure 10 and Figure 11 is please referred to, based on the write-in data obtained from external input output terminal, to selected variable
Resistive element is reseted (S100) or setting (S200).It resets and the bias condition that is arranged is as shown in described Fig. 7, wherein grid
Pole tension Vg applies by way of being the train of pulse P3 shown in the ramp pulse P2 or Fig. 6 (C) as shown in Fig. 6 (B).When weight
If, setting at the end of, then carry out variable resistor element verifying (S102, S202).Reset and be arranged verifying when bias
Condition respectively with reading operation when it is identical.It is determined that whether each memory element carried out after the write-in in the page is qualified
(S104、S204)。
In the case where being judged to reseting qualification, the voltage of bit line BL is changed to VBL=2.6V (S106).Position as a result,
Line BL and source electrode line SL becomes same potential, and electric current will not be further continued for flowing to variable resistor element.On the other hand, it is being determined as not
In the case where qualification, bias condition identical with step S100 is maintained, and then apply ramp pulse P2 or train of pulse P3 again
(S108)。
In the case where being judged to that qualification is arranged, the voltage of bit line BL is changed to VBL=0V (S206).Bit line as a result,
BL and source electrode line SL becomes same potential, and electric current will not be further continued for flowing to variable resistor element.On the other hand, it is being judged to not conforming to
In the case where lattice, apply the voltage VBL=2.2V (S208) for being slightly below step S200 and being applied to bit line BL.So, right
All variable resistor elements being written in the page implement verifying.
According to the present embodiment, electric current is sharp supplied to the variable resistor element being reset by inhibiting, can be prevented moment
The high Filamentous conductive path of density is formed, excessive electric current is circulated in the variable resistor element through reseting to reduce and generates tail
Bit.Therefore, it can be easy to that the variable resistor element through reseting is arranged under common bias condition, thus allow for reliability
High write-in.In turn, by inhibiting the generation of tail bit, it can inhibit the failure of element, to extend the service life of element.
Although having carried out detailed narration to the preferred embodiment of the present invention, the present invention is not limited to specifically implement
Mode, those skilled in the art work as can carry out various modifications or change in the range recorded in claim.
It in the described embodiment, is to be illustrated with memory element as shown in Figure 5, that is, one end of variable resistor element R
It is the one end for being connected in series in selection transistor T, the other end of variable resistor element R is connected to bit line BL, and crystal is used in selection
The other end of pipe T is connected to source electrode line SL, however, the present invention is not limited thereto, it is can also be applied to depositing as shown in Figure 12 (A)
It stores up on element, that is, the other end of variable resistor element R is connected to source electrode line SL, and selection is connected to position with the other end of transistor T
Line BL.In addition, it is can also be applied to including two transistors T1, T2+, two variable resistor elements as shown in Figure 12 (B)
On complementary (Complementary) memory element of R1, R2.Wherein, complementary memory element be to variable resistor element R1,
Variable resistor element R2 remembers respectively and (is arranged, resets) complementary data, and to bit line BL, bit lineExport complementary data.
Claims (10)
1. a kind of resistance-variable type memory, characterized by comprising:
Memory array, comprising by invertibity and non-volatile variable resistor element and selection with transistor are connected in series in position
Memory element made of between line and source electrode line；
Row selector selects the selection transistor of line direction；
Column selection portion selects the variable resistor element of column direction；And
Control unit controls the write-in of variable resistor element；And
The control unit applies the first bias for being used to reset or be arranged variable resistor element to selected bit line and source electrode line
Voltage, and pulse is applied to the grid of the selection transistor selected by the row selector, wherein the control unit is to described
When variable resistor element is configured, the voltage to the pulse that the grid of the selection selected transistor is applied is gradually to increase
Add；And
The control unit include examine reseted and the variable resistor element that is arranged whether He Ge proof department, with to being determined as not
Qualified variable resistor element applies the pulse and the second bias voltage again,
Second bias voltage that wherein proof department applies the variable resistor element being set is less than the warp
First bias voltage that the variable resistor element of setting is applied when setting.
2. resistance-variable type memory as described in claim 1, in which:
The pulse is the pulse of ramp waveform.
3. resistance-variable type memory as described in claim 1, in which:
The pulse is multiple trains of pulse that voltage becomes larger.
4. resistance-variable type memory as described in claim 1, in which:
It is respective that the proof department executes multiple variable resistor elements through reseting in selected wordline as unit of wordline
Verifying.
5. resistance-variable type memory as described in claim 1, in which:
The proof department executes multiple variable resistor elements reseted and be arranged in selected wordline as unit of wordline
Respective verifying.
6. a kind of wiring method of memory array, the memory array includes by variable resistor element and selection transistor
Multiple memory elements made of being connected in series between bit line and source electrode line；Said write method is characterized in that:
The first bias voltage for being used to reset or be arranged variable resistor element is applied to selected bit line and source electrode line, and to institute
The grid of the selection transistor of selection applies pulse, wherein when being configured to the variable resistor element, to what is selected
The voltage for the pulse that the grid of selection transistor is applied gradually increases；And
Examine the variable resistor element being reseted and be arranged whether qualified, with to being determined as underproof variable resistor element again
Apply the pulse and the second bias voltage,
Wherein in the case where the variable resistor element being set is judged as underproof situation, to the variable resistance member being set
Second bias voltage that part applies is less than described first that the variable resistor element being set is applied when setting
Bias voltage.
7. wiring method as claimed in claim 6, in which:
The pulse is the pulse of ramp waveform.
8. wiring method as claimed in claim 6, in which:
The pulse is multiple trains of pulse that voltage becomes larger.
9. wiring method as claimed in claim 6, wherein examine the variable resistor element through reseting whether He Ge step
Before, further includes:
The respective verifying of multiple variable resistor elements through reseting in selected wordline is executed as unit of wordline.
10. wiring method as claimed in claim 6, wherein examine the variable resistor element through reseting whether He Ge step
Before, further includes:
Multiple respective verifyings of variable resistor element reseted and be arranged in selected wordline are executed as unit of wordline.
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| JP7150787B2 (en) * | 2020-07-31 | 2022-10-11 | ウィンボンド エレクトロニクス コーポレーション | Resistance variable crossbar array device |
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