TWI694446B - Non-volatile memory device and non-volatile memory device - Google Patents

Abstract

A non-volatile memory includes a first memory component and a second memory component. The first memory component is configured to receive a control voltage and an input voltage, and output a first current. The second memory component is coupled to the first memory component and configured to receive the control voltage and the input voltage, and output a second current. The first memory component and the second memory component are changed from a high resistance state to a low resistance state according to a setting operation, and are changed from a low resistance state to a high resistance state according to a reset operation. The first current is changed according to the first memory component is in the high resistance state or the low resistance state, the second current is changed according to the second memory component is in the high resistance state or the low resistance state.

Description

Non-volatile memory and non-volatile memory device

The present disclosure relates to a non-volatile memory and non-volatile memory device, in particular to a differential architecture of non-volatile memory and non-volatile memory device.

In recent years, with the development of portable electronic products, the research on memory has vigorously developed. Resistive random-access memory (RRAM) in memory has high storage density and superior reliability And other advantages, it is regarded as one of the most potential non-volatile memory.

Conventional Resistive Random Access Memory (RRAM) devices use an external circuit to provide a reference current to compare with the current generated by resistive random access memory to distinguish resistive random access memory The logic state stored in the body, the additional reference current source greatly increases the overall circuit area. In addition, under high temperature, the resistance state of the single-resistance random access memory device will move to the reference current with time, which is prone to data misjudgment and there are many reliability problems.

In an embodiment of the present disclosure, a non-volatile memory includes a first memory element and a second memory element. The first memory element is used to receive the control voltage and the input voltage and output the first current. The second memory element is coupled to the first memory element and used to receive the control voltage and the input voltage and output a second current. The first memory element and the second memory element change from a high resistance state to a low resistance state according to a setting operation, and from a low resistance state to a high resistance state according to a reset operation, and the first current is in a high resistance according to the first memory element State or low resistance state, the second current changes according to whether the second memory element is in a high resistance state or a low resistance state.

In another embodiment of the present disclosure, a non-volatile memory device includes a plurality of non-volatile memories and a sensing circuit. One of the non-volatile memories is used to generate the first current or the second current according to the control voltage and the input voltage. The sensing circuit is used to compare the first current or the second current to determine whether the non-volatile memory device is in a low logic state or a high logic state.

In summary, the non-volatile memory outputs the first current and the second current according to the control voltage and the input voltage, and is set to the high resistance state or the low resistance state according to the setting operation and the reset operation, the first current and the second current It changes according to the high resistance state or low resistance state of the memory device.

100‧‧‧ Non-volatile memory

110‧‧‧ Non-volatile memory device

110a, 110b‧‧‧ memory element

110c, 110d‧‧‧selected components

120‧‧‧sensing circuit

200‧‧‧ Non-volatile memory device

SL, SL1, SL2‧‧‧Data cable

WL, WL1, WL2 ‧‧‧ character line

BL, BL1, BL2, BLB, BLB1, BLB2 ‧‧‧ bit lines

HRS‧‧‧High resistance state

LRS‧‧‧Low resistance state

I _BL ‧‧‧ First current

I _BLB ‧‧‧second current

FIG. 1 is a circuit diagram of a non-volatile memory according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram of a low logic state and a high logic state of a non-volatile memory according to an embodiment of the present disclosure.

FIG. 3 is a circuit diagram of a non-volatile memory device according to an embodiment of the present disclosure.

The words "including", "having", etc. used in this article are all open terms, which means "including but not limited to". In addition, "and/or" as used in this article includes any one or more of the listed items and all combinations thereof.

In this article, when an element is called "connected" or "coupled", it can be referred to as "electrically connected" or "electrically coupled." "Link" or "Coupling" can also be used to indicate the operation or interaction of two or more components. In addition, although terms such as "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish elements or operations described in the same technical terms. Unless the context clearly dictates, the term does not specifically refer to or imply the order or order, nor is it intended to limit the present disclosure.

Please refer to FIG. 1, which illustrates a circuit diagram of a non-volatile memory 100 according to an embodiment of the present disclosure. The non-volatile memory 100 includes a non-volatile memory element 110 and a sensing circuit 120. The non-volatile memory device 110 includes a memory device 110a, a memory device 110b, a selection device 110c, and a selection device 110d. The non-volatile memory device 110 is The memory element 110a and the memory element 110b are connected in series. The memory element 110a and the memory element 110b share the character line WL and the data line SL to form a differential structure. In this embodiment, the memory element 110a and The memory element 110b may use the same memory element.

The selection element 110c is coupled to the memory element 110a, the selection element 110d is coupled to the memory element 110b, the selection element 110c and the selection element 110d are turned on in response to the control voltage, and the control voltage can be transmitted from the word line WL to the selection element 110c and the selection element 110d control terminal. In one embodiment, the selection element 110c and the selection element 110d may be implemented by transistors, which is not limited in this disclosure.

The sensing circuit 120 is used to compare the current output by the memory element 110a and the memory element 110b to determine whether the non-volatile memory 100 is in a low logic state (logic 0) or a high logic state (logic 1).

Please refer to FIG. 2, which illustrates a schematic diagram of a low logic state and a high logic state of the non-volatile memory 100 according to an embodiment of the present disclosure. The non-volatile memory 100 is a one-bit differential memory architecture composed of left and right memory elements in opposite resistance states. In other words, when one of the memory elements is in a low resistance state (LRS) ), the other memory device is in a high resistance state (HRS). For example, when the memory element 110a is a high-resistance HRS, the memory element 110b is a low-resistance LRS, as shown in the upper diagram of FIG. 2. When the memory element 110a is a low-resistance LRS, the memory element 110b is a high-resistance HRS, as shown in the lower diagram of FIG. 2.

The memory element 110a is used for receiving the control voltage and the input voltage and outputting the first current I _BL . The memory element 110b is coupled to the memory element 110a for receiving the control voltage and the input voltage and outputting the second current I _BLB . The memory device 110a and the memory device 110b change from the high-resistance HRS to the low-resistance LRS according to the setting operation, and change from the low-resistance LRS to the high-resistance HRS according to the reset operation. The first current I _{BL changes} according to the memory element 110 a being in the high resistance state HRS or the low resistance state LRS, and the second current I _BLB changes according to the memory element 110 b being in the high resistance state HRS or the low resistance state LRS.

The control voltage is transmitted to the selection element 110c and the selection element 110d via the word line WL, and the input voltage is transmitted to the memory element 110a and the memory element 110b via the data line SL. The memory element 110a and the memory element 110b perform a setting operation or a reset operation according to the input voltage.

Before the memory element 110a and the memory element 110b are written, the memory element 110a and the memory element 110b need to be erased. In one embodiment, the memory element 110a and the memory element 110b are set to a high-resistance HRS, so that the non-volatile memory 100 operates in an erased state. After erasing, if you want to write this bit to logic 0, you need to set the memory element 110b to set the memory element 110b from the high-resistance HRS to the low-resistance LRS, as shown in the upper diagram of Figure 2. To write this bit to logic 1, the memory element 110a needs to be set to set the memory element 110a from the high-resistance state HRS to the low-resistance state LRS, as shown in the lower diagram of FIG. 2.

Through the above operations, the memory element 110a and the memory element 110b can have different resistance states to complete the writing operation.

The differential memory structure does not need to provide a reference current through an external circuit when reading and accessing the state, only the memory element on the right 110b is used as a reference current to determine the state of the memory element 110a on the left.

Please refer to the upper diagram of FIG. 2, when the memory element 110a is a high-resistance HRS and the memory element 110b is a low-resistance LRS, after the input voltage enters through the data line SL, a first current I will form through the memory element 110a _BL , a second current I _BLB is formed through the memory element 110b, the first current I _BL passes through the selection element 110c and passes through the bit line BL to the sensing circuit 120, and the second current I _BLB passes through the selection element 110d and passes through the bit line The BLB to the sensing circuit 120. The magnitude of the first current I _BL will change according to the memory element 110a in the high resistance state HRS or low resistance state LRS, the magnitude of the second current I _BLB will _depend on the memory element 110b in the high resistance state HRS or low resistance state LRS change. The relationship between current and resistance is inversely proportional. When the resistance is larger, the current is smaller. Therefore, the first current I _{BL is} smaller than the second current I _BLB , and the sensing circuit 120 determines that the non-volatile memory device 110 is in a low logic state, that is, logic 0.

Please refer to the lower diagram of FIG. 2, when the memory element 110a is a low-resistance LRS and the memory element 110b is a high-resistance HRS, the input voltage enters through the data line SL, and a first current I is formed through the memory element 110a _BL , a second current I _BLB will form through the memory element 110b. At this time, the first current I _{BL is} greater than the second current I _BLB , and the sensing circuit 120 determines that the non-volatile memory device 110 is in a high logic state, that is, logic 1.

In the application of high-density memory, you can use a cross-point memory array and omit the selection memory, but if you do not use the selected components and simply use a resistor (1R) array will produce the principle of the connecting tube, also known as the sneak current ( sneak current). Usually the selected memory device is in high resistance state HRS and the surrounding memory element is the low resistance state LRS. When selecting the bit line BL and the word line WL to operate or read a memory element that stores a high-resistance HRS, since the memory elements in the surrounding paths are all low-resistance LRS, the current will choose to flow to the equivalent resistance The lower path causes read errors or interferes with other unselected memory components. Therefore, the memory needs to be used in combination with the selected components to avoid the problem of stealth current.

In order to solve the above-mentioned communication tube problem, the selection element 110c and the selection element 110d are used in the two-dimensional array to drive the array of the memory element 110a and the memory element 110b, as shown in FIG. 3. One end of the memory element 110a and the memory element 110b is shared with the end of the selection element 110c and the selection element 110d to form a NOR type array, and the memory element 110a and the memory element 110b can be stably controlled by the control voltage modulation of the word line WL When the resistance value is converted, the voltage and current at both ends improve the durability of the device, and the unselected channels can be closed to avoid the problem of the communication tube.

Please refer to FIG. 3, which illustrates a circuit diagram of a non-volatile memory device 200 according to an embodiment of the present disclosure. This embodiment illustrates a 2X2 NOR differential resistive memory array. The number and arrangement of memory arrays in this disclosure are not limited to 2X2, and can be adjusted according to actual needs. The non-volatile memory device 200 includes four sets of non-volatile memory elements 110 and a sensing circuit (not shown). The four sets of non-volatile memory elements 110 are arranged in a 2×2 manner, and the sensing circuit may use the sensing circuit 120 shown in FIGS. 1 and 2. The operation mode is similar to the above description. The control voltage of the bit line WL1 is used to control the two non-volatile memory cells on the left. Device 110, the control voltage of the bit line WL2 is used to control the two non-volatile memory devices 110 on the right.

The operation method of the non-volatile memory device 110 on the upper left side is the same as that in FIG. 2 and will not be repeated here. When the upper right non-volatile memory device 110 is selected, the control voltage is input via the data line SL2. The current passing through the left memory element to node B then flows to bit line BLB1. The current passing through the memory element on the right to node C then flows to bit line BL1. The non-volatile memory element 110 on the upper right can change the resistance state through the setting operation and the reset operation to change the current flowing through the left memory element and the right memory element. The sensing circuit detects the two currents. The size determines the logic state of the non-volatile memory device 110 in the upper right.

For example, when the left memory element is in a low resistance state and the right memory element is in a high resistance state, the current flowing to the bit line BLB1 will be greater than the current flowing to the bit line BL1. At this time, the sensing circuit determines that the upper right is non-volatile The memory element 110 is in a low logic state (logic 0), otherwise it is in a high logic state (logic 1).

The operation methods of the non-volatile memory device 110 at the lower left and lower right are the same as above, and will not be repeated here.

The current comparison result on bit line BL1 and bit line BLB1 and the current comparison result on bit line BL2 and bit line BLB2 determine the logic state of the selected nonvolatile memory device 110.

In summary, the non-volatile memory uses two memory elements to form a differential structure. The two memory elements share character lines and data lines to minimize the array area. Use two memory elements to replace traditional resistive memory The memory requires an additional reference current to determine the logic state of the non-volatile memory, which greatly reduces the overall circuit area and enlarges the reading window. In addition to a single memory cell, the differential structure of this disclosure can be arranged in a NOR memory array to provide high-density storage.

In addition, the resistance state of the conventional single-resistance memory device will move to the reference current with time under high temperature, which may cause a misjudgment in data judgment. However, the differential structure proposed in this disclosure uses the self-comparison of the two memory elements to maintain a large current difference even after a long period of temperature, without data flipping.

100‧‧‧ Non-volatile memory

110‧‧‧ Non-volatile memory device

110a, 110b‧‧‧ memory element

110c, 110d‧‧‧selected components

120‧‧‧sensing circuit

SL‧‧‧Data cable

WL‧‧‧character line

BL, BLB‧‧‧bit line

Claims (9)

A non-volatile memory includes: a first memory element for receiving a control voltage and an input voltage and outputting a first current; and a second memory element coupled to the first memory element And used to receive the control voltage and the input voltage and output a second current, wherein the first memory element and the second memory element change from a high resistance state to a low resistance state according to a setting operation, according to a The reset operation changes from the low resistance state to the high resistance state, the first current changes according to whether the first memory element is in the high resistance state or the low resistance state, and the second current changes according to the second memory element Change in the high resistance state or the low resistance state. The non-volatile memory according to claim 1, further comprising: a sensing circuit for comparing the first current and the second current to determine whether the non-volatile memory is in a low logic state or a high logic state . The non-volatile memory of claim 2, wherein when the first current is less than the second current, the sensing circuit determines that the non-volatile memory is in the low logic state, and when the first current is greater than the first At two currents, the sensing circuit determines that the non-volatile memory is in the high logic state. The non-volatile memory according to claim 3, wherein when the first memory element is in the high resistance state, the first current is reduced, and when the first memory element is in the low resistance state, the The first current increases, When the second memory element is in the high resistance state, the second current is decreased, and when the second memory element is in the low resistance state, the second current is increased. The non-volatile memory according to claim 4, wherein when the first memory element and the second memory element are in the high-resistance state, the non-volatile memory operates in an erasing state. The non-volatile memory according to claim 5, further comprising: a first selection element coupled to the first memory element; and a second selection element coupled to the second memory element, wherein The first selection element and the second selection element are turned on in response to the control voltage. A non-volatile memory device includes: a plurality of non-volatile memories, one of which is used to generate a first current and a second current according to a control voltage and an input voltage; And a sensing circuit for comparing the first current or the second current to determine whether the non-volatile memory device is in a low logic state or a high logic state, wherein one of the non-volatile memories includes : A first memory element for receiving the control voltage and the input voltage and outputting the first current; a first selection element, coupled to the first memory element; a second memory element, coupled Used in the first memory element To receive the control voltage and the input voltage and output the second current; and a second selection element coupled to the second memory element, wherein the first selection element and the second selection element are responsive to the control voltage And turn on. The non-volatile memory device according to claim 7, wherein the first memory element and the second memory element change from a high resistance state to a low resistance state according to a setting operation, and from The low resistance state changes to the high resistance state. The non-volatile memory device according to claim 8, wherein when the first current is less than the second current, the sensing circuit determines that one of the non-volatile memories is the low logic state, When the first current is greater than the second current, the sensing circuit determines that one of the non-volatile memories is in the high logic state.

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