KR101231478B1 - Digit line equilibration using access devices at the edge of sub-arrays - Google Patents

Abstract

A method of balancing digit lines, a memory array, a device, a system, and a wafer for digit lines configured with an open digit line architecture are described. Digit lines are balanced by coupling the termination of the first digit line to the equilibrium reference and the non-termination of the second digit line to the termination of the first digit line. The memory array consists of first and second digit lines disposed directly adjacent to each other.

Description

DIGIT LINE EQUILIBRATION USING ACCESS DEVICES AT THE EDGE OF SUB-ARRAYS}

<Priority claim>

This application claims the priority of US patent application Ser. No. 12 / 045,353, filed March 10, 2008.

Various embodiments of the present invention generally relate to the field of volatile memory devices, and in particular, to balance the digit lines of random access memory.

Memory devices, such as dynamic random access memory (DRAM) devices, conventionally include a plurality of memory cells arranged in rows and columns. Memory cells are grouped into subarrays. Each memory cell includes a capacitor capable of holding a charge and an access transistor for accessing the capacitor charge. The charge is called a data bit and can be high voltage or low voltage. The data may be stored in the memory cells during the write mode, or the data may be retrieved from the memory cells during the read mode. The access transistors of the memory cells are connected to internal signal lines called bit or digit lines. The digit lines are connected to the input / output lines via input / output transistors used as switching devices to allow data to be transmitted between the digit lines and the input / output lines during read or write mode.

A number of sense amplifiers are included in the memories to sense data stored in the memory cells and amplify the data for output. Each sense amplifier compares the charge stored in a memory cell with a known reference. The sense amplifier is conventionally connected with two digit lines to perform a sensing operation. In the sensing operation, the two digit lines, first, using an equilibrate circuit, are one half of the supply voltage (Vcc), commonly referred to as DVC2, but not limited thereto. Equivalent The digit lines are then driven to opposite voltage levels. That is, one of the digit lines is driven to Vcc and the other to ground. The voltage of the digit line connected to the memory cell being accessed represents the value of the data stored in the memory cell.

In an open digit line memory device, all digit lines are interleaved. In particular, due to the relatively large dimensions of the sense amplifier relative to the dimensions of the memory cell, one digit line of the subarray is connected to one sense amplifier on one side of the subarray, and adjacent digit lines are on the other side of the subarray. It is connected to another sense amplifier. Thus, the digit line has a terminated end that is directly coupled to a sense amplifier in which logic states are programmed or sensed, and has an extended or unterminated end with the highest impedance path to the sense amplifier. .

Since the sensing circuits on each side of the subarray are only accessed alternately, or only alternately, the digit lines, sense amplifiers can be implemented at the edge of the subarray according to twice the spacing or pitch of the digit lines. The physical space required to implement the sense amplifiers typically limits the density of the memory cells of the subarray. Thus, because sense amplifiers are implemented on alternating sides of the memory subarray, an open digit line architecture with interleaved digit lines facilitates small digit line pitch sizes. In addition, small digit line pitch sizes allow high density subarrays that result in a relatively large physical length of the digit line and large numbers of attached memory cells through the subarray.

To prepare the digit lines for sensing logic values from the memory cells, balanced circuits were formed to electrically balance the digit lines. Conventional balancing circuits have been designed as part of a sense amplifier and have been designed according to the large feature sizes associated with the sense amplifier. Such large feature sizes of balanced circuits are undesirable in view of attempts to further reduce the size of the memory array and associated circuits.

For the reasons described above and other reasons described below that will be apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved balanced circuit that does not affect the pitch of interleaved digit lines. .

1 is a block diagram of a portion of an open digit line architecture of a memory device including a plurality of memory subarrays, in accordance with various embodiments of the present invention.
2 illustrates a balance and isolation circuit, in accordance with various embodiments of the present invention.
3 illustrates a balanced circuit of a portion of a memory subarray, in accordance with various embodiments of the present invention.
4 illustrates the physical layout of the balanced circuit of FIG. 3 in accordance with various embodiments of the present invention.
5 illustrates another balanced circuit of a portion of a memory subarray, in accordance with various embodiments of the present invention.
6 illustrates the physical layout of the balanced circuit of FIG. 5 in accordance with various embodiments of the present invention.
7 illustrates another balanced circuit of a portion of a memory subarray, in accordance with various embodiments of the present invention.
8 illustrates the physical layout of the balanced circuit of FIG. 7 in accordance with various embodiments of the present invention.
9 is a block diagram of a memory device according to various embodiments of the present disclosure.
10 is a block diagram of an electronic system according to various embodiments of the present disclosure.
11 is a diagram of a semiconductor wafer including an integrated circuit die incorporating one or more balanced circuits described herein, in accordance with various embodiments of the present invention.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, that other embodiments may be implemented and that structural, logical and electrical changes may be made without departing from the spirit and scope of the invention. Of course.

A method of balancing digit lines, a memory array, a device, a system, and a wafer comprising the same digit lines are described. In one embodiment of the invention, the digit lines of the memory device couple an end of the first digit line to an equilibrium reference and at least partially simultaneously with the non-termination of the second digit line terminate the first digit line. Equilibrium is maintained by coupling to the part. The memory array consists of an open digit line array with first and second digit lines disposed immediately adjacent to each other.

1 is a diagram of a portion of a memory array 100 in accordance with various embodiments of the present invention. The memory array 100 includes a plurality of subarrays including a subarray A 120 and a subarray B 130, a plurality of sense amplifiers (SAs) 102, 104, and 106. It is constructed according to the open digit line architecture. As an example, memory cells are located at each row and column intersection, and memory cells of the same column are connected to the same digit line, DIGIT A or DIGIT B. Memory cells of the same row are connected to the same row line or word line, WL. That is, the digit lines will be interleaved so that the activated word line WL will access the memory cell of each digit line.

Each of the sense amplifiers 104 is connected to a first digit line 140 on one side, for example DIGIT A, and to a second digit line 142 on the opposite side, for example, DIGIT B. . The first digit line A 140 is connected to the plurality of memory cells 141 represented by the points at each intersection of the digit line, the word line, and WL in the subarray A 120. Second digit line B 142 is also coupled to a plurality of memory cells 143 of subarray B 130 similar to those of subarray A 120. Digit lines A 140 are interleaved with digit lines 138 of subarray A 120, and digit lines B 142 are interleaved with digit lines 144 of subarray B 130.

In another embodiment of the present invention, a memory array is described and includes a memory subarray configured with an open digit line architecture. The memory array further includes a balancing circuit configured to balance the plurality of digit lines of the memory subarray. The balance circuit also includes pass transistors configured to be smaller than the digit line pitch.

2 illustrates a balance and isolation circuit for coupling a memory subarray with a sense amplifier, in accordance with various embodiments of the present invention. The sense amplifier 104 may sense the first memory subarray A 120 and the second memory subarray B 130, wherein each memory subarray includes a plurality of memory cells. The sense amplifier 104 may include a selected memory cell of the subarray A 120 or the subarray B 130, or the complementary digit lines 142, respectively, through a pair of complementary digit lines 140. The voltage level of the selected memory cell of the selected subarray B 130 is sensed through the pair of. One of the subarray A 120 or the subarray B 130 is used to determine the signal to the word line 108 or 109 corresponding to the memory cell of the memory subarray A 120 or the memory subarray B 130, respectively. Application, and application of a signal to ISOA and ISOB for transistors 114, 115, 116, and 117, respectively. Thus, when ISOA is enabled and driven to a logic high value, transistors 114 and 115 become conductive, ie, turned on, connecting subarray A 120 to sense amplifier 104. When ISOB is enabled and driven to a logic high value, transistors 116 and 117 are turned on, connecting subarray B 130 to sense amplifier 104.

Balanced circuits 122 and 132 are provided to precharge the digit lines. For convenience, the operation of the balancing circuit 122 on the memory subarray A 120 side of the sense amplifier 104 is now described, and the balancing circuit 132 including the transistors 133-136 may be configured to include the sense amplifier 104. It will be appreciated that the operation works the same for the memory subarray B 130 side.

Balance circuit 122 is coupled to receive a first source / drain region coupled to digit line 140, a second source / drain region coupled to complementary digit line 140, and a balanced signal named EQA. Transistor 123 having a gate. The balance circuit 122 further includes transistors 124, 125, 126. Transistor 124 includes a first source / drain region coupled to digit line 140, a gate coupled to receive the balanced signal EQA, and a second source / drain coupled to the first source / drain region of transistor 126. It includes a drain region. Transistor 125 includes a first source / drain region coupled to complementary digit line 140, a gate coupled to receive balanced signal EQA, and a second source coupled to first source / drain region of transistor 126. / Drain area. Transistor 126 has a second source / drain region coupled to balanced voltage DVC2, typically Vcc / 2, and a pumped Vcc voltage, typically gated to VCCP, approximately 1 to 2 volts higher than Vcc. Application of VCCP to the gate of transistor 126 causes transistor 126 to supply a balanced voltage to transistors 124 and 125. When the EQA signal is at a high logic level, transistors 124 and 125 apply a balanced voltage to digit lines 140, and transistor 123 shorts the lines, so that both lines are referred to as DVC2, Vcc / 2. Is kept in equilibrium.

During the read operation, digit line 140 will go to Vcc or GND depending on the charge stored in the read memory cell. The sense amplifier 104 senses a differential voltage across the digit lines 140, which represents the charge stored in the accessed memory cell and drives one of the digit lines 140, which includes a high voltage up to Vcc and GND. To drive the other one of the digit lines 140 up to and including the low voltage. Each of these voltages, Vcc and GND, is also provided to I / O, I / O * lines 118.

According to sense amplifier layouts known in the art, the balancing circuits of the respective sense amplifiers are conventionally located in sense amplifier circuit blocks of the memory device layout. In such a configuration, the balanced transistors 123, 124, 125 are fabricated using large feature size sense amplifiers resulting in a much larger circuit area. However, according to various embodiments of the present invention, the balancing circuits of the sense amplifiers are not located in the sense amplifier blocks, but instead are located in or in extension lines of the memory subarray blocks. In particular, various embodiments of the present invention form a balanced circuit after the last memory cell along the word line at the edge of the memory subarray. In addition, various embodiments of the present invention generally provide for the general purpose of a memory subarray, as opposed to balancing circuits of the prior art formed in or near the sense amplifiers in accordance with layout dimensions and rules of the devices associated with the sense amplifiers. Balanced circuits can be formed according to smaller layout dimensions. Forming balanced circuits in accordance with sense amplifier design guidelines results in an unnecessarily bulky design, allowing the balanced circuit to be placed farther away from the portion of the digit line passing through the memory subarray.

3 illustrates a circuit diagram of a balanced circuit of a portion of a memory subarray, in accordance with various embodiments of the present invention. Part of the memory subarray 150 is shown with an open digit line architecture that includes interleaved digit lines. In FIG. 3, the plurality of memory cells 152 are disposed along the word line WL1 156, and the plurality of memory cells 154 are also disposed along the word line WL0 158. Digit lines DL1-DL5 160-168 are interleaved through the memory subarray. In particular, memory cells 154 are initial memory cells along digit line DL1 160, digit line DL3 164, and digit line DL5 168 that are connected to sense amplifiers 180. Memory cells 154 represent the final or terminal memory cells along digit line DL2 162 and digit line DL4 166 coupled to sense amplifiers (not shown) located on opposite sides of the memory subarray.

As described, prior to the read operation of the memory subarray, the digit lines DL1-DL5 160-168 are subjected to undesirable electrical charges from the digit lines before sensing the logic state of the memory cells of the subarray of memory devices. It must be equilibrated to eliminate it. This embodiment uses a balanced circuit formed at the edge of the memory subarray according to the layout standard and process of the subarray as opposed to the layout standard of the sense amplifier. Thus, balance circuit 182 includes balanced pass transistor 174 formed at the edge of memory subarray 150 formed as part of the memory subarray. As an example, balanced pass transistor 174 connects digit line DL1 160 to balance reference 172 (DVC2) when activated by balance signal 170. 3 further shows a pass transistor 176 that is similarly connected to balance digit line DL3 164 and a pass transistor 178 to balance digit line DL5 168. Since the memory subarray is configured according to the open digit line architecture, the digit line DL2 162 and the digit line DL4 166 are formed by other portions of a balanced circuit (not shown) similarly configured on the opposite side of the memory subarray. It should be noted that equilibrium is maintained.

4 illustrates the physical layout of an edge of a subarray of memory cells of the circuit shown in FIG. 3, in accordance with one or more embodiments of the present invention. The present invention begins with conventional DRAM layouts known in the art, by rearranging the balanced circuits within the array and adjacent to the last row of memory cells 154 at the edge of the memory cell subarray 150. The balance signal 170 for the balanced transistors is adjacent to the word lines WL of the memory subarray, and the balance signal 170 is configured to be formed according to the process steps and dimensions of the next adjacent word line WL. 4 also shows digit line DL1 160 and digit line DL3 164 spaced apart by a single digit line pitch.

As shown in FIG. 4, a block 200 of memory cells 152, 154 is formed in a substrate according to one or more known methods, the nonlimiting examples of which are assigned to the assignee of the present invention. US Patent Application No. 11 / 366,212, filed March 2, 2006 entitled " Vertical Gated Access Transistor, " and " Non-Planar Transistor and Techniques for Fabricating the Same, " US patent application Ser. No. 11 / 433,533, filed May 12, 2006, entitled. As an example, and not by way of limitation, a single memory cell and corresponding portion of a balanced circuit is described in a configuration similar to each memory cell and each digit line. As described, the memory subarray consists of an open digit line architecture in which the digit lines are interleaved. Thus, while part of the balancing circuit is described with respect to one edge of the memory subarray, a symmetrical part is also implemented at the opposite edge (not shown) of the memory subarray to balance the other part of the interleaved digit lines.

As will be described, memory cell 152 is a pass transistor 202 formed between vertical pillars 204 configured to couple to digit line DL1 160 via contact 206 (denoted by "X"). ). Pass transistor 202 is also formed to include another vertical column 208 configured to be coupled through contact 210 (indicated by " ○ " to capacitor 212). Pass transistor 202 is controlled by word line WL1 156 which, when activated, connects capacitor 212 (FIG. 3) to digit line DL1 160.

As described, the digit lines must be balanced to a neutral reference that does not have a preferred bias for reading other logic states. Balance circuit 182 responds to balance signal 170 to activate balance pass transistors 174 and 176. According to the embodiment described with reference to FIGS. 3 and 4, the balanced pass transistor 174 is vertically gated formed at one half of the digit line pitch of the memory subarray (width of the feature plus space to the next iteration feature). It is configured as a pass transistor. As described, conventional balance circuits have been formed in accordance with design parameters of sense amplifiers designed to be much larger than the half pitch of the balanced pass transistors of the balanced circuits of the various embodiments of the present invention.

The balanced pass transistor 174 is also formed according to the formation processes of the pass transistor of the memory cell, but the balanced pass transistor is formed as a long transistor while maintaining processing steps similar to those performed during the manufacture of the memory subarray. . Balance pass transistor 174 couples digit line DL1 160 to balance reference 172 (DCV2) when balance signal 170 is asserted. Balanced pass transistor 174 is formed between vertical columns 224 configured to couple to digit line DL1 160 via contact 226 (denoted as “X”). Balanced pass transistor 174 is further formed to include another vertical column 228 configured to couple to isolation 232 of the digit line layer through contact 230 (denoted by "X") for fabrication convenience. Subsequent contacts 234, denoted large " X " continue to contact balance pass transistor 174 to balance reference 172 (DCV2) when balanced signal 170 is asserted.

5 illustrates a circuit diagram of a balanced circuit of a portion of a memory subarray, in accordance with various other embodiments of the present invention. Part of the memory subarray 150 is shown with an open digit line architecture that includes interleaved digit lines. In this embodiment, a balanced circuit is formed at the edge of the memory subarray according to the layout standard of the subarray as opposed to the layout standard of the sense amplifier. Thus, the balanced boosting circuit 282 includes a balanced boosting pass transistor 274 formed at the edge of the memory subarray 150 and is further formed as part of the memory subarray. As an example, the balanced boosting pass transistor 274 connects the digit line DL1 160 to the digit line DL2 162 when activated by the balanced boosting signal 270. In one embodiment, balance boosting signal 270 is activated to match the duty cycle of balance signal 170. In another embodiment of the present invention, the balance boosting signal 270 is activated during a portion of the activation of the balance signal 170 to provide a balance boost to the balance circuit 350 by reducing the resistance of the digit line during the balance process. For connection with the digit line DL2 162, the digit line DL2 162 is formed to include an extension 290 of the digit line DL at an extended end opposite the digit line end connected to the sense amplifier.

Balanced boosting circuit 282 enhances the rate of equilibrium by engaging the extended or non-terminated end of the digit line during equilibrium with adjacent digit lines very close to the balanced circuit. Balanced boosting circuit 282 balances the charge of the digit line from both ends of the digit line by connecting the digit line and the extended or non-terminated end of the digit line physically close to the balance circuit. Balance of the digit line from both ends provides a number of current paths for charging or discharging the digit line as well as providing a low resistance along the digit line. In one embodiment, the balance circuit used by balance boosting circuit 282 is located within sense amplifiers 180. In another embodiment, the balanced boosting circuit 282 uses the balancing circuit 182 described in connection with FIGS. 3 and 4.

FIG. 6 illustrates the physical layout of an edge of a subarray of memory cells of the circuit shown in FIG. 5, in accordance with one or more embodiments of the present invention. FIG. Balance circuit 282 includes a balanced boosting signal 270 to activate balanced boosting pass transistors 274 and 276. In accordance with the embodiment described with reference to FIG. 6, balanced boosting pass transistor 274 is a vertically gated pass formed at one-half of the digit line pitch of the memory subarray (width of the feature plus space to the next repeating feature). It is configured as a transistor. As described, conventional balance circuits have been formed in accordance with design parameters of sense amplifiers designed to be much larger than the half pitch of the balanced pass transistors of the balanced circuits of the various embodiments of the present invention.

The balanced boosting pass transistor 274 is also formed as a vertical transistor, such as a memory cell pass transistor, but the balanced pass transistor is formed as a long transistor while maintaining similar design dimensions as used during the manufacture of the memory subarray. Balanced boost pass transistor 274 couples digit line DL1 160 to digit line DL2 162 when balanced boosting signal 270 is asserted. Balanced boost pass transistor 274 is formed between vertical columns 324 configured to couple to digit line DL1 160 via contact 326 (denoted as "X"). Balanced boost pass transistor 274 is also formed to include another vertical column 328 configured to couple to extension 290 of digit line DL2 162 via contact 330 (denoted as "X").

As described, the balancing circuit may be implemented as the balancing circuit 182 instead of depending on the balancing circuit of the sense amplifier. Thus, in other embodiments, balance circuit 350 may include a combination of balance circuit 182 and balance boosting circuit 282.

7 illustrates a circuit diagram of a balanced circuit of a portion of a memory subarray, in accordance with various other embodiments of the present invention. A portion of memory subarray 150 is shown and implemented as described below. In one embodiment, the balance circuit is formed at the edge of the memory subarray according to the layout standard of the subarray as opposed to the layout standard of the sense amplifier. Thus, the balance circuit 450 includes a balance circuit 350 (FIGS. 5 and 6) and includes a balanced boosting circuit 382 including a balanced boosting pass transistor 374 formed at the edge of the memory subarray 150. It is further included, and formed as part of the memory subarray. As an example, the balanced boosting pass transistor 374 connects the digit line DL2 162 to the digit line DL3 164 when activated by the balanced boosting signal 370. In one embodiment, balanced boosting signal 370 is activated to match the duty cycle of balance signal 170 and balances boosting signal 270. In another embodiment of the present invention, the balanced boosting signal 370 is activated during a portion of the activation of the balanced signal 170 and the balanced boosting signal 270, thereby reducing the resistance of the digit line during the balancing process, thereby balancing the balanced boost. Provided at 450. To form a connection with the extended end of digit line DL2 162, digit line DL2 162 is formed to include an extension 390 of digit line DL at their extended end. In this embodiment, the additional balanced boosting circuit 382 is offset from the balanced boosting circuit 282 by one digit line. This offset of the balanced boosting circuits enables the formation of a network of pass gates, essentially shorting all digit lines DL1-DL5 together, resulting in a common balanced reference voltage across all digit lines DL.

Balanced boost circuit 382 enhances the rate of equilibrium by engaging the extended or non-terminated end of the digit line during equilibrium with a digit line adjacent to the balance circuit in close proximity. The balanced boosting circuit 382 connects the adjacent digit line physically close to the balanced circuit with the extended or non-terminated end of the digit line to balance the charge of the digit line from both ends of the digit line. Keeping the digit line balanced from both ends not only provides a number of current paths for charging or discharging the digit line but also provides a low resistance along the digit line, resulting in faster equilibrium time. In one embodiment, the balance circuit used by balance boosting circuit 382 is located within sense amplifiers 180. In another embodiment, balanced boosting circuit 382 uses balance circuit 182 at the edge of the memory subarray described in connection with FIGS. 3 and 4.

FIG. 8 illustrates the physical layout of an edge of a subarray of memory cells of the circuit shown in FIG. 7, in accordance with one or more embodiments of the present invention. The balance circuit 382 includes a balanced boosting signal 370 for activating the balanced boosting pass transistors 374 and 376. According to the embodiment described with reference to FIG. 8, the balanced boosting pass transistor 374 is a vertically gated pass formed at one half of the digit line pitch of the memory subarray (width of the feature plus space to the next repeating feature). It is configured as a transistor. As described, conventional balance circuits have been formed in accordance with design parameters of sense amplifiers designed to be much larger than the half pitch of the balanced pass transistors of the balanced circuits of the various embodiments of the present invention.

The balanced boosting pass transistor 374 is also formed as a vertical transistor, such as a memory cell pass transistor, but the balanced pass transistor is formed as a long transistor while maintaining processing steps similar to those performed during the manufacture of the memory subarray. Balanced boost pass transistor 374 couples digit line DL2 162 to digit line DL3 164 when balanced signal 370 is asserted. Balanced boost pass transistor 374 is formed between vertical columns 424 configured to couple to extension 390 for digit line DL2 162 via contact 426 (denoted as "X"). The balanced boosting pass transistor 374 is further formed to include another vertical column 428 configured to be coupled through the contact 430 (denoted by "X") of the digit line DL3 164.

As described, the balancing circuit 450 may be implemented using the balancing circuit 182 instead of depending on the balancing circuit of the sense amplifier. Thus, in other embodiments, balance circuit 450 may include a combination of balance circuit 182, balance boosting circuit 282, and balance boosting circuit 282.

In another embodiment of the present invention, a memory device is described. The memory device includes a memory array configured in an open digit line architecture. The memory device also includes a balanced circuit comprising a balanced pass transistor configured to couple an end of the first digit line to the equilibrium reference, and a first balanced boost configured to couple an unterminated portion of the second digit line to an end of the first digit line. And a balanced boosting circuit comprising a pass transistor, wherein the first and second digit lines are disposed immediately adjacent to each other.

9 is a block diagram of a memory device according to an embodiment of the present invention. DRAM memory device 400 includes control logic circuit 420 that controls reads, writes, erases, and performs other memory operations. Column address buffer 424 and row address buffer 428 are configured to receive a memory address request. A refresh controller / counter 426 is coupled to the row address buffer 428 to control the refresh of the memory array 422. The row decode circuit 430 is coupled between the row address buffer 428 and the memory array 422. The memory array 422 includes a memory subarray 452 and a balance circuit 460 in accordance with various embodiments of the present invention. The column decode circuit 432 is coupled to the column address buffer 424. Sense amplifiers-I / O gating circuit 434 are coupled between column decode circuit 432 and memory array 422. DRAM memory device 400 is also shown having an output buffer 436 and an input buffer 438. An external processor may be coupled to the control logic circuit 420 of the DRAM memory device 400 to provide external instructions.

Another embodiment of the present invention describes an electronic system. The electronic system includes a processor and a memory device operably coupled to the processor. The memory device includes a balance circuit and a memory subarray composed of an open digit line architecture. The balance circuit includes a balance pass transistor configured to couple the termination of the first digit line to the balance reference. The balance circuit further includes a balanced boosting circuit including a first balanced boosting pass transistor configured to couple the non-termination of the second digit line to the end of the first digit line. Additionally, the first and second digit lines are disposed immediately adjacent to each other.

10 is a block diagram of an electronic system according to an embodiment of the present invention. Electronic system 500 includes input device 572, output device 574, and memory device 400, all coupled to processor device 576. Memory device 400 incorporates at least one memory subarray and balance circuit in accordance with one or more various embodiments described herein.

Another embodiment describes a semiconductor wafer comprising at least one memory array constructed of an open digit line architecture. The memory array includes a balancing circuit configured to balance the first digit line coupled to the non-termination of the second digit line during the balance process.

FIG. 11 is a semiconductor wafer including an integrated circuit die incorporating capacitor-less memory cells and a memory array of one or more previous embodiments, in accordance with another embodiment of the present invention. It is a drawing of. As shown in FIG. 11, semiconductor wafer 600 includes an yet uncut integrated circuit die 440 incorporating one or more capacitorless memory cells described herein.

The processes and devices described above describe embodiments of some of the methods and devices among a number of methods and devices that can be used and produced in accordance with embodiments of the present invention. The above description and drawings illustrate embodiments that provide the main features and advantages of the present invention. However, it is not intended that the present invention be strictly limited to the above-described and described embodiments.

Although the present invention has been shown and described with reference to specific embodiments, even though not specifically described or shown herein, various additions, deletions, and modifications apparent to those skilled in the art are deemed to be within the scope of the invention, which is accomplished by the following claims. do.

Claims (27)

A method of balancing digit lines in a memory device configured with an open digit line architecture.
Coupling a terminated end of the first digit line of the memory subarray to an equilibration reference; And
Coupling an unterminated end of a second digit line of the memory subarray to the end of the first digit line, coupling the end of the first digit line to the equilibrium reference and the Coupling the non-termination of the second digit line to the termination of the first digit line occurs at least partially simultaneously with each other;
&Lt; / RTI &gt; The method of claim 1,
Coupling the first digit line of the memory subarray from an unterminated end of the first digit line of the memory subarray at least partially simultaneously with coupling the end of the first digit line to the equilibrium reference. The method further comprises a step. 2. The method of claim 1, wherein coupling the non-termination of the second digit line comprises: passing the non-termination of the second digit line through a pass transistor configured at one half of the pitch of the open digit line architecture. Further comprising combining parts. The method of claim 1,
Coupling the termination of the first digit line further comprises coupling the termination of the first digit line to the equilibrium reference through a pass transistor configured at one half of the pitch of the open digit line architecture. How to. The method of claim 1,
Coupling the termination of the first digit line to the equilibrium reference and coupling the non-termination of the second digit line to the first digit line occur simultaneously. The method of claim 1,
Coupling the termination of the first digit line to the equilibrium criterion and coupling the non-termination of the second digit line to the first digit line occur for different durations of time. The method of claim 1,
Coupling an end of a third digit line immediately adjacent to the second digit line and the non-termination of the second digit line,
Coupling the termination of the third digit line and the non-termination of the second digit line directly adjacent to the second digit line comprises: coupling the termination of the first digit line to the equilibrium reference; and Coupling the non-termination of the second digit line to the termination of the first digit line at least partially concurrently. 1. A memory array comprising:
A memory sub-array configured with an open digit line architecture; And
A balanced pass transistor configured to couple an end of a first digit line to an equilibrium reference, and a first balanced boosting pass transistor configured to couple an unterminated portion of a second digit line to the end of the first digit line. A balanced circuit further comprising a balanced boosting circuit, wherein the first digit line and the second digit line are adjacent to each other;
Memory array comprising a. 9. The memory array of claim 8 wherein the balance circuit is configured to balance a plurality of digit lines in the memory subarray. 9. The memory array of claim 8 wherein the balance circuit is formed in accordance with layout dimensions of the memory subarray. The method of claim 10,
And the balanced pass transistor and the first balanced boosting pass transistor are each configured at a pitch less than the digit line pitch of the memory subarray. The method of claim 10,
And said balanced pass transistor and said first balanced boosting pass transistor are each configured at one half of the pitch of said open digit line architecture. The method of claim 10,
The balance circuit is configured at an edge of the memory subarray and fabricated as an extension of the memory subarray. 9. The method of claim 8,
The balance pass transistor is configured to couple the termination of the first digit line to the balance reference in response to a balance signal. 15. The method of claim 14,
And the first balanced boosting pass transistor is configured to couple the non-termination of the second digit line to the termination of the first digit line in response to a first balance boosting signal. 16. The method of claim 15,
And the balanced signal and the first balanced boosting signal are assertable at the same time. 17. The method of claim 16,
And the first balanced boosting signal is assertable for a duration shorter than the balanced signal. 9. The method of claim 8,
The balance circuit further includes a second balance circuit including a second balanced boosting pass transistor configured to couple the non-termination of the second digit line with an end of a third digit line. 19. The method of claim 18,
And the third digit line is adjacent to the second digit line. 9. The method of claim 8,
And the termination of the first digit line comprises an extended portion coupling the first digit line with the first balanced boosting pass transistor. 9. The method of claim 8,
And the first balanced boosting pass transistor is formed twice the feature size of a pass transistor in a memory cell of the memory subarray. The method of claim 21,
And said first balanced boosting pass transistor is configured as an extension of said memory subarray, and is formed in multiples of a feature size of a pass gate of a memory cell of said memory subarray. 9. The method of claim 8,
And a sense amplifier coupled with the non-termination of the second digit line. 9. The method of claim 8,
And the memory array is configured within a memory device. 25. The method of claim 24,
And the memory device is configured within an electronic system including a processor operatively coupled with the memory device. 26. The method of claim 25,
And control logic configured to control memory operations of the memory array including at least one of a read operation, a write operation, an erase operation, a refresh operation, and a balance operation. 9. The method of claim 8,
And the memory array is configured in a semiconductor wafer.

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