KR20090123090A - Manufacturing method of semiconductor device - Google Patents

Abstract

PURPOSE: A manufacturing method of a semiconductor device is provided to make a silicon surface amorphous by including an ion injection process for forming a solid solution through reaction with silicon. CONSTITUTION: A gate insulation film(103) and a polysilicon film are formed on a semiconductor substrate(101). A laminate pattern is formed by etching the polysilicon film and the gate insulation film. A spacer film(107) and an etch stop film(109) are formed in a sidewall of the laminate pattern. A junction region(102) is formed by injecting a dopant ion to the semiconductor substrate of both sides of the laminate pattern. An ion is injected to the junction region and the polysilicon film, and forms a solid solution through reaction with the silicon. A metal film is formed on a top part of the polysilicon film and the junction region.

Description

Manufacturing method of semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of stabilizing the silicide layer forming process of the semiconductor device and improving the characteristics of the semiconductor device by reducing the resistance.

Recently, as the size of a semiconductor device is reduced, a shallow junction is required to prevent deterioration of characteristics due to a short channel phenomenon. In more detail, as the size of the semiconductor device decreases and the length of the channel shortens, characteristics of the semiconductor device such as a punch through phenomenon occur. In order to solve this problem, a shallow junction is required to reduce the strength of the electric field between the junction region, that is, the source and the drain of the semiconductor device, during transistor operation.

The formation of a shallow junction can be formed by lowering the ion implantation depth by lowering the ion implantation energy applied to form the junction region. As the shallow junction is formed, the sheet resistance of the junction region increases to increase the size of the parasitic resistance. Since the parasitic resistance is a factor that hinders the operation of the semiconductor device, a method of reducing the sheet resistance of the junction region is required.

In order to reduce the sheet resistance of the junction region, a method of forming a silicide layer having a similar resistivity to a metal on the surface of the junction region has been introduced. Incorporation of the silicide layer into the shallow junction can reduce the high resistance due to the shallow junction to 10? Or less, thereby facilitating the operation of the semiconductor device.

The silicide layer described above is formed by depositing a metal film on a semiconductor substrate where the junction region is exposed and performing a heat treatment process so that the silicide layer is formed by reacting the metal film and silicon in the junction region. The heat treatment process proceeds step by step so that the metal and silicon react to undergo various phase changes to finally form the silicide layer of the most stable phase. This silicide layer should be thin and uniform in order to preserve the bonding properties of the junction region and to improve thermal stability. However, since the silicide layer is formed through various phase changes until a stable phase is obtained, silicide layers having various states may be included in the entire silicide layer, and defects may be formed at each phase boundary. As described above, when the silicide layer includes various states, it is difficult to control the resistance of the silicide layer as a whole. In addition, defects in the silicide may cause a problem of increased leakage current and resistance (Rs) in the final metal silicide layer.

The problem in forming the silicide layer is not limited to the junction region but also occurs in the gate pattern to which the silicide layer is applied.

The present invention provides a method of forming a silicide layer of a semiconductor device and a method of manufacturing a semiconductor device using the same, which can stabilize a silicide layer forming process of a semiconductor device and reduce resistance to improve characteristics of the semiconductor device.

A method of manufacturing a semiconductor device according to the present invention includes the steps of forming a gate insulating film and a polysilicon film on a semiconductor substrate, etching the polysilicon film and the gate insulating film to form a stacked pattern, and impurity ions are applied to the semiconductor substrates on both sides of the stacked pattern. Implanting to form a junction region, implanting ions forming a solid solution by reacting with silicon to a junction region and a polysilicon film, forming a metal film on the junction region and the polysilicon film, and a heat treatment process And reacting the silicon of the polysilicon film with the metal film to form a metal silicide film on the surface of the junction region and the surface of the polysilicon film.

In the step of injecting ions forming a solid solution by reacting with silicon into the junction region, ions are implanted into the junction region and the polysilicon film, and the surface of the junction region and the surface of the polysilicon film are amorphous.

Ions that react with silicon to form a solid solution include nitrogen.

The conductive film includes a polysilicon film, and the polysilicon film is formed on the uppermost layer of the laminated pattern.

In the step of implanting ions forming a solid solution by reacting with silicon into the junction region, the ions are simultaneously implanted into the conductive film, and in the step of forming the metal film, a metal film is simultaneously formed on the conductive film. The metal silicide film is formed by reacting a metal film.

In the step of implanting ions that react with silicon to form a solid solution, ions are implanted into the conductive film and the polysilicon film is amorphous.

The metal film contains cobalt. In this case, CoSi ₂ phase is formed in the whole area | region of the metal silicide film formed by a heat processing process.

The metal film contains titanium. In this case, TiSi ₂ phase is formed in the whole area | region of the said metal silicide film formed by the heat processing process.

When ions reacting with silicon to form a solid solution include nitrogen and the metal film contains titanium, a TiN ₂ phase is formed on the entire surface of the metal silicide film and a TiN film is formed on the surface of the metal silicide film.

Forming a junction region on the semiconductor substrate on both sides of the laminate pattern using the laminate pattern as a mask, and then forming spacers on sidewalls of the laminate pattern, and forming a spacer at a higher concentration than the junction region in the junction region using the laminate pattern and the spacer as a mask. Implanting impurity ions to form a junction region of the LDD structure.

In the step of implanting ions that react with silicon to form a solid solution, the ion implantation energy is preferably 5KeV to 15KeV.

In the step of implanting ions that react with silicon to form a solid solution, the ion implantation angle is preferably 2 ° to 4 °.

In the step of implanting ions that react with silicon to form a solid solution, the ion implantation target depth Rp is preferably 20 kPa to 40 kPa.

In the step of implanting ions that react with silicon to form a solid solution, the ion dose is preferably 5 × 10 13 Ions / cm 2 to 8 × 10 13 Ions / cm 2.

The heat treatment process is preferably carried out for a temperature increase rate of 20 ℃ / min to 40 ℃ / min, a temperature of 450 ℃ to 750 ℃ and a time of 10 seconds to 60 seconds.

The present invention includes a step of injecting ions to react with silicon to form a solid solution, which can not only amorphous the surface of the silicon so that the reaction between the metal and silicon can occur uniformly, but also prevent abnormal compound formation and prevent the formation of metal silicide in a stable phase. To form a layer.

Since the metal silicide layer can be uniformly formed in a stable phase, the present invention can easily control the overall resistance and improve the electrical characteristics of the semiconductor device.

According to the present invention, since the metal silicide layer may be uniformly formed into a stable phase, defects may not occur due to phase change, and thus the resistance of the metal silicide layer may be reduced.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

Referring to FIG. 1A, a gate insulating film 103 and a conductive film 105 are formed on a semiconductor substrate 101.

In general, the semiconductor substrate 101 uses a silicon substrate. In addition, the gate insulating layer 103 may be formed by forming an oxide film on the semiconductor substrate 101 by a thermal oxidation process and then nitriding the same. Here, the conductive film 105 includes a polysilicon film. The polysilicon film may be in an undoped state in which n-type or p-type ions are not doped or in a doped state in which n-type or p-type ions are doped.

Referring to FIG. 1B, after the hard mask pattern (not shown) is formed on the conductive film, the gate insulating film 103 and the conductive film are etched by etching the conductive film 105 and the gate insulating film 103 using the hard mask pattern as an etching mask. A lamination pattern including the film 105 is formed. After the lamination pattern is formed, the first junction region 101a is formed by implanting impurity ions having a first concentration into the semiconductor substrate 101 on both sides of the lamination pattern using the lamination pattern as a mask. The hard mask pattern may be removed after forming the stacked pattern or after forming the first bonding region 101a. As a result, the conductive film 105 formed at the uppermost layer of the stacked pattern, that is, the polysilicon film is exposed.

Referring to FIG. 1C, a spacer layer 107 and an etch stop layer 109 are formed on sidewalls of the stacked pattern. The spacer layer 107 and the etch stop layer 109 are formed so as not to expose the stacked pattern in a subsequent process of forming a contact hole for exposing a junction region formed between the stacked patterns. In this case, the spacer layer 107 includes an oxide layer and the etch stop layer 109 includes a nitride layer.

The spacer layer 107 and the etch stop layer 109 may be formed on the semiconductor substrate 101 including the surface of the stacked pattern and then etched by an etch-back process to remain only on the sidewalls of the gate pattern 105a. .

Referring to FIG. 1D, an impurity ion implantation process having a second concentration higher than the first concentration may be performed using the spacer layer 107, the etch stop layer 109, and the stacked pattern as a mask, and the semiconductor substrate 101 may be formed on both sides of the stacked pattern. 2 joining area | region 101b is formed. As a result, a junction region 102 having a lightly doped drain (LDD) structure is formed.

On the other hand, when the conductive film 105 is in an undoped state, an impurity ion implantation process may be performed to target the conductive film 105 to provide electrical characteristics to the conductive film 105. The implantation of impurity ions into the conductive film 105 may be performed before or after the formation of the junction region 102 or at the same time as the formation of the first or second junction regions 101a or 101b. When the semiconductor device has a CMOS structure, n-type impurity ions may be implanted into the conductive film 105 corresponding to the NMOS transistor, and p-type impurity ions may be implanted into the conductive film 105 corresponding to the PMOS transistor. When performing the ion implantation process, the remaining regions other than the target region may be covered by the photoresist pattern so that the ion implantation may be limited to the target region. For example, in order to perform an n-type impurity ion implantation process, a photoresist pattern exposing the NMOS transistor region and covering the PMOS transistor region may be used as a mask. In addition, in order to perform the p-type impurity ion implantation process, a photoresist pattern exposing the PMOS transistor region and covering the NMOS transistor region may be used as a mask. These photoresist patterns are each removed after completing each ion implantation process.

When implanting n-type impurity ions, acenic (As75) or phosphorus (P31) is used, and when implanting p-type impurity ions, boron (B11) or boron fluoride (BF49) is used.

Referring to FIG. 1E, ions for reacting with silicon to form a solid solution are implanted into the surface of the conductive film 105 and the bonding region 102 so that the silicide layer may be uniformly formed in a subsequent process. Through the ion implantation process, silicon on the surfaces of the conductive film 105 and the junction region 102 may be amorphized.

Ions that react with silicon to form a solid solution include nitrogen ions (N +), and the nitrogen ion implantation process is performed by a blanket process. In other words, the nitrogen ion implantation process is limited to the exposed portions of the junction region 102 and the conductive film 105, whereby nitrogen ions may be implanted into the surfaces of the conductive film 105 and the junction region 102. The surfaces of the conductive film 105 and the junction region 102 may be amorphous.

The reason for using nitrogen ion is as follows.

First, since nitrogen ions are light in weight, they can reduce defects in the crystal lattice of silicon during the ion implantation process.

Second, silicon and nitrogen form a solid solution to prevent the occurrence of abnormal compounds.

In order to minimize defects in the silicon crystal lattice during the nitrogen ion implantation process, its energy and ion implantation angle need to be limited. In more detail, it is preferable that the ion energy applied by using ultra low energy equipment in the nitrogen ion implantation process is limited to 5 KeV to 15 KeV. In addition, the ion implantation angle in the nitrogen ion implantation process is preferably 2 ° to 4 ° based on the axis perpendicular to the semiconductor substrate 101.

The ion implantation target depth Rp during the nitrogen ion implantation process is preferably 20 kPa to 60 kPa from the surface of the junction region 102 or the stacked pattern, and the dose is 5 × 10 13 Ions / cm 2 to 8 × 10 13 Ions / cm 2. It is preferable.

The nitrogen ion implantation process may be performed by a laser thermal process (LTP) so that the exposed junction region 102 and the lamination pattern may be more easily amorphous.

Referring to FIG. 1F, an oxide film that may occur on the conductive film 105 (particularly, an upper portion of the conductive film 105 doped with n-type impurities) may be formed by the ion implantation process described above with reference to FIG. 1D. After the cleaning process for removing is performed, the metal film 111 is formed on the semiconductor substrate 101 including the upper portion of the conductive film 105 and the upper portion of the junction region 102.

The metal film 111 is preferably formed to a thickness of 50 kPa to 500 kPa. In addition, various metals such as titanium (Ti) and cobalt (Co) may be used as the metal layer 111.

Referring to FIG. 1G, a heat treatment process is performed such that a metal film and an amorphous silicon layer react by a rapid thermal anneal (RTA) or rapid thermal process (RTP) method, and then a cleaning process is performed. Accordingly, the gate pattern 105a including the gate insulating film 103, the conductive film 105, and the metal silicide film 113, the first junction region 101a, the second junction region 101b, and the metal silicide film ( A junction region 102 is formed that includes 113.

In detail, the metal silicide layer 113 is formed on the surfaces of the junction region 102 and the conductive layer 105 by reacting the metal layer with the amorphous silicon layer by performing the above-described heat treatment process.

Hereinafter, the process of forming the metal silicide film 113 will be described in detail using the case of using cobalt as the metal film. In general, cobalt silicide comprises three polymorphs of an initial phase (Co ₂ Si), an intermediate phase (CoSi), and a final phase (CoSi ₂ ). The formation temperature of Co ₂ Si is 350 ° C to 500 ° C, the formation temperature of CoSi is 375 ° C to 500 ° C, and the formation temperature of CoSi ₂ is 550 ° C. That is, when the heat treatment step is performed, Co ₂ Si is first generated at the interface between the cobalt film and silicon. After all the cobalt film of phase change in the Co ₂ Si CoSi is generated in the Co ₂ Si and the silicon interface. After the entire Co ₂ Si phase transformation into CoSi, CoSi ₂ is formed again at the interface between CoSi and silicon. Conventionally, the heat treatment process was performed step by step to form a stable phase metal silicide film, but defects occurred during the phase transformation process, thereby becoming a problem. In the present invention, as described above with reference to FIG. 1E, since nitrogen ion implantation is implanted into the surface of the junction region 102 and the surface of the conductive layer 105, the cobalt silicide layer may be formed of CoSi ₂ , which is the most stable phase without phase change. As a result, the probability of occurrence of defects in the cobalt silicide layer is reduced, so that the cobalt silicide layer 113 may be stably formed. As such, the reason for forming the metal silicide layer 113 as the most stable phase without changing the phase is because silicon and nitrogen form a solid solution, thereby excluding abnormal compound formation.

In addition, the metal silicide layer 113 may be uniformly formed because the metal silicide is formed by reacting silicon in an amorphous state by a nitrogen ion implantation process. This is because the metal is uniformly and stably diffused in the silicon in the amorphous state compared to the crystallized silicon to form the metal silicide film 113. When the metal film is reacted with the silicon in an amorphous state, the metal may be easily diffused even after the oxide film is not completely removed and remains locally on the conductive film 105 after the cleaning process described above with reference to FIG. 1G. The silicide film 113 can be formed uniformly.

The above-described heat treatment process is preferably performed to minimize the volume change of the metal silicide layer 113 and to prevent the metal silicide layer 113 from growing laterally. In addition, the heat treatment process is preferably carried out for a temperature increase rate of 20 ℃ / min to 40 ℃ / min, temperature of 450 ℃ to 750 ℃, 10 seconds to 60 seconds.

When cobalt is applied to the metal film, a cobalt silicide film of CoSi ₂ , which is a stable phase, is formed through a heat treatment process, and the CoSi ₂ film has an advantage of having a resistance of 15 μΩ · cm or less.

When titanium is applied to the metal film, a titanium silicide film of TiSi ₂ , which is a stable phase, is formed through a heat treatment process. At this time, the nitrogen ions may promote the solid phase diffusion between the titanium atoms and the silicon atoms to control the formation thickness of the TiSi ₂ film within the thickness of the junction region 102 without aggregation. In particular, when titanium is applied, the TiSi ₂ film is formed by the solid phase diffusion reaction between titanium and nitrogen in a portion where the junction region 102 and the metal film are in contact with each other, and a metastable TiN phase may be formed on the TiSi ₂ film surface. Since the TiN having a dense structure can prevent the TiSi ₂ film below it from being exposed and oxidized, the resistance of the metal silicide film 113 can be further improved.

After the metal silicide layer 113 is formed, the metal layer that is not reacted with the amorphous silicon layer is removed by performing the cleaning process using the cleaning solution. As the washing solution, a mixture of NH ₄ OH (SC-1) and HCl can be used.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1G are diagrams for explaining a silicide film forming method of a semiconductor device according to the present invention;

<Description of the symbols for the main parts of the drawings>

101: semiconductor substrate 101a: first junction region

101b: second junction region 102: junction region of LDD structure

103: gate insulating film 105: conductive film

105a: gate pattern 107: spacer

109: etch stop film 111: metal film

113 metal silicide film 115 gate pattern

Claims (14)

Forming a gate insulating film and a polysilicon film on the semiconductor substrate; Etching the polysilicon layer and the gate insulating layer to form a stacked pattern; Implanting impurity ions into semiconductor substrates on both sides of the stacked pattern to form a junction region; Implanting ions which react with silicon to form a solid solution in the junction region and the polysilicon film; Forming a metal film on the junction region and the polysilicon film; And And forming a metal silicide film on the surface of the junction region and the surface of the polysilicon film by reacting the junction region and the silicon of the polysilicon film with the metal film. The method of claim 1, In the step of injecting ions forming a solid solution by reacting with the silicon into the junction region, the ion is implanted into the junction region and the polysilicon film and at the same time the surface of the junction region and the surface of the polysilicon film is amorphous Manufacturing method. The method of claim 1, A method of manufacturing a semiconductor device comprising ions reacting with silicon to form a solid solution comprising nitrogen. The method of claim 1, The metal film is a manufacturing method of a semiconductor device containing cobalt. The method of claim 4, wherein A method of manufacturing a semiconductor device in which a CoSi ₂ phase is formed over the entire region of the metal silicide film formed by the heat treatment process. The method of claim 1, The metal film is a method of manufacturing a semiconductor device containing titanium. The method of claim 6, And a TiSi ₂ phase is formed over the entire region of the metal silicide film formed by the heat treatment process. The method of claim 3, wherein The metal film includes titanium, The TiSi ₂ phase is formed in the whole area | region of the said metal silicide film formed by the said heat processing process, and the TiN film is formed on the surface of the said metal silicide film. The method of claim 1, After forming a junction region on the semiconductor substrate on both sides of the laminated pattern using the laminated pattern as a mask, Forming a spacer on sidewalls of the stacked pattern; And And forming a junction region of an LDD structure by implanting the impurity ions having a higher concentration than the junction region into the junction region using the stack pattern and the spacer as a mask. The method of claim 1, In the step of implanting ions forming a solid solution by reacting with the silicon ion implantation energy is a method of manufacturing a semiconductor device 5KeV to 15KeV. The method of claim 1, In the step of implanting ions reacting with the silicon to form a solid solution, the ion implantation angle is 2 ° to 4 ° manufacturing method of a semiconductor device. The method of claim 1, And implanting ions forming the solid solution by reacting with the silicon, wherein the ion implantation target depth (Rp) is between 20 kV and 40 kV. The method of claim 1, In the implantation of ions forming a solid solution by reacting with the silicon, the dose of the ions is 5 × 1013 Ions / ㎠ to 8 × 1013 Ions / ㎠. The method of claim 1, The heat treatment process is a method of manufacturing a semiconductor device is carried out for a temperature increase rate of 20 ℃ / min to 40 ℃ / min, a temperature of 450 ℃ to 750 ℃ and a time of 10 seconds to 60 seconds.

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