KR20090114110A - Method for fabricating the semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating the semiconductor device is provided to prevent the thickness of a spacer from being reduced in the cleaning process. CONSTITUTION: The gate pattern(220) is formed in the silicon substrate(200) in which the element isolation film(210) is formed. The first spacer(245) is formed in the gate pattern side wall of the peripheral circuit region. The silicon substrate of the peripheral circuit region is exposed. The second spacer(225a) of the thickness which is thinner than the thickness of the first spacer in the gate pattern side wall of the cell region is formed. The silicon substrate of the cell region is exposed. The selective epitaxial growth film is formed in the exposed silicon substrate of the cell region and peripheral circuit region.

Description

Method for manufacturing a semiconductor device {METHOD FOR FABRICATING THE SEMICONDUCTOR DEVICE}

The present invention relates to a method for manufacturing a semiconductor device. In particular, the present invention relates to a method for manufacturing a transistor of a semiconductor device having an elevated source / drain structure.

As semiconductor devices become more integrated, gate line widths of transistors decrease, junction regions become shallower, and ion implantation concentrations in junction regions increase.

In response to this trend of high integration, various techniques have been proposed for forming shallow source / drain junctions.

Examples thereof include a method of forming a junction by low energy ion implantation and a method of suppressing a channeling effect by a double ion implantation method using the same. However, these methods are still insufficient in identifying physical and chemical properties due to defects caused by implanted ions in order to form shallow junctions of a semiconductor device of 0.1 μm or less. In addition, there is a problem that the junction resistance increases as the junction region becomes shallow, and the reliability of the device is lowered due to etching damage when forming contact holes for contact between the junction region and the metal wiring.

Therefore, in recent years, as a method for forming a shallow junction, an escaped source / drain (Elevated Source Drain) using a selective epitaxial growth (SEG) method is removed from the conventional method of implanting ions into a silicon substrate. A structure has been proposed.

1A to 1E illustrate a method of manufacturing a semiconductor device according to the prior art.

Referring to FIG. 1A, the device isolation layer 110 is formed by etching and embedding the silicon substrate 100 in the cell region I and the peripheral circuit region II.

Next, the gate pattern 120 is formed on the silicon substrate 100. Here, the gate pattern 120 is formed in a stacked structure of the polysilicon layer 120a, the gate metal layer 120b, and the gate hard mask 120c.

Next, the nitride film 125 is deposited on the entire surface including the gate pattern 120. An oxide film (not shown) is further deposited on the nitride film 125.

Referring to FIG. 1B, after forming a first photoresist layer pattern (not shown) for opening the peripheral circuit region II, a front etching process is performed to form a first photoresist layer on the sidewall of the gate pattern 120 of the peripheral circuit region II. 1 Spacer 125a is formed. Here, the first spacer 125a is formed of a nitride film and an oxide film. In this case, the silicon substrate 100 of the peripheral circuit region II is exposed.

Next, the SEG film 130 is grown on the exposed silicon substrate 100.

1C and 1D, after removing the first photoresist layer pattern (not shown), an insulating layer 135 is formed at a height higher than that of the gate pattern 120 of the cell region I and the peripheral circuit region II. do.

Next, the planarization process is performed until the gate hard mask 120c on the gate pattern 120 is exposed. As a result, the nitride film 125 on the gate pattern 120 is removed.

Referring to FIG. 1E, a photoresist layer is formed on the planarized insulating layer 130, and a second photoresist layer pattern (not shown) is formed by performing exposure and development processes using a landing plug contact mask.

Next, the insulating layer 130 between the gate pattern 120 of the cell region I and the neighboring gate pattern 120 is etched using the second photoresist pattern (not shown) as a mask to make the landing plug contact hole 137. ).

In this case, the nitride film 125 on the sidewall of the gate pattern 120 is not etched to become the second spacer 125b and is formed on the silicon substrate 100 between the gate pattern 120 and the neighboring gate pattern 120. The nitride film 125 is completely removed to expose the silicon substrate 100 of the cell region I.

Next, the second photoresist pattern (not shown) is removed.

Next, a SEG film 140 is grown on the exposed silicon substrate 100 in the cell region I.

In the above-described method for manufacturing a semiconductor device according to the related art, since the steps of exposing the silicon surface in the cell region and the peripheral circuit region are different, there is a problem that the SEG film cannot be grown simultaneously in the cell region and the peripheral circuit region.

Therefore, when the growth process of the SEG film is carried out twice, since the process of 800 ° C. or more must be performed twice, the device characteristics are deteriorated by heat, and there is a problem of doubling the investment in terms of equipment investment.

In addition, a cleaning process is performed before the SEG film is grown, and an oxide film used as a spacer is removed during the cleaning process, thereby preventing the SEG film from growing and thinning the spacer.

According to the present invention, the SEG film growth process performed at a high temperature may be performed only once to reduce deterioration of devices and equipment investment due to thermal effects. In addition, while securing a landing plug contact open margin of the cell region, the gate pattern sidewall spacer of the peripheral circuit region may be sufficiently thick to secure a short channel margin. In addition, an object of the present invention is to provide a method of manufacturing a semiconductor device which prevents a phenomenon that the thickness of the spacer is reduced after a cleaning process before forming the SEG film by forming the spacer using only the nitride film.

Method for manufacturing a semiconductor device according to the present invention

Forming a gate pattern on the silicon substrate on which the device isolation layer is formed;

Forming a first spacer on sidewalls of the gate pattern of the peripheral circuit region, and exposing the silicon substrate of the peripheral circuit region;

Forming a second spacer on the sidewall of the gate pattern of the cell region, the second spacer having a thickness thinner than the thickness of the first spacer, and exposing the silicon substrate of the cell region;

Growing an SEG film on the exposed silicon substrate in the cell region and the peripheral circuit region,

The first spacer and the second spacer is formed of a nitride film,

Forming the first spacer

Forming a first nitride film on the gate pattern surface;

Forming an insulating film pattern on the cell region;

Forming a second nitride film on the insulating film pattern surface and the first nitride film surface of the peripheral circuit region;

Etching the first nitride film and the second nitride film by full etching;

Forming a height of the insulating layer pattern higher than that of the gate pattern;

Depositing an oxide film on a surface of the gate pattern on which the insulating film pattern and the first spacer are formed;

Forming the second spacer

Etching the first nitride layer by etching the entire surface after removing the insulating layer pattern;

Removing the insulating layer pattern by performing a dip-out process;

And performing a cleaning process after exposing the silicon substrate in the cell region.

In the method of manufacturing a semiconductor device according to the present invention, the SEG film growth process performed at a high temperature may be performed only once to reduce deterioration of the device and equipment investment due to thermal effects. In addition, while securing a landing plug contact open margin of the cell region, the gate pattern sidewall spacer of the peripheral circuit region may be sufficiently thick to secure a short channel margin. In addition, by forming the spacer using only the nitride film, there is an effect that can prevent the phenomenon that the thickness of the spacer is reduced after the cleaning process (Cleaning Process) before forming the SEG film.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Hereinafter, with reference to the accompanying drawings an embodiment of the present invention will be described in detail.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

Referring to FIG. 2A, the silicon substrate 200 including the cell region I and the peripheral circuit region II is etched to form a device isolation trench (not shown) defining an active region, and the device isolation trench. An oxide film is formed over the entire silicon substrate 200 including (not shown).

Next, a device isolation film 210 is formed by filling the device isolation trench (not shown) by a planarization process.

Next, a stacked structure of the gate polysilicon layer 220a, the gate metal layer 220b, and the gate hard mask layer 220c is formed on the silicon substrate 200. Here, the gate metal layer 220b is preferably formed of tungsten.

Next, the stacked structure is patterned to form a gate pattern 220. In this case, a plurality of gate patterns 220 are formed in the cell region I, and one gate pattern 220 is formed in the peripheral circuit region II.

The first nitride film 225 is deposited on the entire surface of the silicon substrate 200 including the gate pattern 220.

Referring to FIG. 2B, an insulating film 230 is formed on the silicon substrate 200. In this case, the insulating layer 230 is formed to be higher than the height of the gate pattern 220 so that the gate pattern 220 of the cell region I may be protected.

Here, the insulating film 230 is preferably formed of an oxide film.

Referring to FIG. 2C, an insulating film of the cell region I may be formed by forming a photoresist film (not shown) on the insulating film 230 and performing an exposure and development process using a mask that opens the peripheral circuit region II. 230, a first photoresist pattern (not shown) is formed on the upper portion.

Next, a dip-out process is performed using the first photoresist pattern (not shown) as a mask to remove the insulating layer 230 on the peripheral circuit region II. Here, the insulating film 230 remaining on the cell region I is defined as the insulating film pattern 230a.

Next, the first photoresist pattern (not shown) is removed.

Next, a second nitride film 235 is deposited on the insulating film pattern 230a and the gate pattern 220 of the peripheral circuit region II. In the gate pattern 220 of the peripheral circuit region II, since the second nitride layer 235 is deposited while the first nitride layer 225 is deposited, the gate pattern 220 of the cell region I is formed. The thickness becomes thicker than the nitride film formed on the surface.

Referring to FIG. 2D, an etching back process is performed.

The second nitride layer 235 on the surface of the insulating layer pattern 230a is removed by the entire surface etching. The first spacer 245 including the first nitride film 225 and the second nitride film 235 is formed on the sidewall of the gate pattern 120 of the peripheral circuit region II.

Here, since the cell region I is covered with the insulating layer pattern 230a, the second nitride layer 235 is not deposited on the sidewall of the gate pattern 220 of the cell region I. Accordingly, the short channel is increased by increasing the thickness of the first spacer 245 of the gate pattern 220 of the peripheral circuit region II while securing an area of a landing plug contact region of the cell region I. A short channel margin can be obtained.

In addition, since the first spacer 245 is made of only a nitride film, the thickness of the first spacer 245 may be prevented in a subsequent cleaning process.

In this case, the first spacer 245 is formed on the sidewall of the gate pattern 220 of the peripheral circuit region II to expose the silicon substrate 200.

Next, an oxide film 250 is deposited on the entire surface including the insulating film pattern 230a and the gate pattern 220 of the peripheral circuit region II. Here, since the oxide film 250 is in direct contact with the silicon substrate 200 exposed to the peripheral circuit region II when the photoresist pattern subsequently opens the cell region I, the silicon substrate ( It is preferable to form to protect the 200).

Referring to FIG. 2E, a mask is formed on the insulating layer pattern 230a deposited on the oxide layer 250 and the photoresist layer on the gate pattern 220 of the peripheral circuit region II, and opens the cell region I. An exposure and development process is performed to form a second photoresist pattern (not shown) that opens the cell region (I). Although not shown in the drawings, a space is separated between the first photoresist pattern (not shown) for opening the peripheral circuit region (II) and the second photoresist pattern (not shown) for opening the cell region (I). In this case, since the lower device isolation layer 210 may be damaged by two dip outs, the mask for opening the cell region I may be the peripheral circuit region II of FIG. 2A. You can also proceed to overlap the mask that opens.

Next, a dip-out process using the second photoresist pattern (not shown) as a mask is performed to remove the insulating layer pattern 230a of the cell region I. In this case, the oxide film 250 formed to protect the silicon substrate 200 of the peripheral circuit region II is also removed during the dip out process.

Next, an entire surface etching process is performed to form a second spacer 225a formed of the first nitride layer 225 on the sidewall of the gate pattern 220 of the cell region (I). As a result, the silicon substrate 200 between the gate pattern 220 and the neighboring gate pattern 220 is exposed.

Next, the second photoresist layer pattern (not shown) is removed to expose the silicon substrate 200 in the cell region I and the peripheral circuit region II. Here, the silicon substrate 200 is exposed between the gate pattern 220 of the cell region I and the neighboring gate pattern 220, and the silicon substrate is disposed on both sides of the gate pattern 220 of the peripheral circuit region II. 200 is exposed.

Referring to FIG. 2F, after a pre-cleaning process, a silicon layer of the exposed silicon substrate 200 is grown to form a selective epitaxial growth (SEG) layer 260. Here, since the silicon substrate 200 of the cell region I and the peripheral circuit region II are simultaneously exposed, the process of growing the SEG film 260 may be performed at once.

Therefore, it is possible to prevent thermal damage by the high temperature thermal process that is performed while growing the SEG film 260, and to reduce the investment of equipment.

1A to 1E are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A to 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

<Explanation of Signs of Major Parts of Drawings>

200: silicon substrate 210: device isolation film

220: gate pattern 225: first nitride film

225a: second spacer 230: insulating film

230a: insulating film pattern 245: first spacer

250: oxide film 260: SEG film

Claims (8)

Forming a gate pattern on the silicon substrate on which the device isolation layer is formed; Forming a first spacer on sidewalls of the gate pattern of the peripheral circuit area and exposing the silicon substrate of the peripheral circuit area; Forming a second spacer on the sidewall of the gate pattern of the cell region, the second spacer having a thickness thinner than the thickness of the first spacer, and exposing the silicon substrate of the cell region; And Growing an SEG film on the exposed silicon substrate in the cell region and the peripheral circuit region; Method of manufacturing a semiconductor device comprising a. The method of claim 1, And the first spacer and the second spacer are formed of a nitride film. The method of claim 1, Forming the first spacer Forming a first nitride film on the gate pattern surface; Forming an insulating film pattern on the cell region; Forming a second nitride film on the insulating film pattern surface and the first nitride film surface of the peripheral circuit region; And And etching the first nitride film and the second nitride film by etching the entire surface. The method of claim 3, wherein The height of the insulating film pattern is formed higher than the height of the gate pattern manufacturing method of a semiconductor device. The method of claim 3, wherein And depositing an oxide film on a surface of the gate pattern having the insulating layer pattern and the first spacer formed thereon. The method of claim 3, wherein Forming the second spacer And removing the insulating layer pattern to form the first nitride layer by etching the entire surface. The method of claim 5, wherein And removing the insulating film pattern by performing a dip-out process. The method of claim 1, And performing a cleaning process after exposing the silicon substrate in the cell region.

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