KR20090111481A - Method for manufacturing columnar poly silicon gate and method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a columnar poly silicon gate and a method for manufacturing a semiconductor device are provided to satisfy the poly silicon depletion rate characteristic of NMOS without adding the ion injection process. CONSTITUTION: A method for manufacturing a columnar poly silicon gate and a method for manufacturing a semiconductor device are as follows. A columnar poly silicon layer(41) in which the first conductivity type dopant is doped in formed. The columnar poly silicon layer is counter-doped using a cluster in which the second conductive impurities are contained. The first conductivity type dopant and the second conductivity type dopant are thermally treated with activation.

Description

METHOD FOR MANUFACTURING COLUMNAR POLY SILICON GATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method, and to a polysilicon gate manufacturing method and a semiconductor device manufacturing method using the same.

Recently, memory devices such as DRAMs form a multi-channel transistor having a multi-sided channel such as a recess channel in a cell region, and a planar channel transistor in a peripheral circuit region. In the peripheral circuit region, a CMOS process for simultaneously forming an NMOS transistor and a PMOS transistor is applied.

When the cell region proceeds to the gate structure having the recess channel, a converted scheme is applied in the peripheral circuit region to form gate electrodes of the NMOS transistor and the PMOS transistor. The converted method is a counter doping method in which a polysilicon film doped with N-type impurities is doped with P-type impurities such as boron. Accordingly, an N-type polysilicon film and a P-type polysilicon film used as the gate electrode may be formed, respectively, and are called 'dual poly silicon gates'.

However, the general dual polygate has a polysilicon depletion effect (PDE) in which dopants doped in the polysilicon film are out-diffused in a subsequent process and depletion occurs at the interface between the gate insulating film and the polysilicon film. Cause.

In order to suppress the polysilicon depletion phenomenon (PDE) as described above, a polysilicon film having a columnar structure (Columnar) has been proposed (abbreviated as 'column polysilicon film').

1 is a view showing the structure of a dual polysilicon gate according to the prior art.

Referring to FIG. 1, a gate insulating film 12 is formed on a substrate 11 in which an NMOS region and a PMOS region are divided.

An N-type polysilicon film (N ⁺ C-Poly, 13) is formed on the gate insulating film 12 in the NMOS region, and a P-type polysilicon film (P ⁺ C-Poly, 14) on the gate insulating film 12 in the PMOS region. ) Is formed. The N-type polysilicon film 13 and the P-type polysilicon film 14 are each doped with N-type impurities and P-type impurities in high concentrations, and have crystal grains of columnar structure. Accordingly, the polysilicon film having a columnar structure doped with N-type impurities at high concentration is called 'N ⁺ C-Poly', and the polysilicon film having a high concentration doped P-type impurity is called 'P ⁺ C-Poly'.

Unlike the polysilicon film obtained by heat treatment of the amorphous silicon film or a conventional polysilicon film, the polysilicon film having a columnar structure does not have a change in grain size even when exposed to subsequent thermal process. Therefore, by using a polysilicon film having a columnar structure, it is possible to ensure a uniform impurity concentration at the interface between the surface and the gate insulating film. As a result, a high impurity concentration can be ensured even at the interface between the polysilicon film and the gate insulating film, so that both NMOS and PMOS can suppress polysilicon depletion.

However, when a polysilicon film having a columnar structure is applied to the gate electrode of the PMOS, impurity penetrating phenomenon such as boron (reference numeral '15') is deteriorated. For example, a boron penetration phenomenon in which boron doped in the P-type polysilicon film 14 penetrates the thin gate insulating film 12 and is diffused into the channel region while a subsequent thermal process is performed. Cause. In particular, in the polysilicon film having a columnar structure, channeling easily penetrates the gate insulating film 12 due to the characteristics of the columnar crystal grains, and the boron penetration phenomenon is deteriorated by the channeling.

Such boron penetration causes a drop in carrier mobility in the channel region, causing threshold voltage fluctuations.

The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a polysilicon gate manufacturing method capable of minimizing impurity penetration while suppressing polysilicon depletion (PDR).

Another object of the present invention is to provide a method for forming a dual polysilicon gate capable of minimizing impurity penetration of a P-type polygate while satisfying the polysilicon depletion rate of the N-type polygate, and a method of manufacturing a semiconductor device using the same. .

Polysilicon gate manufacturing method for achieving the above object comprises the steps of forming a columnar polysilicon film doped with a first conductivity type impurities; Counter doping the columnar polysilicon layer using a cluster containing a second conductive impurity; And an activation heat treatment step of the first conductive impurity and the second conductive impurity.

In addition, the method of manufacturing a dual polysilicon gate of the present invention includes forming a columnar polysilicon film doped with a first conductive impurity on a front surface of a substrate in which first and second regions are defined; Counter-doping the columnar polysilicon film of the second region using a cluster containing a second conductive impurity; And an activation heat treatment stage of the first conductive impurity and the second conductive impurity.

The semiconductor device manufacturing method may further include forming a multi-channel pattern in the cell region of the substrate in which a cell region and a peripheral circuit region are defined; Forming a gate insulating film on the entire surface of the substrate; Forming a columnar polysilicon film doped with N-type impurities on the gate insulating film; Counter doping the columnar polysilicon film of the peripheral circuit region by using a cluster containing P-type impurities; And activation heat treatment of the N-type and P-type impurities.

Preferably, the cluster comprises a boron hydride cluster, the boron hydride cluster is characterized in that it comprises an octade caborene (B ₁₈ H ₂₂ ).

Preferably, the counter doping using the cluster is characterized in that the dose is 1E16 ~ 4E16 atoms / cm ² , the energy is 60 ~ 90keV, the inclined incident angle is 0 to 7 °.

The present invention has an effect of obtaining a P-type polysilicon gate in which impurity penetration and polysilicon depletion are suppressed by using a polysilicon film having a columnar structure and a cluster doping method.

In addition, the present invention uses a columnar polysilicon film having excellent impurity distribution at the interface between the N-type polysilicon gate and the gate insulating film, so that even if an ion implantation ('NPG Imp') process is not added to secure a high concentration, polysilicon balls of NMOS It can satisfy the pip rate characteristic.

In addition, the present invention has the effect of obtaining a planarized polysilicon gate by applying the CMP process to the polysilicon film.

In the present invention, a cluster doping method using a boron hydride cluster is applied as an ion implantation impurity for forming a P-type polysilicon gate. The boron hydride cluster includes octadecarborene (B ₁₈ H ₂₂ ).

Octadecarborene (B ₁₈ H ₂₂ ) is a substance having significantly higher molecular weight than 11B, 49BF ₂ , and BF ₃ . Therefore, compared with the case of using 11B, 49BF ₂ , and BF ₃ , the ion implantation current (Implant beam current) can be significantly increased. As a result, when octadecarborene (B ₁₈ H ₂₂ ) is used, the ion implantation time is considerably shortened, thereby greatly improving the through-put. For example, when octadecarborene (B ₁₈ H ₂₂ ) is used, the dose is reduced by about one-twentieth as compared with 11B, 49BF ₂ , and BF ₃ , and the productivity is greatly improved by that amount.

In addition, in the case of BF ₃ and 49BF _2, the deterioration of characteristics of the device was caused due to boron penetration by fluorine, but in the case of octadecarbonene (B ₁₈ H ₂₂ ) used in the present invention, it contained fluorine. Therefore, boron penetration caused by fluorine does not occur. This improves the reliability and product yield of the device compared with the case of using BF ₃ , 49BF ₂ .

As a result, the present invention adopts a cluster doping method as an ion implantation method for forming a P-type polysilicon gate, and by using a boron hydride cluster such as octadecarbonene (B ₁₈ H ₂₂ ) as a cluster, In addition to greatly improving mass productivity, it is possible to implement a highly reliable device by suppressing boron infiltration.

When the impurities are doped by the cluster doping method, boron penetration can be suppressed even in the columnar polysilicon film structure. Meanwhile, when doping impurities 11B, 49BF ₂ , and BF ₃ by plasma doping and beamline implants, boron penetration is caused by channeling due to the columnar structure. There is.

2A to 2D are cross-sectional views illustrating a method of manufacturing a polysilicon gate according to a first embodiment of the present invention.

As shown in FIG. 2A, a gate insulating film 22 is formed on a substrate 21 such as a silicon substrate. The gate insulating layer 22 may include a silicon oxide layer (SiO ₂ ) formed through thermal oxidation or a silicon oxynitride layer (SiON) in which nitrogen is injected into the silicon oxide layer. The silicon oxynitride film may be formed by nitriding through a plasma nitridation method after forming the silicon oxide film. Forming the silicon oxynitride film as described above has an effect of partially suppressing boron penetration.

The polysilicon film 23 is formed on the gate insulating film 22. Preferably, when the polysilicon film 23 is deposited, the chemical vapor deposition method is performed in a single wafer type chamber or a furnace. Deposition temperature is in the range of 680 ~ 800 ℃, formed by injecting silicon source gas SiH ₄ (50sccm) and N-type impurity gas PH ₃ (280 ~ 600sccm), may be further injected by H ₂ (2000sccm) have. At this time, the pressure is 10 mTorr to 500 mTorr (preferably 50 mTorr), the deposition time is within 100 seconds (preferably 10 seconds to 100 seconds), and the thickness is 500 to 1000 kPa. As the PH ₃ gas is introduced as the doping gas, phosphorus (P) in the polysilicon layer 23 may be doped in situ with a concentration of 4E20 to 6E20 atoms / cm ³ .

As described above, since phosphorus (Ph) is doped, an N-type polysilicon film is formed, and at the same time, the film is deposited at a temperature in the range of 680 to 800 ° C., so that the crystal grain is an N-type polysilicon film having a columnar structure. Hereinafter, the polysilicon film 23 is abbreviated as "N-type columnar polysilicon film (N ⁺ C-poly, 23)". The crystal grain C of the columnar structure has a structure doped in the direction of the arrow.

An amorphous silicon film has a structure in which grains and grain boundaries do not exist because of lack of regularity of the arrangement of silicon atoms, and a single crystal silicon film is a silicon film made of one grain having a regular atomic arrangement, and polysilicon ( polysilicon) refers to a silicon film in which a plurality of crystal grains are collected. The crystal structure of polysilicon may have a columnar structure depending on the shape of the crystal grains, and the columnar structure may be obtained by depositing at a temperature range of 680 to 800 ° C. An amorphous silicon film is deposited at a temperature of 500 ° C. or lower, and a conventional polysilicon film is obtained by heat-treating the amorphous silicon film.

The polysilicon film having a columnar structure exhibits a different behavior with respect to the diffusion of impurities from the polysilicon film obtained by heat-treating the amorphous silicon film.

Since the N-type columnar polysilicon film 23 has a columnar structure and is deposited, even if a subsequent thermal process (for example, a PIA process for activating impurities) proceeds, the grain size changes little. In other words, the N-type columnar polysilicon film 23 is a structurally stable polysilicon film having an as-deposition of polycrystal and no change in grain size due to subsequent heat treatment. In addition, the N-type columnar polysilicon film 23 has better step coverage than the amorphous silicon film.

As shown in Fig. 2B, the N-type columnar polysilicon film 23 is doped with P-type impurities. As such, the method of doping the second conductive impurity (P-type impurity) to the material doped with the first conductive impurity (N-type impurity) is called counter doping. In the case of counter doping, plasma doping (PLAMA) or cluster doping (Cluster doping) is applied in consideration of mass productivity. Preferably, the counter doping is applied to the cluster doping method, the cluster doping method is superior in mass productivity compared to the plasma doping method and beamline ion implantation (Beamline implant). The cluster doping method is excellent in mass productivity because it is capable of oblique incidence (Tilt, refer to 'T') and is capable of doping impurities at a concentration sufficiently required even at a low dose.

P-type impurities implanted through the cluster doping method include boron hydride (B _n H _x , n and x are natural numbers) clusters. For example, the boron hydride cluster uses Octadecaborane (B ₁₈ H ₂₂ ). Octadecarborene uses about one-half dose than 11B, 49BF _2, and BF ₃ , which are commonly used as boron sources, so that the beam current increases to increase productivity. In addition, since there is no fluorine effect (Fluorine effect) occurred in 49BF ₂ and BF ₃ boron penetration is suppressed.

When the cluster doping method is applied, the dose is 1E16 to 4E16 atoms / cm ² , the energy is 60 to 90 keV, and the inclined incident angle is 0 to 7 °.

By the above counter doping, the N-type columnar polysilicon film is converted into a P-type columnar polysilicon film (P ⁺ C-Poly, 23A).

As shown in FIG. 2C, chemical mechanical polishing (CMP) is performed to planarize the surface of the P-type columnar polysilicon film 23A. Through this planarization, the damage layer generated by the cluster doping method can be removed, and the surface of the P-type columnar polysilicon film 23A can be smoothed. Flattening can ensure a uniform thickness.

Subsequently, PIA (Post Implant Annealing) process is performed. The PIA process is performed by a rapid thermal process (RTP). As a result, the P-type impurities injected into the P-type polysilicon film 23A are activated. Preferably, the PIA process is performed using N ₂ alone at a temperature of 950-1000 ° C. or is performed for 20 seconds in an O ₂ dilution atmosphere.

The amorphous silicon film is converted to a polysilicon film after the PIA process, and the grain size increases to 800 Å. However, the polysilicon film having a columnar structure has a crystal grain size of 200-300 Å, which is much smaller than that of the amorphous silicon film. In this way, since there is no change in crystal grain size, the use of a polysilicon film having a columnar structure facilitates diffusion of impurities, thereby ensuring a uniform impurity concentration over the entire area of the polysilicon film. As a result, a high impurity concentration can be ensured even at the interface between the polysilicon film and the gate insulating film, thereby reducing the polysilicon depletion phenomenon.

On the other hand, the polysilicon film obtained by heat-treating the amorphous silicon film is more difficult to diffuse impurities than the polysilicon film of columnar structure, and thus it is difficult to secure a sufficiently high impurity concentration at the interface between the polysilicon film and the gate insulating film. That is, in the polysilicon film obtained by heat-treating the amorphous silicon film, the impurity concentration varies depending on the thickness, and in particular, the polysilicon depletion phenomenon is increased because the concentration is small at the portion in contact with the gate insulating film. In other words, the polysilicon depletion phenomenon causes the amorphous silicon film to have a larger grain size or a smaller grain boundary when the PIA process is performed, thereby reducing the amount of impurities diffused into the interface between the polysilicon film and the gate insulating film.

As shown in FIG. 2D, the P-type columnar polysilicon layer 23A is etched through a gate etching process to form a P-type polysilicon gate (P ⁺ C-Poly, 23B). The gate etching process may be performed after the low resistance metal film 24 such as tungsten and the hard mask film 25 such as silicon nitride are laminated on the P-type polysilicon film. A diffusion barrier film may be positioned between the low resistance metal film 24 and the P-type polysilicon gate 23B.

The P-type polysilicon gate 23B formed as above is used as the gate electrode of the PMOS transistor.

In a subsequent process, ion implantation to form the source / drain (P ⁺ -S / P ⁺ -D, 26) may proceed.

According to the first embodiment described above, the concentration of impurities required at the interface between the P-type columnar polysilicon film 23A and the gate insulating film 22 can be sufficiently secured by simultaneously applying the columnar polysilicon film and the cluster doping method. . This suppresses polysilicon depletion. In addition, since boron hydride clusters containing no fluorine are used, boron penetration is fundamentally prevented.

3A to 3D are cross-sectional views illustrating a method of manufacturing a dual polysilicon gate according to a second embodiment of the present invention.

As shown in FIG. 3A, the gate insulating layer 32 is formed on the substrate 31 in which the NMOS region and the PMOS region are defined. The substrate 31 includes a silicon substrate. The gate insulating layer 32 may include a silicon oxide layer (SiO ₂ ) formed by thermal oxidation or a silicon oxynitride layer (SiON) in which nitrogen is injected into the silicon oxide layer. The silicon oxynitride film may be formed by nitriding through a plasma nitridation method after forming the silicon oxide film. Forming the silicon oxynitride film as described above has an effect of partially suppressing boron penetration.

The polysilicon film 33 is formed on the gate insulating film 32. Preferably, the polysilicon film 33 is deposited by chemical vapor deposition in a single wafer type chamber or a furnace. The deposition temperature is in the range of 680 to 800 ° C., formed by injecting SiH ₄ (50 sccm), a silicon source gas, and PH ₃ (280 to 600 sccm), an N-type impurity gas, and proceeding by further injecting H ₂ (2000 sccm). have. At this time, the pressure is 10 mTorr to 500 mTorr (preferably 50 mTorr), the deposition time is within 100 seconds (preferably 10 seconds to 100 seconds), and the thickness is 500 to 1000 kPa. As the PH ₃ gas is introduced as the doping gas, phosphorus (P) in the polysilicon film 23 may be doped in situ with a concentration of 4E20 to 6E20 atoms / cm ³ .

As described above, since phosphorus (Ph) is doped, an N-type polysilicon film is formed, and at the same time, the film is deposited at a temperature in the range of 680 to 800 ° C., so that the crystal grain is an N-type polysilicon film having a columnar structure. Hereinafter, the polysilicon film 33 is abbreviated as "N-type columnar polysilicon film (N ⁺ C-poly, 33)".

An amorphous silicon film has a structure in which grains and grain boundaries do not exist because of lack of regularity of the arrangement of silicon atoms, and a single crystal silicon film is a silicon film made of one grain having a regular atomic arrangement, and polysilicon ( polysilicon) refers to a silicon film in which a plurality of crystal grains are collected. The crystal structure of polysilicon may have a columnar structure depending on the shape of the crystal grains, which can be obtained by depositing at a temperature range of 680 to 800 ° C.

The polysilicon film having a columnar structure exhibits a different behavior with respect to the diffusion of impurities from the polysilicon film obtained by heat-treating the amorphous silicon film.

Since the N-type columnar polysilicon film 33 has a columnar structure and is deposited, even if a subsequent thermal process (for example, a PIA process for activating impurities) is performed, the grain size changes little. In other words, the N-type columnar polysilicon film 23 is a structurally stable polysilicon film having an as-deposition of polycrystal and no change in grain size due to subsequent heat treatment. In addition, the N-type columnar polysilicon film 23 has better step coverage than the amorphous silicon film.

As shown in FIG. 3B, a photosensitive film is coated on the N-type columnar polysilicon film 33, exposed, and developed to form a photosensitive film pattern 34. The photosensitive film pattern 34 covers the upper portion of the N-type columnar polysilicon film 33 in the NMOS region and exposes the surface of the N-type columnar polysilicon film 33 in the PMOS region.

Next, the P-type impurity is doped into the N-type columnar polysilicon film 33 in the exposed PMOS region. The method of doping P-type impurities in the polysilicon film doped with N-type impurities is called counter-doping. In the case of counter doping, plasma doping (PLAMA) or cluster doping (Cluster doping) is applied in consideration of mass productivity. Preferably, the counter doping is applied to the cluster doping method, the cluster doping method is superior in mass productivity compared to the plasma doping method and beamline ion implantation (Beamline implant). The cluster doping method is excellent in mass productivity because it is capable of oblique incidence (Tilt, refer to 'T') and is capable of doping impurities at a concentration sufficiently required even at a low dose.

P-type impurities implanted through the cluster doping method include boron hydride (B _n H _x ) clusters. For example, the boron hydride cluster uses Octadecaborane (B ₁₈ H ₂₂ ). Octadecarborene uses about one-half dose than 11B, 49BF ₂ , and BF ₃ , which are commonly used as a boron source, so that the beam current increases to increase productivity. In addition, since there is no fluorine effect (Fluorine effect) occurred in 49BF ₂ and BF ₃ boron penetration is suppressed.

When the cluster doping method is applied, the dose is 1E16 to 4E16 atoms / cm ² , the energy is 60 to 90 keV, and the inclined incident angle is 0 to 7 °.

By the above counter doping, the N-type columnar polysilicon film in the PMOS region is converted into a P-type columnar polysilicon film (P ⁺ C-Poly, 35). The N-type columnar polysilicon film 33 remains in the NMOS region.

As shown in FIG. 3C, chemical mechanical polishing (CMP) is performed to planarize the surfaces of the N-type and P-type columnar polysilicon films 33 and 35. Through this planarization, the damage layer generated by the cluster doping method can be removed, and the surfaces of the N-type and P-type columnar polysilicon films 33 and 35 can be smoothed. Flattening can ensure a uniform thickness.

Subsequently, PIA (Post Implant Annealing) process is performed. The PIA process is performed by a rapid thermal process (RTP). As a result, the P-type impurities injected into the P-type columnar polysilicon film 35 are activated. Preferably, the PIA process is performed using N ₂ alone at a temperature of 950-1000 ° C. or is performed for 20 seconds in an O ₂ dilution atmosphere.

The amorphous silicon film is converted to a polysilicon film after the PIA process, and the grain size increases to 800 Å. However, the polysilicon film having a columnar structure has a crystal grain size of 200-300 Å, which is much smaller than that of the amorphous silicon film. In this way, since there is no change in crystal grain size, the use of a polysilicon film having a columnar structure facilitates diffusion of impurities, thereby ensuring a uniform impurity concentration over the entire area of the polysilicon film. As a result, a high impurity concentration can be ensured even at the interface between the polysilicon film and the gate insulating film, thereby reducing the polysilicon depletion phenomenon.

On the other hand, the polysilicon film obtained by heat-treating the amorphous silicon film is more difficult to diffuse impurities than the polysilicon film of columnar structure, and thus it is difficult to secure a sufficiently high impurity concentration at the interface between the polysilicon film and the gate insulating film. That is, in the polysilicon film obtained by heat-treating the amorphous silicon film, the impurity concentration varies depending on the thickness, and in particular, the polysilicon depletion phenomenon is increased because the concentration is small at the portion in contact with the gate insulating film. In other words, the polysilicon depletion phenomenon causes the amorphous silicon film to have a larger grain size or a smaller grain boundary when the PIA process is performed, thereby reducing the amount of impurities diffused into the interface between the polysilicon film and the gate insulating film.

As shown in FIG. 3D, the N-type columnar polysilicon film 33 and the P-type columnar polysilicon film 35 are etched through the gate etching process, respectively, to form the N-type polysilicon gate 33A and the P-type polysilicon gate. It forms 35A. The gate etching process may be performed after laminating a low resistance metal film 36 such as tungsten and a hard mask film 37 such as silicon nitride. A diffusion barrier film may be positioned between the low resistance metal film 36 and each of the polysilicon gates 33A and 35A.

The N-type polysilicon gate 33A formed as above is used as the gate electrode of the NMOS transistor, and the P-type polysilicon gate 35A is used as the gate electrode of the PMOS transistor. The N-type polysilicon gate 33A and the P-type polysilicon gate 35A become dual polysilicon gates.

In a subsequent process, ion implantation may be performed to form a source / drain corresponding to each transistor.

According to the second embodiment described above, the impurity concentration required at the interface between the P-type columnar polysilicon film and the gate insulating film can be sufficiently secured by applying the cluster doping method while using the columnar polysilicon film. Accordingly, an effect of reducing polysilicon depletion may be obtained. In addition, by using an N-type columnar polysilicon film having excellent impurity distribution at the interface between the polysilicon film and the gate insulating film, an ion implantation ('NPG Imp') process for securing high concentrations in the NMOS region and the cell region is not required. Polysilicon depletion rate characteristics can be satisfied. In addition, since boron hydride clusters containing no fluorine are used, boron penetration is fundamentally prevented.

4A through 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.

As shown in FIG. 4A, a recess pattern 42 is formed in a cell region of a substrate 41 in which a cell region in which an NMOS is to be formed and a peripheral circuit region in which an NMOS and a PMOS are simultaneously formed are defined. Here, the cell region may be a region where an NMOS having a recess type recess channel is to be formed, and the peripheral circuit region may be a region where an NMOS and a PMOS having a planar channel are formed. The substrate 41 includes a silicon substrate.

As shown in FIG. 4B, a gate insulating film 43 is formed on the substrate 41. The gate insulating layer 43 may include a silicon oxide layer (SiO ₂ ) formed through thermal oxidation or a silicon oxynitride layer (SiON) in which nitrogen is injected into the silicon oxide layer. The silicon oxynitride film may be formed by nitriding through a plasma nitridation method after forming the silicon oxide film. Forming the silicon oxynitride film as described above has an effect of partially suppressing boron penetration.

Subsequently, the polysilicon film 44 is formed on the entire surface until the recess pattern is gap filled. Preferably, when the polysilicon film 44 is deposited, chemical vapor deposition is performed in a single wafer type chamber or a furnace. Deposition temperature is in the range of 680 ~ 800 ℃, formed by injecting silicon source gas SiH ₄ (50sccm) and N-type impurity gas PH ₃ (280 ~ 600sccm), may be further injected by H ₂ (2000sccm) have. At this time, the pressure is set to 10 mTorr to 500 mTorr (preferably 50 mTorr), the deposition time is within 100 seconds (preferably 10 seconds to 100 seconds), and the thickness is set to 500 to 1000 kPa. As the PH ₃ gas is introduced as the doping gas, phosphorus (P) in the polysilicon film 23 may be doped in situ with a concentration of 4E20 to 6E20 atoms / cm ³ .

As described above, since phosphorus (Ph) is doped, an N-type polysilicon film is formed, and at the same time, the film is deposited at a temperature in the range of 680 to 800 ° C., so that the crystal grain is an N-type polysilicon film having a columnar structure. Hereinafter, the polysilicon film 44 is abbreviated as "N-type columnar polysilicon film (N ⁺ C-poly, 44)".

An amorphous silicon film has a structure in which grains and grain boundaries do not exist because of lack of regularity of the arrangement of silicon atoms, and a single crystal silicon film is a silicon film made of one grain having a regular atomic arrangement, and polysilicon ( polysilicon) refers to a silicon film in which a plurality of crystal grains are collected. The crystal structure of polysilicon may have a columnar structure depending on the shape of the crystal grains, and the columnar structure may be obtained by depositing at a temperature range of 680 to 800 ° C.

The polysilicon film having a columnar structure exhibits a different behavior with respect to the diffusion of impurities from the polysilicon film obtained by heat-treating the amorphous silicon film.

Since the N-type columnar polysilicon film 44 has a columnar structure and is deposited, even if a subsequent thermal process (eg, a PIA process for activating impurities) is performed, the grain size is less changed. In other words, the N-type columnar polysilicon film 44 is a structurally stable polysilicon film in which the as-deposition is polycrystalline and no change in grain size occurs by subsequent heat treatment. Therefore, even if a seam is generated when the recess pattern 42 is filled, expansion and movement of the seam does not occur in a subsequent thermal process. In addition, the N-type columnar polysilicon film 44 has better step coverage than the amorphous silicon film.

As shown in FIG. 4C, a photosensitive film is coated on the N-type columnar polysilicon film 44, exposed, and developed to form a photosensitive film pattern 45. The photosensitive film pattern 45 covers the upper portion of the N-type columnar polysilicon film 44 in the cell region and the NMOS region and exposes the surface of the N-type columnar polysilicon film 44 in the PMOS region.

Next, the P-type impurity is doped into the N-type polysilicon film 44 in the exposed PMOS region. The method of doping P-type impurities in the polysilicon film doped with N-type impurities is called counter-doping. In the case of counter doping, plasma doping (PLAMA) or cluster doping (Cluster doping) is applied in consideration of mass productivity. Preferably, the counter doping is applied to the cluster doping method, the cluster doping method is superior in mass productivity compared to the plasma doping method and beamline ion implantation (Beamline implant). The cluster doping method is excellent in mass productivity because it is capable of oblique incidence (Tilt, refer to 'T') and is capable of doping impurities at a concentration sufficiently required even at a low dose.

P-type impurities implanted through the cluster doping method include boron hydride (B _n H _x ) clusters. For example, the boron hydride cluster uses Octadecaborane (B ₁₈ H ₂₂ ). Octadecarborene uses about one-half dose than 11B and 49BF ₂ , which are commonly used as a boron source, so that the beam current increases to increase productivity. In addition, since there is no fluorine effect (Fluorine effect) occurred in 49BF ₂ boron penetration is suppressed.

When the cluster doping method is applied, the dose is 1E16 to 4E16 atoms / cm ² , the energy is 60 to 90 keV, and the inclined incident angle is 0 to 7 °.

By the above counter doping, the N-type columnar polysilicon film in the PMOS region is converted into the P-type columnar polysilicon film 46. Here, the N-type columnar polysilicon film 44 remains in the cell region and the NMOS region as it is.

As shown in FIG. 4D, after the photoresist pattern is removed, chemical mechanical polishing (CMP) is performed to planarize the surface of the polysilicon layer. Through this planarization, the damage layer generated by the cluster doping method can be removed, and the surface of the polysilicon film can be smoothed. Flattening can ensure a uniform thickness.

Subsequently, PIA (Post Implant Annealing) process is performed. The PIA process is performed by a rapid thermal process (RTP). As a result, impurities injected into the P-type columnar polysilicon film 46 and the N-type columnar polysilicon film 44 are activated. Preferably, the PIA process is performed using N ₂ alone at a temperature of 950-1000 ° C. or is performed for 20 seconds in an O ₂ dilution atmosphere.

The amorphous silicon film is converted to a polysilicon film after the PIA process, and the grain size increases to 800 Å. However, the polysilicon film having a columnar structure has a crystal grain size of 200-300 Å, which is much smaller than that of the amorphous silicon film.

In this way, since there is no change in crystal grain size, the use of a polysilicon film having a columnar structure facilitates diffusion of impurities, thereby ensuring a uniform impurity concentration over the entire area of the polysilicon film. As a result, a high impurity concentration can be ensured even at the interface between the P-type columnar polysilicon film 46 and the gate insulating film 43, thereby reducing the polysilicon depletion phenomenon. On the other hand, the polysilicon film obtained by heat-treating the amorphous silicon film is more difficult to diffuse impurities than the polysilicon film of columnar structure, and thus it is difficult to secure a sufficiently high impurity concentration at the interface between the polysilicon film and the gate insulating film. That is, in the polysilicon film obtained by heat-treating the amorphous silicon film, the impurity concentration varies depending on the thickness, and in particular, the polysilicon depletion phenomenon is increased because the concentration is small at the portion in contact with the gate insulating film.

On the other hand, in the case of the amorphous silicon film, the PIA process causes a polysilicon depletion phenomenon that the grain size becomes larger or the grain size becomes smaller, so that the amount of impurities diffused to the interface between the polysilicon film and the gate insulating film decreases.

As shown in FIG. 4E, the N-type columnar polysilicon film 44 and the P-type columnar polysilicon film 46 are etched through the gate etching process, respectively, to form the N-type polysilicon gate 44A and the P-type polysilicon gate. It forms 46A. Meanwhile, the gate etching process may be performed after laminating a low resistance metal film 47 such as tungsten and a hard mask film 48 such as a silicon nitride film. A diffusion barrier film may be positioned between the low resistance metal film 47 and each of the polysilicon gates 44A and 46A. In a subsequent process, ion implantation to form the source / drain may proceed.

The N-type polysilicon gate 44A formed as described above is used as a gate electrode of an NMOS transistor formed in a cell region and an NMOS region, and the P-type polysilicon gate 46A is used as a gate electrode of a PMOS transistor.

According to the third embodiment described above, the impurity concentration required at the interface between the P-type columnar polysilicon film 46 and the gate insulating film 43 can be sufficiently secured by applying the cluster doping method while using the columnar polysilicon film. . Accordingly, an effect of reducing polysilicon depletion may be obtained. In addition, by using an N-type columnar polysilicon film having excellent impurity distribution at the interface between the polysilicon film and the gate insulating film, an ion implantation ('NPG Imp') process for securing high concentrations in the NMOS region and the cell region is not required. Polysilicon depletion rate characteristics can be satisfied. In addition, since boron hydride clusters containing no fluorine are used, boron penetration is fundamentally prevented.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

1 is a view showing the structure of a dual polysilicon gate according to the prior art.

2A to 2D are cross-sectional views illustrating a method of manufacturing a polysilicon gate according to a first embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a dual polysilicon gate according to a second embodiment of the present invention.

4A to 4E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

41 substrate 42 recess pattern

43 gate insulating film 44 N-type columnar polysilicon film

46: P-type columnar polysilicon film

Claims (19)

Forming a columnar polysilicon film doped with a first conductive impurity; Counter doping the columnar polysilicon layer using a cluster containing a second conductive impurity; And Activation heat treatment step of the first conductive impurity and the second conductive impurity Polysilicon gate manufacturing method comprising a. The method of claim 1, The cluster is a polysilicon gate manufacturing method comprising a boron hydride cluster. The method of claim 2, The boron hydride cluster is octade carborene (B ₁₈ H ₂₂ ) comprising a polysilicon gate manufacturing method. The method of claim 1, The polysilicon film of the columnar structure, A method for producing a polysilicon gate deposited at a temperature of 680 to 800 ° C. by chemical vapor deposition using a silicon source gas and an N-type impurity-containing gas. The method of claim 1, And planarizing the surface of the counter-doped polysilicon film before the activation heat treatment proceeds. The method according to any one of claims 1 to 5, The counter-doping using the cluster is a polysilicon gate manufacturing method proceeds with a dose of 1E16 to 4E16 atoms / cm ² , energy of 60 to 90 keV, oblique incident angle of 0 to 7 °. Forming a columnar polysilicon film doped with a first conductivity type impurity on an entire surface of the substrate on which the first region and the second region are defined; Counter-doping the columnar polysilicon film of the second region using a cluster containing a second conductive impurity; And Activation heat treatment step of the first conductive impurity and the second conductive impurity Dual polysilicon gate manufacturing method comprising a. The method of claim 7, wherein The cluster is a dual polysilicon gate manufacturing method comprising a boron hydride cluster. The method of claim 8, The boron hydride cluster is octade carborene (B ₁₈ H ₂₂ ) comprising a dual polysilicon gate manufacturing method. The method of claim 7, wherein The polysilicon film of the columnar structure, A method for producing a dual polysilicon gate deposited at a temperature of 680-800 ° C. by chemical vapor deposition using a silicon source gas and an N-type impurity gas. The method of claim 7, wherein And prior to the heat treatment, planarizing the surface of the counter-doped polysilicon film. The method according to any one of claims 7 to 11, The counter-doping using the cluster, the dose is 1E16 to 4E16 atoms / cm ² , the energy is 60 to 90 keV, the oblique incidence angle is 0 to 7 ° to proceed. Forming a multi-channel pattern in the cell region of the substrate where a cell region and a peripheral circuit region are defined; Forming a gate insulating film on the entire surface of the substrate; Forming a columnar polysilicon film doped with N-type impurities on the gate insulating film; Counter doping the columnar polysilicon film of the peripheral circuit region by using a cluster containing P-type impurities; And Activation heat treatment step of the N-type and P-type impurities A semiconductor device manufacturing method comprising a. The method of claim 13, And wherein the peripheral circuit region is divided into an NMOS region and a PMOS region, and the counter doping proceeds to the PMOS region after covering the cell region and the NMOS region with a photoresist pattern. The method of claim 13, And the cluster comprises a boron hydride cluster. The method of claim 15, The boron hydride cluster comprises octade carborene (B ₁₈ H ₂₂ ). The method of claim 13, The polysilicon film of the columnar structure, A method of manufacturing a semiconductor device which is deposited at a temperature of 680 to 800 ° C. by chemical vapor deposition using a silicon source gas and an N-type impurity-containing gas. The method of claim 13, And planarizing the surface of the counter-doped polysilicon film prior to the activation heat treatment. The method according to any one of claims 13 to 18, A method of manufacturing a semiconductor device in which the counter doping using the cluster proceeds at a dose of 1E16 to 4E16 atoms / cm ² , an energy of 60 to 90 keV, and an oblique incident angle of 0 to 7 °.

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