KR20090109303A - Metal oxide semiconductor field effect transistor and method for fabricating the same - Google Patents

Abstract

PURPOSE: A metal oxide semiconductor field effect transistor is provided to obtain the low resistance and the equivalent oxide thickness(EOT) value. CONSTITUTION: A metal oxide semiconductor field effect transistor includes a semiconductor substrate(21), a source(22), a drain(23), a gate insulating layer(24), a gate(26), and an insulated side wall(25). The source and the drain are formed in the both side top of the semiconductor substrate. The gate insulating layer and the gate are successively formed on the upper side of the semiconductor substrate between the source and the drain. The insulated side wall surrounds the circumference of the gate to insulate the gate neighboring. The source, the drain and the gate are altogether formed by the same silicide.

Description

Metal oxide semiconductor field effect transistor and method for manufacturing the same {Metal oxide semiconductor field effect transistor and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal oxide semiconductor field effect transistors (MOSFETs) and methods of manufacturing the same. It relates to a transistor (pMOSFET) and a method of manufacturing the same.

A typical pMOSFET is a gate formed of poly-silicon (poly-Si), and a p +-formed by injecting a dopant such as boron by ion implantation into a silicon substrate on both sides of the gate, followed by high temperature heat treatment. It has a source and a drain of Si. In addition, in the case of a general pMOSFET, for example, NiSi may be formed as a contact metal on each surface of the gate, the source and the drain in order to lower the resistance of the gate, the source and the drain.

However, as the general MOSFET is gradually miniaturized, the thickness of the source and drain formed by the dopant must be continuously thinned, and thus the resistance is increased, thereby requiring a new alternative. In addition, when boron is used as the dopant for the manufacture of the pMOSFET, boron penetrates into the gate insulating film to change the threshold voltage and lower the reliability. In addition, in the formation of the source and drain, a high temperature heat treatment of about 800 ° C. or more is required to activate the dopant after ion implantation of the dopant, which limits the utilization of the gate electrode material.

On the other hand, in the case of the gate electrode formed of poly-Si, the equivalent oxide thickness (EOT) is increased due to the poly-depletion phenomenon, and has a disadvantage in that the resistance is relatively large. When pure metal or silicide is used instead of poly-Si, high temperature stability is inferior, and nitride electrodes such as TaN and TiN may be used in terms of high temperature stability, but resistance is greater than pure metal or silicide electrodes. There is this.

Schottky barrier MOSFET (Schottky barrier MOSFET) proposed to improve the above-mentioned disadvantages of the general MOSFET can significantly reduce the parasitic resistance by forming the source and drain as silicide, and dopant implantation and dopant through ion implantation method There is an advantage that does not need a high temperature heat treatment process to activate the. When manufacturing a pMOSFET with the structure of such a Schottky barrier MOSFET, it is suitable to use PtSi as a silicide. In this case, the source and the drain are made of PtSi, and the gate is made of a poly-Si layer and a PtSi layer. However, even in such a Schottky barrier pMOSFET, since poly-Si is used as the gate electrode, the problems of the existing poly-Si are not completely improved, and a high temperature heat treatment process for activation of the dopant in the poly-Si electrode is performed. This is still necessary.

Summary of the Invention The present invention is directed to improving the above-mentioned conventional problems, and an object of the present invention is to eliminate the need for a high temperature heat treatment process, and have a p-type Schottky barrier metal oxide semiconductor field effect transistor (pMOSFET) having improved characteristics compared to the conventional art. To provide.

Another object of the present invention is to provide a method of manufacturing the above-described schottky barrier metal oxide semiconductor field effect transistor.

A metal oxide semiconductor field effect transistor according to one type of the present invention includes a semiconductor substrate; Source and drain formed on upper sides of the semiconductor substrate, respectively; A gate insulating film and a gate each formed on an upper surface of the semiconductor substrate between the source and the drain in order; And an insulating sidewall surrounding the gate to insulate the gate, wherein the source, the drain, and the gate are all formed of the same silicide.

According to the invention, the silicide may be for example FUSI PtSi.

In addition, according to a preferred embodiment of the present invention, the gate insulating film and the insulating side wall, for example, may be used any one material of SiO ₂ , SiO _x N _y , HfO ₂ , Al ₂ O ₃ .

On the other hand, the method for manufacturing a metal oxide semiconductor field effect transistor according to another type of the present invention, a) a first insulating material layer and a poly-Si layer laminated on a semiconductor substrate, the first insulating material layer and poly-Si layer Patterning a predetermined pattern; b) first laminating the second insulating material layer over the resultant of step a) and etching the second insulating material layer until the surface of the semiconductor substrate and the poly-Si layer are exposed. Forming a sidewall of a layered gate insulating film and a second insulating material layer; c) depositing a Pt layer on the product of step b); d) reacting the Pt layer with the poly-Si layer and the semiconductor substrate, respectively, by heat treatment to simultaneously form a source, a drain, and a gate consisting of only PtSi; And e) removing the residual Pt layer.

Here, the semiconductor substrate may be made of silicon.

In addition, the first and second insulating material layers may be any one of, for example, SiO ₂ , SiO _x N _y , HfO ₂ , Al ₂ O ₃ .

According to a preferred embodiment of the present invention, the thickness of the Pt layer may be at least 0.76 times the thickness of the poly-Si layer.

According to the present invention, the heat treatment in step d) may be performed in an RTA device or a furnace equipment for a semiconductor at a temperature of 400 ℃ to 700 ℃.

According to an embodiment of the present invention, after the step b) or after the step c), the dopant may be ion implanted into the region where the source and the drain are to be formed.

In addition, after step b) or after step c), an additional dopant may be implanted into the region where the gate is to be formed.

Hereinafter, a configuration of a p-type Schottky barrier metal oxide semiconductor field effect transistor (pMOSFET) and a method of manufacturing the same will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a schematic structure of a Schottky barrier pMOSFET 20 according to an embodiment of the present invention. Referring to FIG. 1, a Schottky barrier pMOSFET 20 according to a preferred embodiment of the present invention may include, for example, a semiconductor substrate 21 formed of silicon (Si) and a source formed on both sides of the semiconductor substrate 21. 22 and a drain 23, and a gate insulating layer 24 and a gate 26, which are sequentially formed on the upper surface of the semiconductor substrate 21 between the source 22 and the drain 23, respectively. In addition, a sidewall 25 made of an insulating material is further formed around the gate 26 so that the source 22 and the drain 23 are electrically insulated from the gate 26. Here, the same material as that of the gate insulating film 24 may be used as the material of the sidewall 26, or another dielectric material having a high dielectric constant may be used. For example, the gate insulating layer 24 and the sidewall 26 may be formed of a material such as SiO ₂ , SiO _x N _y , HfO ₂ , Al ₂ O _3, or the like.

According to the present invention, the source 22, the drain 23 and the gate 26 may all be made of the same silicide material only. For example, the source 22, the drain 23, and the gate 26 may be formed using PtSi. In this case, when the source 22 and the drain 23 are formed on the semiconductor substrate 21, it is possible to simultaneously form the gate 26. Then, unlike the conventional MOSFET manufacturing process, there is no need for a high temperature heat treatment process of 800 ° C. or higher at all. In addition, the Schottky barrier pMOSFET 20 according to the present invention has a simpler structure than the conventional method, and thus, the manufacturing process may be simplified. In particular, when PtSi is used as the silicide material of the source 22, drain 23 and gate 26, the resistance is lower than that of the case of using a nitride electrode. Further, FUSI (fully silicided) PtSi formed as the gate 26 on the gate insulating film 24 formed of SiO ₂ , for example, is suitable for use as a gate electrode of a pMOSFET because it has a work function value of about 4.9 eV.

2A to 2G are cross-sectional views sequentially illustrating a process of manufacturing the Schottky barrier pMOSFET 20 according to the exemplary embodiment of the present invention illustrated in FIG. 1. 2A to 2G, the method for manufacturing the Schottky barrier pMOSFET 20 according to the present invention will be described in detail.

First, referring to FIG. 2A, a first insulating material layer 14 is formed on an upper surface of a semiconductor substrate 21, which may be formed of, for example, silicon (Si). For example, the first insulating material layer 14 is for forming a gate insulating film. For example, any one of SiO ₂ , SiO _x N _y , HfO ₂ , and Al ₂ O ₃ may be used.

Next, as shown in FIG. 2B, the poly-Si layer 11 is formed on the upper surface of the first insulating material layer 14. Thereafter, the photoresist 12 is formed on the surface of the poly-Si layer 11, and then the photoresist 12 is patterned in a predetermined pattern by, for example, a lithography process. The first insulating material layer 14 and the poly-Si layer 11 are etched using dry etching to form the same pattern as that of the photoresist 12. Pattern layer 11. FIG. 2C shows a cross-sectional view after the first insulating material layer 14 and the poly-Si layer 11 are patterned in this manner. FIG. 2C illustrates a state in which the upper surface of the semiconductor substrate 21 is completely exposed until the first insulating material layer 14 is completely etched. However, in this process, it is not necessary to fully etch the first insulating material layer 14, and only the poly-Si layer 11 is sufficient to be etched. Therefore, in FIG. 2C, the first insulating material layer 14 may partially remain on the surface of the semiconductor substrate 21.

Thereafter, referring to FIG. 2D, a second insulating material layer 15 is entirely formed over the semiconductor substrate 21 and the poly-Si layer 11. The second insulating material layer 15 is for forming sidewalls that surround the gate and insulate the gate, and like the first insulating material layer 14, for example, SiO ₂ , SiO _x N _y , HfO ₂ , Al _2. Any material of O ₃ can be used. However, the first insulating material layer 14 and the second insulating material layer 15 are not necessarily formed of the same material, and may be formed of different materials.

After forming the second insulating material layer 15, as shown in FIG. 2E, all of the second insulating material layer 15 except for the peripheral portion of the poly-Si layer 11 is removed by dry etching. do. In this process, it is necessary to perform dry etching until the upper surface of the semiconductor substrate 21 and the upper surface of the poly-Si layer 11 are completely exposed. In this way, the gate insulating film 24 and the side wall 25 are completed.

Next, as shown in FIG. 2F, a Pt layer 16 is formed over the semiconductor substrate 21 and the poly-Si layer 11 to a sufficient thickness to simultaneously form a source, a drain, and a gate made of PtSi. In general, when forming PtSi, about 1.32 nm thick Si is consumed for about 1 nm thick Pt. Therefore, when forming FUSI PtSi, the thickness of the Pt layer 16 is at least 0.76 times the thickness of the poly-Si layer 11 in order to completely consume poly-Si so that no poly-Si remains after the reaction. Should be

After forming the Pt layer 16 to a sufficient thickness, the Pt layer 16, the poly-Si layer 11, the Pt layer 16, and the semiconductor substrate 21 are reacted through annealing, respectively. . The heat treatment here may be carried out at a relatively low temperature of about 400 ℃ to 700 ℃. For example, such heat treatment may be performed using rapid thermal annealing (RTA) equipment or furnace equipment for semiconductors. Then, Pt of Pt layer 16 reacts with Si of poly-Si layer 11 and semiconductor substrate 21 to form PtSi. After the heat treatment process is completed, the remaining Pt is finally removed by wet etching. At this time, for example, Aqua Regia made by mixing nitric acid and hydrochloric acid in distilled water (DI water) can be used. By doing so, as shown in Fig. 2G, the source 22, the drain 23 and the gate 26 are formed at the same time, and the Schottky barrier pMOSFET according to the present invention with the structure shown in Fig. 1 is completed.

As described so far, according to the pMOSFET fabrication method according to the present invention, the gate 26 is made of only silicide such as PtSi, and can be formed simultaneously with the source 22 and the drain 23. Thus, lower resistance and equivalent oxide thickness (EOT) values can be obtained compared to conventional Schottky barrier pMOSFETs with poly-Si gate electrodes, resulting in larger driving currents than conventional Schottky barrier pMOSFETs. And mobility characteristics can be secured. In addition, as described above, according to the pMOSFET manufacturing method according to the present invention, there is no need for a high temperature heat treatment of 800 ° C. or higher for activating the dopant implanted in poly-Si.

On the other hand, in order to lower the Schottky barrier height (SBH) of the source 22 and the drain 23, near the region where the source 22 and the drain 23 are to be formed before and after the formation of the Pt layer 16. The dopant may be ion implanted into it. Likewise, the dopant may be ion implanted into the poly-Si layer 11 on which the gate 26 is to be formed. As the dopant, boron or the like may be used. For example, the dopant may be implanted immediately after the sidewall 25 is formed in the process illustrated in FIG. 2E, or the dopant may be implanted immediately after the Pt layer 16 is formed in the process illustrated in FIG. 2F. have. According to the present invention, since such dopant implantation is merely for lowering the Schottky barrier height, the existing high temperature heat treatment process for activation of the dopant is not required. After forming the Pt layer 16 only, the heat treatment process for forming PtSi in the process shown in FIG. 2G can sufficiently lower the Schottky barrier height to 0.3 eV or less.

To date, exemplary embodiments have been described and illustrated in the accompanying drawings in order to facilitate understanding of the present invention. However, it should be understood that such embodiments are merely illustrative of the invention and do not limit it. And it is to be understood that the invention is not limited to the illustrated and described description. This is because various other modifications may occur to those skilled in the art.

1 is a cross-sectional view illustrating a schematic structure of a Schottky barrier pMOSFET according to the present invention.

2A through 2G are cross-sectional views sequentially illustrating a process of manufacturing a Schottky barrier pMOSFET according to the present invention shown in FIG.

<Description of Symbols for Main Parts of Drawings>

11 ..... poly-Si layer 12 ..... photoresist

14,15 ..... insulating material layer 16 ..... Pt layer

20 ..... pMOSFET 21 ..... Substrate

22 ..... source 23 ..... drain

24 ..... gate insulating film 25 ..... side wall

26 ..... gate

Claims (10)

Semiconductor substrates; Source and drain formed on upper sides of the semiconductor substrate, respectively; A gate insulating film and a gate each formed on an upper surface of the semiconductor substrate between the source and the drain in order; And An insulating sidewall surrounding the gate to insulate the gate; And the source, drain, and gate are all formed of the same silicide only. The method of claim 1, The silicide is FUSI PtSi metal oxide semiconductor field effect transistor. The method of claim 1, And the gate insulating layer and the insulating sidewall are made of any one of SiO ₂ , SiO _x N _y , HfO ₂ , and Al ₂ O ₃ . a) laminating a first insulating material layer and a poly-Si layer on a semiconductor substrate, and patterning a predetermined pattern on the first insulating material layer and the poly-Si layer; b) first laminating the second insulating material layer over the resultant of step a) and etching the second insulating material layer until the surface of the semiconductor substrate and the poly-Si layer are exposed. Forming a sidewall of a layered gate insulating film and a second insulating material layer; c) depositing a Pt layer on the product of step b); d) reacting the Pt layer with the poly-Si layer and the semiconductor substrate, respectively, by heat treatment to simultaneously form a source, a drain, and a gate consisting of only PtSi; And e) removing the residual Pt layer; and manufacturing a metal oxide semiconductor field effect transistor. The method of claim 4, wherein The semiconductor substrate is a method of manufacturing a metal oxide semiconductor field effect transistor, characterized in that made of silicon. The method of claim 4, wherein The first and second insulating material layers are any one of SiO ₂ , SiO _x N _y , HfO ₂ , Al ₂ O _{3 A} method of manufacturing a metal oxide semiconductor field effect transistor. The method of claim 4, wherein And the thickness of the Pt layer is at least 0.76 times the thickness of the poly-Si layer. The method of claim 4, wherein Heat treatment in step d) is a method of manufacturing a metal oxide semiconductor field effect transistor, characterized in that carried out in the furnace equipment for RTA equipment or semiconductor at a temperature of 400 ℃ to 700 ℃. The method of claim 4, wherein After step b) or after step c), a dopant is ion implanted into a region where a source and a drain are to be formed. The method of claim 9, After step b) or after step c), an additional dopant is implanted into the region where the gate is to be formed.

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