KR20090103567A - CMOS charge pump - Google Patents

Abstract

PURPOSE: A CMOS charge pump is provided to increase the current delivery ability without voltage drop. CONSTITUTION: A CMOS charge pump comprises a pre-charge driving unit, a pre-charging unit, a booster, a delivery switch unit, and a bulk pumping unit. The pre-charge driving unit generates first and second pre-charge signals having first and second levels in response to first and second clock signals(clk1,clk2). The pre-charging unit pre-charges first and second nodes(N1,N2) up to the first level in response to the first and second pre-charge signals. The booster boosts the first node up to the second level in response to the third clock signal(clk3), and the second node up to the second level in response to the fourth clock signal(clk4).

Description

CMOS charge pump

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to CMOS charge pumps, and more particularly, to a CMOS charge pump capable of increasing current carrying capacity without voltage drop and stabilizing forward bulk bias.

As the line width of the CMOS process is gradually reduced and refined, the supply voltage used is gradually decreasing. The use of low supply voltages is a very important design element not only for solving the reliability problems of micro processes, but also for battery powered portable low power integrated circuit devices. However, not all circuits inside an integrated circuit device operate with a low supply voltage alone. For example, a word line of a memory device has a very high voltage to remove the threshold voltage Vth of a cell. Therefore, a circuit for generating a high output voltage by receiving a low supply voltage is needed, which is mainly achieved through a CMOS charge pump. Accordingly, high performance charge pumps are an important part of integrated circuit device design.

The CMOS charge pump operates by applying a clock signal or a phase signal, which is a standard of normal operation, to step up a voltage by a capacitor and send the boosted voltage to an output terminal through a transfer switch. On the other hand, at the output terminal, current consumption occurs due to the connected external load, and as the current consumption increases, the output voltage does not maintain the boosted voltage and falls. Therefore, the charge pump must be designed to supply the boosted voltage invariably despite this current consumption.

The charge pump uses NMOS transistors or PMOS transistors as transfer switches. Dickson charge pumps and NCPs (new charge pumps) are well known as NMOS-type charge pumps that use NMOS transistors as transfer switches, and cross-linked PMOS-type charge pumps that use PMOS transistors as transfer switches. Coupled charge pumps and two-phase charge pumps are well known.

Among the NMOS type charge pumps, the Dixon charge pump is composed of NMOS transistors having a diode-connected configuration and capacitors connected to the NMOS transistors in each stage, and thus has a very simple structure and the advantage that charges are transferred only from the input to the output direction. have. However, there is a disadvantage in that the output efficiency decreases due to the decrease caused by the threshold voltage of the NMOS transistor at each stage and the last output stage. That is, the output voltage Vout of the N-stage Dickson charge pump drops and is output by the threshold voltage Vth of the N + 1 NMOS transistors.

1 is a diagram illustrating an NCP as an example of an NMOS type charge pump. 1 shows a three-stage NCP.

NCP is an NMOS type charge pump that was developed to compensate for the fact that the Dixon charge pump has a reduction due to the threshold voltage of the NMOS transistor at each stage. Referring to FIG. 2, the configuration of the first stage of the NCP will be described. A parallel connection is made between an input node Nin and a first transfer node Nd1 which is a transfer node that transfers the output of the first stage to the second stage. NMOS transistors T1 and PMOS transistors connected in series between two NMOS transistors D1 and S1 and an input node Nin and a second transfer node Nd2 that transfers the output of the second stage to the third stage. Q1 and one end thereof are provided with a boosting capacitor Cm1 connected to the first transfer node Nd1 and receiving the first clock signal clk1 at the other end thereof. The NMOS transistors D1 and S1 are transfer transistors, which transfer the output of the previous stage to the next stage. The gate of the NMOS transistor D1 is connected to the input node Nin, and the gate of the NMOS transistor S1 is connected between the NMOS transistor T1 and the PMOS transistor Q1. Gates of the NMOS transistor T1 and the PMOS transistor Q1 are connected to the second transfer node Nd2.

The configuration of the second and third stages is also the same as that of the first stage, but each stage is configured to receive the first and second clock signals clk1 and clk2 alternately. Here, the first and second clock signals clk1 and clk2 are clock signals having phases opposite to each other.

The PMOS transistor Q1 is provided to apply the boosted voltage of the next stage to the gate of the NMOS transistor S1, and the NMOS transistor T1 is provided to prevent the boosted voltage from flowing back to the input node Nin. do.

Since the two NMOS transistors D1 and S1 are transfer transistors and the NMOS transistor D1 has a gate connected to the input node N1 like the Dickson charge pump, a voltage drop equal to the threshold voltage Vth occurs during charge transfer. . However, since the NMOS transistor S1 receives a voltage boosted through the PMOS transistor Q1 to the gate, no voltage drop occurs. In other words, it can deliver a boosted voltage without a voltage drop.

However, in the case of the last output stage, there is no later stage where higher boost voltages can be applied. Therefore, it has a different structure from 1st thru | or 3rd stage. In FIG. 2, the output terminal is connected between the third transfer node Nd3 and the output node Nout, and the NMOS transistor DO and the third transfer node Nd3 having a gate connected to the third transfer node Nd3. An NMOS transistor D4 connected between the fourth boosting capacitor Cm4, a gate connected to the third transfer node Nd3, and one end connected to the NMOS transistor D4, and the second clock signal clk2 on the other end thereof. ) Is provided with a fourth boosting capacitor (Cm4) and an output capacitor (Cout) connected between the output node (Nout) for outputting the output voltage (Vout) and the ground voltage (Vss).

The NMOS transistor D4 transfers the voltage boosted by the boost capacitor Cm4 to the third transfer node Nd3. The NMOS transistor DO transfers the voltage of the third transfer node Nd3 to the output node Nout as an output transistor. However, since the gate of the NMOS transistor DO is connected to the third transfer node Nd3, the voltage of the third transfer node Nd3 drops as much as the threshold voltage Vth of the NMOS transistor DO, thereby outputting the output node Nout. Is delivered. The output capacitor Cout stabilizes the output voltage Vout and outputs it.

Therefore, the NCP of FIG. 1 is more efficient than the Dickson charge pump described above because the voltage drop occurs only once at the last output stage. However, although there is one voltage drop, the voltage drop still occurs.

The NMOS type charge pump is advantageous in that charge is transferred only from an input to an output direction, and a transfer speed is high. However, there is a disadvantage in that the output efficiency decreases because the threshold voltage Vth decreases due to the NMOS transistors MN1 to MN3 at each stage. Although not shown, in the NMOS type charge pump, each of the NMOS transistors has a bulk voltage connected to the ground voltage Vss to prevent the forward bias from being applied to the bulk.

On the other hand, the PMOS type charge pump can transfer the boosted voltage to the output terminal without the voltage drop caused by the threshold voltage. Among the PMOS type charge pumps, the cross-linked charge pump (not shown) may directly connect the bulk of the PMOS transistor and the output node so that the bulk voltage may change due to the change of the output voltage. Leakage current in bulk in a CMOS device can cause not only current loss but also latch-up, which can have a critical impact on product reliability.

2 is a diagram illustrating a two-phase charge pump as an example of a PMOS type charge pump.

The two phase charge pump has a boosting section, a precharge section and a bulk pumping section. The booster includes two PMOS transistors MT1 and MT2, a first node N1, and a second node N2 connected between the power supply voltage Vdd and the first node N1 and the second node N2, respectively. Two NMOS transistors M1 and M2 and one end respectively connected between the power supply voltage Vdd are connected to the first and second nodes N1 and N2, respectively, and the first and second clock signals clk1 and clk2. The two stages are provided with two boosting capacitors Ca1 and Ca2, respectively. The gate of the PMOS transistor MT1 is cross-connected to the second node N2, and the gate of the PMOS transistor MT2 is cross-connected to the first node N1. The gates of the NMOS transistors M1 and M2 are connected to the first and second precharge nodes Npr1 and Npr2, respectively.

 The precharge unit is connected between the first precharge capacitor Ca3, which boosts the first precharge node Npr1 by receiving a third clock signal clk3, between the power supply voltage Vdd and the first precharge node Npr1. A first precharge unit including two NMOS transistors Pr1 and Pr2, a second precharge capacitor Ca4 that boosts the second precharge node Npr2 by receiving a fourth clock signal clk4, and a power supply A second precharge unit having two NMOS transistors Pr3 and Pr4 connected between the voltage Vdd and the second precharge node Npr2 is provided. The bulks of the four NMOS transistors Pr1 to Pr4 of the precharge part are all connected to the power supply voltage Vdd, and the gates of the NMOS transistors Pr1 and Pr4 are also connected to the power supply voltage Vdd. The gate of the NMOS transistor Pr2 is connected to the second precharge node Npr2, and the gate of the NMOS transistor Pr3 is cross-connected to the first precharge node Npr1.

The bulk pumping unit is coupled between the first bulk capacitor Ca5 and the output node Nout and the first bulk node Nb1, which receives the fifth clock signal clk5 and boosts the first bulk node Nb1. A second bulk capacitor Ca4 and an output node Nout for boosting the second bulk node Nb2 by receiving a first bulk pumping unit including the NMOS transistors B1 and B2 and a sixth clock signal clk6; A second bulk pumping part including two NMOS transistors B3 and B4 connected between the second bulk nodes Nb2 is provided. The bulks of the four NMOS transistors B1 to B4 of the bulk pumping part are all connected to the output node Nout, and the gates of the NMOS transistors B1 and B4 are also connected to the output node Nout. The gate of the NMOS transistor B2 is cross-connected to the second bulk node Nb2, and the gate of the NMOS transistor B3 is cross-connected to the first bulk node Nb1.

In the two-phase charge pump of FIG. 2, since the NMOS transistors Pr2 and Pr3 of the precharge unit are cross-connected, the precharge nodes Npr1 and Npr2 maintain a voltage level higher than the power supply voltage Vdd. The NMOS transistors M1 and M2 of the boost unit have a gate connected to the precharge nodes Npr1 and Npr2, respectively, so that the power supply voltage Vdd level (hereinafter referred to as Vdd level) before the first and second nodes N1 and N2 are pumped. Precharge with). This improves boost and transfer speeds compared to cross-linked charge pumps. In addition, the bulk pumping unit connected to the bulk of the PMOS transistors MT1 and MT2 pumps the bulk nodes Nb1 and Nb2 in response to the fifth and sixth clock signals clk5 and clk6, thereby maintaining a high and stable bulk voltage.

The two-phase charge pump of FIG. 2 can improve the boost and transfer speed and maintain a stable bulk voltage compared to the cross-link charge pump, but like the cross-link charge pump, the two-phase charge pump also has the gate-source voltage of the transfer transistor. (Vgs) is limited to the supply voltage (Vdd) level to limit the current transfer capability, the bulk pumping effect is small when the output voltage (Vout) is lowered by an external load.

In addition, there is a charge pump that improves the current transfer capability of the PMOS type charge pump by using a level shifter, but the level shifter generates a leakage current to lower the voltage level of the output voltage. In addition, since a circuit for generating a level shifter and a control signal for controlling the level shifter must be further provided, an area is increased. In addition, there is still a problem that the bulk voltage is unstable even when using a level shifter.

As a result, the NMOS type charge pump has the advantage of easy low voltage transfer and fast transfer speed, but has a disadvantage in that a loss due to a threshold voltage occurs when transferring a high voltage. On the other hand, a charge pump using a PMOS transistor as a transfer switch has an advantage of delivering a high voltage without losing a threshold voltage, but has a disadvantage in that a transfer speed is slow and leakage current flows in bulk.

SUMMARY OF THE INVENTION An object of the present invention is to provide a CMOS charge pump that has no voltage drop, has high current carrying capability, and can stabilize forward bulk bias.

The CMOS charge pump of the present invention for achieving the above object is a precharge driver for generating first and second precharge signals of first and second levels in response to first and second clock signals, the first and second A precharge unit which precharges the first and second nodes to the first level in response to a second precharge signal; boosting the first node to the second level in response to a third clock signal; A booster that boosts the second node to the second level in response, and a plurality of switch NMOS transistors that respectively transmit voltages of the first and second nodes to an output node in response to the first and second precharge signals And a transfer switch unit having a plurality of switch PMOS transistors which transfer voltages of the first and second nodes to the output node in response to voltage levels of the first and second nodes, and the third and fourth clocks. Respond to signals And a bulk pumping unit configured to pump bulk nodes connected to bulks of the plurality of switch PMOS transistors, and apply voltages of the first and second nodes to the bulk nodes in response to voltages of the first and second nodes. It is characterized by.

In order to achieve the above object, the precharge driver of the present invention is connected between a power supply voltage and a third node on which the first precharge signal is output, and a gate is connected to a fourth node on which the second precharge signal is output. A first driving transistor, a second driving transistor connected between the power supply voltage and the fourth node, a gate connected to the third node, one end connected to the third node, and the other end receiving the first clock signal; And a first precharge capacitor, and a second precharge capacitor, one end of which is connected to the fourth node and the other end of which receives the second clock signal.

A precharge unit of the present invention for achieving the above object is connected between the power supply voltage and the first node, the first precharge transistor to receive the first precharge signal to the gate, and the power supply voltage and the second And a second precharge transistor connected between nodes and receiving the second precharge signal through a gate.

A booster of the present invention for achieving the above object is a first boosting capacitor having one end connected to the first node and receiving the third clock signal at the other end, and one end connected to the first node and the third end at the other end. And a first boosting capacitor configured to receive a clock signal.

First bulk transistor of the present invention for achieving the above object, the first bulk transistor is connected between the first node and the bulk node, the gate is connected to the second node, the bulk is connected to the bulk node, the first A second bulk transistor connected between a second node and the bulk node, a gate connected to the first node, a bulk connected to the bulk node, and one end connected to the bulk node, and the third and And first and second bulk capacitors receiving the fourth clock signal, respectively.

In the first to fourth clock signals of the present invention for achieving the above object, the first and second clock signals have a phase difference of 180 degrees between the third and fourth clock signals, respectively, and the third and fourth clock signals. The signal may be set such that the third level periods do not overlap each other, and the first and third clock signals and the second and fourth clock signals do not overlap each other.

A first switch NMOS transistor connected between the first node and the output node and receiving the second precharge signal through a gate, the second node and the output node of the present invention for achieving the above object. A second switch NMOS transistor connected between the second switch NMOS transistor to receive the first precharge signal, a first switch PMOS transistor connected between the first node and the output node, and a gate connected to the second node; And a second switch PMOS transistor connected between the second node and the output node and whose gate is connected to the first node.

The CMOS charge pump of the present invention for achieving the above object is the first auxiliary pumping to output a first auxiliary signal of a fourth level higher than the second level in response to the first precharge signal and the second to fourth clock signal And a second auxiliary pumping part configured to output the second auxiliary signal of the fourth level in response to the second precharge signal and the first, third and fourth clock signals.

A transfer switch unit of the present invention for achieving the above object is connected between a first node and the output node, the first switch NMOS transistor to receive the first auxiliary signal to the gate, between the second node and the output node A second switch NMOS transistor coupled to receive the first auxiliary signal through a gate, a first switch PMOS transistor coupled between the first node and the output node, and a gate connected to the second node, and the first switch PMOS transistor connected to the second node; And a second switch PMOS transistor connected between the two nodes and the output node, the gate of which is connected to the first node.

Therefore, the CMOS charge pump of the present invention has no voltage drop generated in the NMOS type charge pump while the output voltage is transferred, and has a higher current transfer capability than the PMOS type charge pump. It also has high reliability because it can stabilize the forward bulk bias.

1 is a diagram illustrating an example of an NMOS type charge pump.

2 is a diagram illustrating an example of a PMOS type charge pump.

3 is a diagram showing one embodiment of a CMOS charge pump of the present invention.

4 is a diagram showing a waveform of a clock signal.

Fig. 5 shows another embodiment of the CMOS charge pump of the present invention.

6A to 6C are simulation diagrams for comparing the conventional charge pump with those of FIGS. 3 and 5.

Hereinafter, the CMOS charge pump of the present invention will be described with reference to the accompanying drawings.

3 is a view showing an embodiment of the CMOS charge pump according to the present invention. The CMOS charge pump, which is nicknamed, pumps the boost circuit 110 and the precharge driver 120 and the bulk bias to reduce the boost time at the initial stage of the boost operation. It is provided with a bulk pumping unit 130 to.

The booster circuit 110 is connected to the first and second nodes N1 and N2 and is connected to the first and second nodes N1 and N2 in response to the third clock signal clk3 and the fourth clock signal clk4. Is connected between the boost operation unit for boosting the power supply and the power supply voltage Vdd and the first and second nodes N1 and N2 to precharge the first and second nodes N1 and N2. The output node Nout is connected between the charge unit and the first and second nodes N1 and N2 and the output node Nout as the output voltage Vout using the boosted voltage of the first and second nodes N1 and N2. It consists of a transfer switch unit that outputs to

The boost operation unit includes two boost capacitors C1 and C2 having one end connected to the first and second nodes N1 and N2, respectively, and the third clock signal (C1 and C2) is provided at the other end of the boost capacitors C1 and C2. clk3) and a fourth clock signal clk4 are applied respectively.

The first precharge NMOS transistor NP1 is connected between the first node N1 and the power supply voltage Vdd and receives the first precharge signal P applied by the precharge driver 120 as a gate. ) And a second precharge NMOS transistor NP2 connected between the second node N2 and the power supply voltage Vdd and receiving a second precharge signal Q applied from the precharge driver 120 as a gate. It is provided.

The transfer switch unit may be connected between the output node Nout and the first node N1 to which the output voltage Vout is output, and transfer the voltage of the first node N1 to the output node Nout. And a second transfer unit connected between the output node Nout and the second node N2 to transfer the voltage of the second node N2 to the output node Nout. The first transfer part includes a first switch PMOS transistor PT1 and a first switch NMOS transistor NT1 connected in parallel between the output node Nout and the first node N1. The gate of the first switch PMOS transistor PT1 is connected to the second node N2, and the gate of the first switch NMOS transistor receives a second precharge signal Q applied from the precharge driver 120. The second transfer unit includes a second switch PMOS transistor PT2 and a second switch NMOS transistor NT2 connected in parallel between the output node Nout and the second node N2. The gate of the second switch PMOS transistor PT2 is connected to the first node N1, and the gate of the second switch NMOS transistor NT2 receives the first precharge signal P applied from the precharge driver 120. Licensed.

The precharge driver 120 is connected between the power supply voltage Vdd and the third node N3, and the first driving NMOS transistor ND1 and the power supply voltage Vdd having a gate connected to the fourth node N4. One end of each of the second driving NMOS transistors ND2 and the third node N3 and the fourth node N4 connected between the fourth node N4 and the gate connected to the third node N3, respectively. Two precharge capacitors C3 and C4 are provided. The first clock signal clk1 and the second clock signal clk2 are applied to the other ends of the two precharge capacitors C3 and C4, respectively. The first and second precharge signals P and Q, which are output signals of the precharge driver 120, are respectively output to the third and fourth nodes N3 and N4.

The bulk pumping unit 130 is connected between the first node N1 and the bulk node Nb, and the first bulk PMOS transistor Pb1 and the second node N2 having a gate connected to the second node N2. And a second bulk PMOS transistor Pb2 having a gate connected to the first node N1 and a bulk node Nb connected between the bulk node Nb and the first node N1, and the third clock signal clk3 on the other end thereof. ) And two bulk capacitors Cb1 and Cb2 receiving the fourth clock signal clk4 and a third bulk capacitor Cb3 connected between the bulk node Nb and the ground voltage Vss.

In Figure 3, the bulk of all NMOS transistors NT1, NT2, ND1, ND2, NP1, NP2 are connected to ground voltage Vss, and all of the PMOS transistors PT1, PT2, Pb1, Pb2 are connected to bulk node Nb. Connected.

4 is a diagram showing a waveform of a clock signal. The CMOS charge pump of Fig. 3 uses four clocks (clk1 to clk4). However, the charge pump using two or more clocks is not a special configuration since it is already used in a conventional charge pump such as the two-phase charge pump of FIG. In FIG. 4, the first clock signal clk1 and the second clock signal clk2 are signals having a phase difference of 180 degrees with each other, and the third clock signal clk3 and the fourth clock signal clk4 have a phase difference of 180 degrees with each other. It is a signal. The low level periods of the third clock signal clk3 and the fourth clock signal clk4 are non-overlap so that the first and second switch PMOS transistors PT1 and PT2 of the transfer switch unit are non-overlap. Should not be turned on at the same time. Further, the first and third clock signals clk1 and clk3 and the second and fourth clock signals clk2 and clk4 are set so that the high level periods do not overlap each other, so that the first and second clock signals clk1 and clk3 are not overlapped with each other. Do not allow the precharge operation and the boost operation to occur at the same time.

Referring to FIGS. 3 and 4, first, the gate and the drain of the first and second driving NMOS transistors ND1 and ND2 of the precharge driver 120 are cross-connected with each other. Therefore, when one of the first clock signal clk1 or the second clock signal clk2 is applied at the power supply voltage level (hereinafter referred to as Vdd level), the first clock signal clk1 or the second clock signal clk2 applied at the Vdd level. In response to the third and fourth nodes N3 and N4 have a Vdd level. Since the third and fourth nodes N3 and N4 have a Vdd level, the first and second switch NMOS transistors NT1 and NT2 and the first and second precharge NMOS transistors NP1, NP2) is turned on. The turned on first and second precharge NMOS transistors NP1 and NP2 always precharge the first and second nodes N1 and N2 to the Vdd level.

The third clock signal clk3 is applied at the Vdd level so that the first boosting capacitor C1 boosts the first node N1 to 2Vdd level, which is twice the Vdd level, and then the fourth clock signal clk4 at the Vdd level. Transitions to the ground voltage level (hereinafter, Vss level), the gate-source voltage difference Vgs of -Vdd is generated in the first switch PMOS transistor PT1 and turned on to output the voltage of the first node N1. Start delivery to node Nout.

Meanwhile, while the third clock signal clk3 is applied at the Vdd level, the second clock signal clk2 transitions to the Vdd level. The precharge capacitor C4 boosts the fourth node N4 to 2Vdd level in response to the second clock signal clk2 and outputs a second precharge signal Q of 2Vdd level. The second precharge signal Q having a 2Vdd level turns on the first switch NMOS transistor NT1 and the second precharge NMOS transistor NP2. The turned on first switch NMOS transistor NT1 transfers the voltage of the first node N1 to the output node Nout together with the first switch PMOS transistor NP1. At this time, the first switch PMOS transistor PT1 transfers the voltage of the first node N1 to the output node Nout without a voltage drop, but the maximum value of the gate-source voltage Vgs is limited to the -Vdd level. The amount of current that can be limited is also limited. On the other hand, the first switch NMOS transistor NT1 drops the voltage of the first node N1 by the threshold voltage Vth of the first switch NMOS transistor NT1 and transfers it to the output node Nout, but the first switch NMOS Since the source of the transistor NT1 is connected to the output node Nout, the gate-source voltage Vgs is equal to the voltage level of 2 Vdd of the second precharge signal Q and the output voltage N which is the voltage of the output node Nout. 2Vdd-Vout, which is the difference between Vout). Therefore, the current transfer capability of the first switch NMOS transistor NT1 varies depending on the output voltage Vout. The first switch NMOS transistor NT1 transfers a large amount of current to the output node Nout when the output voltage is almost 0 V at the initial stage of the boosting operation to increase the transfer speed, and when the voltage level of the output node Vout increases. Gradually, the amount of current to be transmitted decreases, and when the voltage difference 2Vdd-Vout becomes equal to the threshold voltage Vth of the first switch NMOS transistor NT1, it is turned off and does not transmit current. The second switch PMOS transistor PT2 is turned off because the voltage of the first node N1 boosted to the gate is applied. However, since the gate-source voltage of the second switch NMOS transistor NT2 is the difference between the first precharge signal P having the Vdd level and the output voltage Vout, the output voltage Vout drops to a voltage level lower than Vdd-Vth. In this case, it is turned on to transfer the voltage of the second node N2 to the output node Vout.

That is, while the second and third clocks clk2 and clk3 are applied at the Vdd level, the CMOS charge pump of FIG. 3 may not only operate the first switch PMOS transistor PT1 but also the first node NMOS transistor NT1. Since the charge of N1) is transferred to the output node Nout, there is no voltage drop and a large amount of current can be delivered in response to the output voltage Vout. Therefore, even when a large load is connected to the output node Vout, the output voltage Vout can be transmitted stably.

In addition, the second bulk PMOS transistor Pb2 of the bulk pumping unit 130 receives a voltage of 2Vdd level of the first node N1 boosted by the third clock signal clk3 as a gate and has a second voltage of Vdd level. The voltage of the node N2 is applied as a source. The first bulk PMOS transistor Pb1 receives the voltage of the second node N2 of the Vdd level as a gate and the voltage of the first node N1 of the 2Vdd level as a source. The gate-source voltage of the first bulk PMOS transistor Pb1 is turned on since -Vdd, and the gate-source voltage of the second PMOS transistor Pb2 is turned off by Vdd. Therefore, the first bulk PMOS transistor Pb1 applies a voltage of 2Vdd level of the first node N1 to the bulk node Nb. In addition, the first bulk capacitor Cb1 receiving the third clock signal clk3 also boosts the bulk node Nb.

Since the bulk pumping unit of FIG. 2 performs bulk pumping based on an output node in which current consumption directly occurs, the effect of bulk pumping may be reduced according to the charge loss of the output node. However, the bulk pumping part 130 of the present invention pumps separately from the output terminal unlike the bulk pumping part of FIG. 2 because the charge loss generated at the bulk node Nb is relatively small compared to the output node. This ensures stable bulk voltage and does not require a separate clock signal to pump the bulk.

When the third and fourth clock signals clk1 and clk3 transition to the Vdd level, the voltage change ΔVb of the bulk node Nb is equal to the voltage level of the third and fourth clock signals clk1 and clk3, respectively. When it changes to (DELTA) V4, it calculates as (Cb1 ((DELTA) V3) + Cb2 ((DELTA) V4)) / (Cb1 + Cb2 + Cb). Therefore, the variation width of the bulk voltage is determined by the capacitances of the first to third bulk capacitors Cb, Cb1, and Cb2.

When the fourth clock signal clk4 transitions to the Vdd level, and then the first clock signal clk1 transitions to the Vdd level, the boosted voltage is transmitted to the output node Nout in the same manner as described above. In this case, however, the second switch PMOS transistor PT2 and the second switch NMOS transistor NT2 transfer the voltage of the second node N2 to the output node Nout.

As a result, the CMOS type charge pump of the present invention shown in Fig. 3 uses both the PMOS transistor and the NMOS transistor as transfer switches, so that no voltage drop occurs at the output voltage Vout, and the operation speed is fast and a large amount of current can be delivered. Can be. However, since the first and second switch PMOS transistors PT1 and PT2 transfer charges in response to the third and fourth clock signals clk3 and clk4, the first and second switch PMOS transistors PT1 and PT2 transfer charges for a relatively long time. Since the two-switch NMOS transistors NT1 and NT2 are turned on limitedly only while the first and second clock signals clk1 and clk2 are at the Vdd level, and especially, only until the output voltage Vout reaches 2Vdd-Vth. When the voltage level of the output voltage Vout rises above a certain level, the charge transfer capability is reduced.

Fig. 5 shows another embodiment of the CMOS charge pump of the present invention. The CMOS charge pump shown in Fig. 5 is a CMOS charge pump designed to improve the charge transfer capability of the switch NMOS transistors NT1 and NT2.

In the CMOS charge pump of FIG. 3, the gate of the first switch NMOS transistor NT1 receives the second precharge signal Q, and the gate of the second switch NMOS transistor NT2 receives the first precharge signal P. 5, the first charge NMOS transistor NQ1 receives the first auxiliary signal A output from the first auxiliary pump 220, and the second switch NMOS transistor NQ2. Is configured to receive a second auxiliary signal B output from the second auxiliary pump 230. The rest of the configuration is the same as the CMOS charge pump of FIG.

The first auxiliary pump 220 is connected between the power supply voltage Vdd and the first auxiliary node Na1 and receives the first auxiliary NMOS transistor NM1 and the first and the first precharge signals P as gates. The second auxiliary NMOS transistor NM2, which is connected between the second auxiliary nodes Na1 and Na2 and whose gate is connected to the third auxiliary node Na3, is connected between the first and third auxiliary nodes Na1 and Na3. One end is respectively connected to the third auxiliary NMOS transistor Na3 and the first to third auxiliary nodes Na1 to Na3 having a gate connected to the second auxiliary node Na2, and the second to fourth clocks are respectively connected to the other ends thereof. Three auxiliary capacitors Cs1 to Cs3 to which the signals clk2 to clk4 are applied are provided.

The second auxiliary pump 230 is connected between the power supply voltage Vdd and the fourth auxiliary node Na4 and receives the fourth auxiliary NMOS transistor NM4 and the fourth and the second precharge signal Q applied to the gate. The fifth auxiliary NMOS transistor NM5 and the fourth and sixth auxiliary nodes Na4 and Na6 are connected between the fifth auxiliary nodes Na4 and Na5 and the gate is connected to the sixth auxiliary node Na6. One end is respectively connected to the sixth auxiliary NMOS transistor Na6 and the fourth to sixth auxiliary nodes Na4 to Na6 having a gate connected to the fifth auxiliary node Na5, and the first, third and Three auxiliary capacitors Cs4 to Cs6 to which the fourth clock signals clk1, clk3, and clk4 are applied.

The configurations of the first and second auxiliary pumps 220 and 230 are the same, except that the first auxiliary pump 220 supplies the second to fourth clock signals clk2 to clk4 and the first precharge signal P. FIG. On the other hand, the second auxiliary pump 230 is different from the first, third, and fourth clock signals clk1, clk3, and clk4.

Referring to the operation of the first auxiliary pump 220, when the first clock signal clk1 transitions to the Vdd level, the first precharge signal P transitions to the 2Vdd level. Since the first precharge signal P has risen by 2Vdd level, the first auxiliary NMOS transistor NM1 precharges the first auxiliary node Na1 to the Vdd level. Thereafter, when the third clock signal clk3 transitions to the Vdd level, the first auxiliary node Na1 has a voltage of 2Vdd level. Since the second auxiliary NMOS transistor NM2 is connected to a gate of the third auxiliary node Na3, a voltage of the first auxiliary node Na1 is applied to the second auxiliary node Na2, and the second auxiliary node Na1 is applied to the second auxiliary node Na1. ) Has a voltage of 3Vdd level while the fourth clock signal clk4 is maintained at the Vdd level, so that the third auxiliary NMOS transistor NM3 uses the threshold voltage based on the voltage level of the first auxiliary node Na1. When the voltage of 2Vdd level is transferred to the third auxiliary node Na3 without the voltage drop and the second clock signal clk2 transitions to the Vdd level, the third auxiliary node Na3 is boosted to the 3Vdd level and the third voltage of the 3Vdd level is reduced. 1 Output the auxiliary signal (A).

Therefore, the first auxiliary pump 220 sequentially applies a voltage of 3 Vdd level through the 2 Vdd level from the Vdd level to the gate of the first switch NMOS transistor NT1.

Meanwhile, the second auxiliary pump 230 is turned on in response to the second precharge signal Q having the Vdd level to precharge the fourth auxiliary node Na4 to the Vdd level. When the third clock signal clk3 transitions to the Vdd level, the fifth auxiliary node Na5 has a voltage level of the Vdd level, thereby turning on the sixth auxiliary NMOS transistor NM6. However, since the fourth clock signal clk4 transitions from the Vdd level to the Vss level, the voltage level of the fourth auxiliary node Na4 does not change. Therefore, the sixth auxiliary node N6 is at the Vdd level. Since the first clock signal clk1 also maintains the Vss level, the voltage of the sixth auxiliary node N6 is maintained at the Vdd level and is applied to the gate of the second switch NMOS transistor NT2 as the second auxiliary signal B. .

As a result, the first and second auxiliary signals A and B remain at Vdd level when the first and second switch transistors NT1 and NT2 do not need to transfer charges, but 3Vdd level when they need to transfer charges. The gate voltages of the first and second switch transistors NT1 and NT2 are stepped up to completely transfer the boosted voltages of the first and second nodes N1 and N2 having a 2Vdd level. Also, even when the first and second clock signals clk1 and clk2 transition to the Vss level, the first and second auxiliary pumps 220 and 230 may maintain the 2Vdd level in response to the third and fourth clock signals clk3 and clk4. Since the first and second auxiliary signals A and B of Fig. 3 are outputted, they show improved charge transfer capability over the CMOS charge pump of Fig. 3.

6A to 6C are simulation diagrams for comparing the conventional charge pump with the charge pump of the present invention in FIGS. 3 and 5. The conventional NMOS type charge pump, the charge pump using the PMOS type charge pump and the level shifter, and the CMOS charge pump of the present invention shown in FIGS. 3 and 5 are subjected to an 80 nm MOS process, and the power supply voltage Vdd is 1.5V. 6A is a graph comparing the output voltage according to the load current, FIG. 6B is a graph comparing the change of the bulk voltage according to the load current, and FIG. 6C is a graph comparing the pumping speed.

 Referring to FIG. 6A, when the load current is 0.8 mA, the CMOS charge pump of FIG. 5 improves the output voltage by about 56% over the conventional NMOS type charge pump and about 47% over the PMOS type charge pump. This is because the CMOS charge pump of the present invention uses a PMOS transistor and an NMOS transistor together as a transfer switch, and thus there is no reduction in threshold voltage and can transfer a large amount of current. I never do that.

Referring to Figure 6B, the CMOS charge pump of the present invention likewise operates less sensitive to changes in load current than two phase charge pumps that pump bulk. That is, even if the load current changes, the bulk forward voltage is kept below 0.4V. Given that the threshold voltage of PMOS transistors used in current memory systems is 0.5-0.6V, the CMOS charge pump of the present invention maintains a very stable bulk voltage.

Referring to FIG. 6C, the CMOS charge pump of the present invention exhibits a pumping characteristic of about 9 to 10% faster when the 95% of the output voltage is reached as compared with the conventional PMOS type charge pump.

Therefore, the CMOS charge pump of the present invention significantly improves the charge transfer capacity and the pumping speed, and stabilizes the bulk forward bias voltage of the PMOS transistor to within 04V to ensure stability with high efficiency.

For convenience of description, the level of each signal is described as a Vss level and a Vdd level, but it is obvious that the level of each signal can be changed according to design. 3 and 5 show only a CMOS charge pump having a one-stage configuration, it is obvious that it can be composed of a plurality of stages.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (12)

A precharge driver configured to generate first and second precharge signals of first and second levels in response to the first and second clock signals; A precharge unit configured to precharge first and second nodes to the first level in response to the first and second precharge signals; A booster boosting the first node to the second level in response to a third clock signal and boosting the second node to the second level in response to a fourth clock signal; A plurality of switch NMOS transistors which transfer voltages of the first and second nodes to output nodes in response to the first and second precharge signals, respectively; and the first and second voltages in response to voltage levels of the first and second nodes. And a transfer switch unit including a plurality of switch PMOS transistors to transfer a voltage of a second node to the output node. And Pumping a bulk node connected to bulks of the plurality of switch PMOS transistors in response to the third and fourth clock signals, and converting voltages of the first and second nodes in response to voltages of the first and second nodes. A CMOS charge pump comprising a bulk pumping unit for applying to a bulk node. The method of claim 1, wherein the precharge driving unit A first driving transistor connected between a power supply voltage and a third node at which the first precharge signal is output, and a gate connected to a fourth node at which the second precharge signal is output; A second driving transistor connected between the power supply voltage and the fourth node and having a gate connected to the third node; A first precharge capacitor having one end connected to the third node and receiving the first clock signal at the other end; And And a second precharge capacitor having one end connected to the fourth node and the other end applied with the second clock signal. The method of claim 2, wherein the precharge unit A first precharge transistor connected between the power supply voltage and the first node and receiving the first precharge signal through a gate; And And a second precharge transistor connected between the power supply voltage and the second node and receiving the second precharge signal as a gate. The method of claim 3, wherein the boosting unit A first boosting capacitor having one end connected to the first node and receiving the third clock signal at the other end; And And a first boosting capacitor connected to the first node at one end thereof and receiving the third clock signal at the other end thereof. The method of claim 4, wherein the bulk pumping unit A first bulk transistor connected between the first node and the bulk node, a gate connected to the second node, and a bulk connected to the bulk node; A second bulk transistor connected between the second node and the bulk node, a gate connected to the first node, and a bulk connected to the bulk node; And And a first and a second bulk capacitor, one end of which is connected to the bulk node and the other end of which receives the third and fourth clock signals. The method of claim 5, wherein the first to fourth clock signal is The first and second clock signals have a phase difference of 180 degrees from the third and fourth clock signals, respectively, and the third and fourth clock signals do not overlap each other in a third level period, and the first and second clock signals do not overlap each other. And the third clock signal and the second and fourth clock signals are set such that the first level periods do not overlap each other. The method of claim 6, wherein the first to third levels are COMS charge pump, characterized in that each of the power supply voltage level, twice the voltage level and the ground voltage level. The method of claim 7, wherein the transfer switch unit A first switch NMOS transistor connected between the first node and the output node and receiving the second precharge signal through a gate; A second switch NMOS transistor connected between the second node and the output node and receiving the first precharge signal through a gate; A first switch PMOS transistor connected between the first node and the output node and having a gate connected to the second node; And And a second switch PMOS transistor coupled between the second node and the output node and whose gate is connected to the first node. The method of claim 7, wherein the CMOS charge pump A first auxiliary pumping unit configured to output a first auxiliary signal having a fourth level higher than the second level in response to the first precharge signal and the second to fourth clock signals; And And a second auxiliary pumping part configured to output the second auxiliary signal of the fourth level in response to the second precharge signal and the first, third, and fourth clock signals. The method of claim 9, wherein the first auxiliary pumping unit A first auxiliary transistor connected between the power supply voltage and a first auxiliary node and receiving the first precharge signal as a gate; A second auxiliary transistor connected between the first auxiliary node and a second auxiliary node and having a gate connected to a third auxiliary node to which the first auxiliary signal is output; A third auxiliary transistor connected between the first auxiliary node and the third auxiliary node and having a gate connected to the second auxiliary node; A first auxiliary capacitor having one end connected to the first auxiliary node and receiving a third clock signal at the other end; A second auxiliary capacitor having one end connected to the second auxiliary node and receiving a fourth clock signal at the other end; And And a third auxiliary capacitor having one end connected to the third auxiliary node and receiving the second clock signal on the other end thereof. The method of claim 9, wherein the second auxiliary pumping unit A fourth auxiliary transistor connected between the power supply voltage and a fourth auxiliary node and receiving the second precharge signal as a gate; A fifth auxiliary transistor connected between the fourth auxiliary node and a fifth auxiliary node and having a gate connected to a sixth auxiliary node to which the second auxiliary signal is output; A sixth auxiliary transistor connected between the fourth auxiliary node and the sixth auxiliary node and having a gate connected to the fifth auxiliary node; A fourth auxiliary capacitor having one end connected to the fourth auxiliary node and receiving a fourth clock signal at the other end; A fifth auxiliary capacitor having one end connected to the fifth auxiliary node and receiving a third clock signal at the other end; And And a sixth auxiliary capacitor having one end connected to the sixth auxiliary node and receiving the first clock signal on the other end thereof. The method of claim 11, wherein the transfer switch unit A first switch NMOS transistor connected between the first node and the output node and receiving the first auxiliary signal through a gate; A second switch NMOS transistor connected between the second node and the output node and receiving the first auxiliary signal through a gate; A first switch PMOS transistor connected between the first node and the output node and having a gate connected to the second node; And And a second switch PMOS transistor coupled between the second node and the output node and whose gate is connected to the first node.