CN114157140A

CN114157140A - Charge pump circuit

Info

Publication number: CN114157140A
Application number: CN202111443380.2A
Authority: CN
Inventors: 黄明永
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-03-08

Abstract

The invention discloses a charge pump circuit, which comprises a depletion type high-voltage MOS tube and an enhancement type high-voltage MOS tube, wherein the node potential is ensured through the depletion type tube, so that the enhancement type tube is fully opened, meanwhile, the depletion type tube does not supply power to a load, so that the voltage of the node potential is relatively stable, the depletion type tube uses the MOS tube with a small gate length ratio and a larger channel length, and the problem of backward flow current is effectively solved.

Description

Charge pump circuit

Technical Field

The present invention relates to the field of semiconductor device manufacturing processes, and more particularly, to a charge pump circuit.

Background

A charge pump (charge pump), also known as a switched capacitor voltage converter, is a DC-DC (converter) that uses a so-called "flying" or "pumping" capacitor (rather than an inductor or transformer) to store energy. A charge pump is a dc-dc converter that uses a capacitor as an energy storage element to generate an output voltage that is greater than an input voltage or a negative output voltage. The electrical efficiency of the charge pump circuit is high, about 90-95%, and the circuit is relatively simple.

The charge pump utilizes some switching elements to control the voltage connected to the capacitor. For example, a lower input voltage may be used to generate a higher pulsed voltage output in conjunction with a two-phase cycle. In the first phase of the cycle, the capacitor is connected to the supply terminal and thus charged to the same voltage as the supply voltage, and in the first phase the circuit configuration is adjusted so that the capacitor is connected in series with the supply voltage. Without considering the effect of leakage current, also assuming no load, the output voltage would be twice the input voltage (original supply voltage plus the voltage across the capacitor). The pulse characteristic of the higher output voltage may be filtered with a filter capacitor at the output.

Charge pumps can be divided into: a boost pump of a switching regulator, a non-regulation capacitance type charge pump and a regulation capacitance type charge pump. The working process is as follows: energy is first stored and then released in a controlled manner to achieve the desired output voltage. A switching regulator boost pump uses an inductor to store energy, while a capacitive charge pump uses a capacitor to store energy. The capacitive charge pump realizes voltage boosting through a switch array, an oscillator, a logic circuit and a comparison controller, and adopts a capacitor to store energy. The charge pump can provide an output voltage of +/-2 times by using an external capacitor only. Its losses mainly come from the Equivalent Series Resistance (ESR) of the capacitor and the rds (on) of the internal switching transistor. The charge pump converter does not use an inductor and therefore its radiated EMI is negligible. The input noise can be filtered out by a small capacitor. The output voltage of the charge pump is precisely preset in factory production and can be adjusted by the linear regulator on the back-end chip, so that the charge pump can increase the switching stage number of the charge pump as required during design so as to provide enough activity space for the back-end regulator. The charge pump is very suitable for the design of portable application products, and is a system consisting of a reference circuit, a comparison circuit, a conversion circuit and a control circuit.

Inside the flash chip, a charge pump is a necessary circuit module. What structure the charge pump takes depends on what devices the process platform can provide. On the A process platform of a certain process node, a 5V high-voltage device (NCHH) and a 5V Native high-voltage device (NCHHZ) are provided, and on the A process platform, a power supply with 1.2V +/-10% is required to generate a voltage of 9-10V, and the characteristics of the NCHH device and the NCHHZ device are shown in the table below.

5V NCHH，W/L＝9/0.702(Vdd＝5V)	LSL	Typ	HSL	Unit
					Vt_Lin(Vg@Vd＝0.1V,Vs＝Vb＝0@Id＝0.1xW/L(uA))	0.52	0.62	0.72	V
Idsat(Id@Vg＝Vd＝Vdd,Vs＝Vb＝0)	315	375	435	uA/um
					Ioff(Id@Vg＝0,Vd＝5.5V,Vs＝Vb＝0)	--	1	100	pA/um
BVsd(@ID＝5nA/um)	9	--	--	V
					BVGPW(@Ig＝-10nA)	--	--	-12	V
5V Native NCHHZ，W/L＝9/1.62
					Vt_Gmax(Vd＝0.1V,Vd＝0.1,Gmmax method)	-0.27	-0.12	0.03	V
Ids(Id@Vg＝Vd＝Vdd＝5V,Vs＝Vb＝0)	328	408	488	uA/um

Watch 1

As shown in the above table, if the 5V high voltage device NCHH is selected and Vth is between 0.52V and 0.72V, and under the influence of the core/temperature/body bias, Vth can reach about 2V, i.e. even if 2 x vdd (2.16V to 2.64V) is used as the clock CLK, it is difficult to transfer charges from the previous stage to the next stage.

If 5V Native high-voltage device NCHHZ is selected, the problem of charge pump is not caused due to the low Vt, however, when the Vt is negative, the situation that the 5V Native NCHHZ is used as a switch tube can occur that the switch tube can not be completely closed, the charge can flow backwards from the next stage to the previous stage, the power consumption is large under the condition of no load, and the standby current of the whole flash IP is large.

Disclosure of Invention

The present invention provides a charge pump circuit to prevent the current from flowing backward.

In order to solve the above problems, the charge pump circuit according to the present invention is composed of a plurality of MOS transistors and a plurality of capacitors, and has a connection structure in which first ends of first to fourth MOS transistors are connected in parallel to form an input terminal VIN of the charge pump circuit, a third end of the first MOS transistor is connected to a second end of a third MOS transistor, a third end of the second MOS transistor is connected to a second end of the fourth MOS transistor, a third end of the third MOS transistor is connected to a second end of the first MOS transistor, and a third end of the fourth MOS transistor is connected to a second end of the second MOS transistor;

after being in short circuit with the first end and the second end of the fifth MOS tube and the sixth MOS tube, the fifth MOS tube and the sixth MOS tube are respectively connected with the second ends of the first MOS tube and the second MOS tube, and the third end of the fifth MOS tube is in short circuit with the third end of the sixth MOS tube; one end of the first capacitor is connected with the second end and the third end of the fifth MOS short circuit, and the other end of the first capacitor is grounded; one end of the second capacitor is connected with the second end and the third end of the sixth MOS short circuit, and the other end of the second capacitor is grounded;

the first end and the second end of the seventh MOS tube and the second end of the eighth MOS tube are respectively connected with the second end of the third MOS tube and the second end of the fourth MOS tube after being in short circuit, and the third end of the seventh MOS tube is in short circuit with the third end of the eighth MOS tube; one end of the third capacitor is connected with the first end and the second end of the seventh MOS short circuit, and the other end of the third capacitor is grounded; one end of the fourth capacitor is connected with the first end and the second end of the eighth MOS short circuit, and the other end of the fourth capacitor is grounded;

the third end of the ninth MOS is connected with the second end of the third MOS, the second end of the tenth MOS and the second end of the eleventh MOS, the third end of the tenth MOS is connected with the second end of the second MOS, the second end of the ninth MOS and the second end of the twelfth MOS, the ninth MOS is connected with the second end and the third end of the tenth MOS, and the serial node is connected with the substrate electrodes of the eleventh MOS and the twelfth MOS;

the first end of the eleventh MOS is in short circuit connection with the drain of the twelfth MOS to form the output end VOUT of the charge pump circuit;

and the differential clock signals respectively pass through the first input module and the second input module and then are respectively input to a third end of the fifth MOS and the sixth MOS which are in short circuit, and a third end of the seventh MOS and the eighth MOS which are in short circuit.

The further improvement is that the first MOS and the fourth MOS are depletion type high voltage MOS, and other MOS tubes are enhancement type high voltage MOS tubes.

The further improvement is that the first end of each MOS tube is a source/drain end, the second end is a drain/source end, and the third end is a gate end.

In a further improvement, the first to eighth MOS are NMOS, and the ninth to twelfth MOS are PMOS.

In a further improvement, the width-to-length ratio of the gates of the first and fourth MOS is smaller than the width-to-length ratio of the gates of the second and third MOS.

In a further refinement, the charge pump circuit further includes a clock circuit that provides a differential clock signal to the charge pump circuit.

In a further improvement, the clock circuit comprises a plurality of not gates to form two paths of outputs, and the clock input signal forms a differential clock signal after passing through the plurality of not gates.

The clock circuit converts a clock input signal into a differential clock signal through two branches, wherein the first branch is two cascaded NOT gates, the clock input signal forms a Positive signal of the differential clock signal after passing through the first branch, and the clock input signal forms a Negative signal of the differential clock signal after passing through the second branch.

The further improvement is that a Positive signal in the differential clock signal controls a third end of the fifth MOS and the sixth MOS in short circuit after passing through the first input module, and a Negative signal in the differential clock signal controls a third end of the seventh MOS and the eighth MOS in short circuit after passing through the second input module.

According to the charge pump circuit provided by the invention, the problem of current extraction is solved and the problem of reverse current is effectively prevented by combining and selecting the high-voltage device NCHHZ and the high-voltage device NCHHZ.

Drawings

Fig. 1 is a schematic diagram of a charge pump circuit according to the present invention.

Fig. 2 is a schematic diagram of a simulation of the circuit arrangement shown in fig. 1.

Detailed Description

The following detailed description of the present invention is provided with reference to the accompanying drawings, and the technical solutions in the present invention will be clearly and completely described, but the present invention is not limited to the following embodiments. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is noted that the drawings are in greatly simplified form and that non-precision ratios are used for convenience and clarity only to aid in the description of the embodiments of the invention. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity, and the same reference numerals denote the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "adjacent to …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on …," "directly adjacent to …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

An embodiment of a charge pump circuit according to the present invention is shown in fig. 2, and the circuit structure includes a plurality of MOS transistors and a plurality of capacitors, and includes M1-M12 and C1-C4, where M1-M8 are NMOS, M9-M12 are PMOS, and the connection structure is that drain terminals of M1-M4 are connected in parallel to form an input terminal VIN of the charge pump circuit, a gate terminal of the M1 is connected to a source terminal of a M3 transistor, a gate terminal of the M2 transistor is connected to a source terminal of a M4 transistor, a first gate terminal of the M3 transistor is connected to a source terminal of the M1, and a gate terminal of the M4 transistor is connected to a source terminal of the M2 transistor.

The source ends and the drain ends of the M5 and M6 tubes are respectively connected with the source ends of M1 and M2 after being in short circuit, and the grid end of M5 is in short circuit with the grid end of M6; one end of the first capacitor C1 is connected with the source and drain end shorted by the M5, and the other end of the first capacitor C1 is grounded; one end of the second capacitor C2 is connected with the source and drain end shorted by the M6, and the other end of the second capacitor C2 is grounded.

The source-drain ends of the M7 and M8 tubes are respectively connected with the source ends of M3 and M4 after being in short circuit, and the gate end of M7 is in short circuit with the gate end of M8; one end of the third capacitor C3 is connected with the source and drain end shorted by the M7, and the other end of the third capacitor C3 is grounded; one end of the fourth capacitor C4 is connected with the source and drain end shorted by the M8, and the other end of the fourth capacitor C4 is grounded.

The gate end of M9 is connected with the source end of M3, the source end of M10 and the source end of M11, the gate end of M10 is connected with the source end of M2, the source end of M9 and the source end of M12, the source and drain ends of M9 and M10 are connected in series, and the nodes connected in series are connected with the substrate electrodes of M11 and M12.

And the output terminal VOUT of the charge pump circuit is formed after the drain terminal of the M11 is shorted with the drain terminal of the M12.

The differential clock signals CK and CKb are amplified by the first input module and the second input module respectively and then input to the grid ends which are short-circuited by M5 and M6 and the grid ends which are short-circuited by M7 and M8 respectively. Wherein, CK is a Positive limit number in the differential clock signal, and CKb is a Negative signal in the differential clock signal. The first and second input modules are amplification circuits, which increase the amplitude of the clock signal to, for example, 2 times, and then input the clock signal to the next stage, for example, the original clock signal amplitude is 0 to Vdd, and after amplification, the clock signal amplitude becomes 0 to 2Vdd, so as to enhance the control capability of the next stage, i.e., M5, M6, M7, and M8.

The differential clock signal is generated by a clock circuit, as shown in the lower part of fig. 2, the clock circuit comprises a plurality of not gates, two branches are formed to output and form the differential clock signal, wherein the first branch is two cascaded not gates, the clock input signal forms a Positive signal of the differential clock signal after passing through the first branch, and the clock input signal forms a Negative signal of the differential clock signal after passing through the second branch.

The Positive signal CK in the differential clock signal controls the grid end of M5 and M6 in short circuit after passing through the first input module, and the Negative signal CKb in the differential clock signal controls the grid end of M7 and M8 in short circuit after passing through the second input module.

In the circuit structure, the M1 and the M4 are depletion type high voltage MOS transistors, and the other MOS transistors are enhancement type high voltage MOS transistors.

The width-to-length ratios of the gates of M1-M4 are smaller than those of M2 and M3, but the channel lengths are slightly longer.

In the structure shown in fig. 1, four nodes a1 and A, B, B1 are respectively formed at the source ends of M1-M4, when the circuit is in operation, the voltages of the nodes a1 and B1 are higher than the voltage of the node A, B because the M1 and M4 are high-voltage depletion type tubes, namely, NCHHZ, so that the 5V NCHH can be sufficiently turned on, the voltages of the nodes a1 and B1 do not decrease with time because the load current does not draw the charges at the nodes a1 and B1, and the 5V nat Nch (namely, M1 and M4) connected with the nodes a1 and B1 can use devices with small W/L ratio because the nodes a1 and B1 do not need to draw large current, and the problem of backward current can be effectively prevented by increasing the channel length.

Fig. 2 is a simulation graph of the charge pump circuit of the present invention, in which the top curve is the VOUT output curve, and the third and fourth curves below are the voltages of the nodes a1 and B1, respectively, and after the whole circuit is started, the potentials of the nodes are relatively stable, and the overall performance is superior to that of the conventional structure.

The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A charge pump circuit, comprising: the charge pump circuit is characterized by comprising a plurality of MOS (metal oxide semiconductor) tubes and a plurality of capacitors, wherein the connection structure is that first ends of first to fourth MOS tubes are connected in parallel to form an input end VIN of the charge pump circuit, a third end of the first MOS tube is connected with a second end of a third MOS tube, a third end of the second MOS tube is connected with a second end of the fourth MOS tube, a third end of the third MOS tube is connected with a second end of the first MOS tube, and a third end of the fourth MOS tube is connected with a second end of the second MOS tube;

and the differential clock signals respectively pass through the first input module and the second input module and then are respectively input to a third end of the fifth MOS and the sixth MOS in short circuit, and a third end of the seventh MOS and the eighth MOS in short circuit.

2. The charge pump circuit of claim 1, wherein: the first MOS and the fourth MOS are depletion type high-voltage MOS tubes, and other MOS tubes are enhancement type high-voltage MOS tubes.

3. The charge pump circuit of claim 1, wherein: the first end of each MOS tube is a source/drain end, the second end is a drain/source end, and the third end is a grid end.

4. The charge pump circuit of claim 1, wherein: the first to eighth MOS are NMOS, and the ninth to twelfth MOS are PMOS.

5. The charge pump circuit of claim 2, wherein: the width-length ratio of the grid electrode of the first MOS and the grid electrode of the fourth MOS is smaller than that of the second MOS and the third MOS.

6. The charge pump circuit of claim 1, wherein: the charge pump circuit further includes a clock circuit that provides a differential clock signal to the charge pump circuit.

7. The charge pump circuit of claim 6, wherein: the clock circuit comprises a plurality of NOT gates to form two paths of output, and a clock input signal forms a differential clock signal after passing through the NOT gates.

8. The charge pump circuit of claim 7, wherein: the clock circuit converts a clock input signal into a differential clock signal through two branches, wherein the first branch is two cascaded NOT gates, the clock input signal forms a Positive signal of the differential clock signal after passing through the first branch, and the clock input signal forms a Negative signal of the differential clock signal after passing through the second branch.

9. The charge pump circuit of claim 1, wherein: the Positive signal in the differential clock signal controls the third end of the fifth MOS and the sixth MOS in short circuit after passing through the first input module, and the Negative signal in the differential clock signal controls the third end of the seventh MOS and the eighth MOS in short circuit after passing through the second input module.

10. The charge pump circuit of claim 1, wherein: the first input module and the second input module are amplitude multiplication circuits, and the differential clock signals are input to the next stage after being subjected to amplitude multiplication.