KR20090096864A - Method of forming metal line a semiconductor device - Google Patents

Abstract

A method of forming metal line of a semiconductor device is provided to reduce the number of a metal deposition process and an insulating film deposition by forming an even or an odd metal wire having a step height in patterning process at a time. In a method of forming metal line of a semiconductor device, a drain contact plugs contacting a drain(110) is formed inside a first insulating film of the semiconductor device. A recess process for lowering the height of drain contact plugs included in the even or odd group among drain contact plugs is performed. A metal layer for forming a metal wirings included in the even and the odd group is formed on the entire structure including the recess area.

Description

Method of forming metal line a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and to a method for forming metal wirings in semiconductor devices that can simplify the process of forming even and odd metal wirings having steps.

As the size of devices decreases due to the recent trend toward higher integration of semiconductor devices, the circuit line width becomes very fine, and the pitch of the bit lines is also very small. Interferences between the bit lines, a decrease in cell current, and a decrease in operating speed are occurring. In addition, in severe cases, a bridge between adjacent bit lines causes a fatal adverse effect on the operation of the device.

In order to solve this problem, a method of improving the resistance problem and the bridge problem of the bit line by providing a step between bit lines belonging to the even group and bit lines belonging to the odd group has been proposed. Hereinafter, a bit line forming method having a conventional step will be briefly described with reference to FIGS. 1A to 1G. First, a first interlayer insulating film 14 is formed on a semiconductor substrate 10 on which a predetermined lower structure including a gate (not shown) and a junction region (here, only a drain is shown; 12) is formed. The first interlayer insulating layer 14 corresponding to the region is etched to form a first contact hole (not shown) that exposes the drain 12. Then, the first contact hole is filled with a conductive material such as polysilicon and then planarized by a chemical mechanical polishing (hereinafter referred to as "CMP") process using the first interlayer insulating film 14 as a polishing stop film. As a result, a drain contact plug (hereinafter referred to as 'DCP') is formed in the first contact hole (FIG. 1A). Such drain contact plugs are classified into even drain contact plugs DCPe and odd drain contact plugs DCPo.

Subsequently, a recess process of the even drain contact plug DCPe is performed to the thickness of the desired bit line to form a recess region (not shown) on the even drain contact plug DCCP (FIG. 1B). Subsequently, the recess region is filled with a metal material such as tungsten (W) or aluminum (Al), and then planarized by a CMP process using the first interlayer insulating film 14 as a polishing stop film, thereby evening the recess region. A line BLe is formed (FIG. 1C).

Then, the inter-wire insulating film 16 is formed on the entire structure including the even bit line BLe (FIG. 1D), and the inter-wire insulating film 16 corresponding to the odd-drain contact plug DCPo is etched. A second contact hole (not shown) exposing the anode drain contact plug DCPo is formed (FIG. 1E). Subsequently, after filling the second contact hole with a metal material such as tungsten (W) or aluminum (Al), the second contact hole is flattened by a CMP process using the inter-metallic insulating film 16 as a polishing stop film. An odd bit line BLo is formed in FIG. 1F. Subsequently, the second interlayer insulating layer 18 is formed on the entire structure including the odd bit line BLo to complete the bit line forming process.

According to the conventional method of forming the bit line as described above, the advantage that the resistance between the bit lines due to the decrease in the pitch between the bit lines due to the high integration can be largely solved. However, in the conventional bit line forming method, since a large number of metal material deposition and CMP processes are used to form the step between the bit lines, a significant cost and processing time loss occurs. This not only increases manufacturing costs but also results in lower process yields and productivity.

The present invention provides a semiconductor device capable of eliminating CMP processes for forming metal wirings by forming even and odd metal wirings having a step at a time in a patterning process after metal layer deposition, and reducing the number of metal material deposition and insulation film deposition processes. A metal wiring forming method is provided.

Metal wire forming method of a semiconductor device according to an embodiment of the present invention, Providing a semiconductor substrate having drain contact plugs in contact with a drain in a first insulating layer, and recesses for lowering heights of drain contact plugs belonging to an even or odd group of the drain contact plugs Performing a process, forming a metal layer for forming metal wires belonging to the even and odd groups on the entire structure including the recessed region, and first metal wires belonging to the even or odd groups in the recessed region being formed Patterning the metal layer such that second metal wires belonging to the remaining group of metal wires are formed on the first insulating film and the planarized drain contact plugs, and on the first insulating film including the first and second metal wires. 2 forming an insulating film.

In the above, the recess process sets the height of the target metal wiring to a target etching target. The metal layer fills the recess region and is further deposited by the height of the target metal wiring to be formed on the first insulating film and the planarized drain contact plugs.

In patterning the metal layer, a mask corresponding to the line width of the target metal wiring to be formed on the first insulating layer and the planarized drain contact plugs is used as an etching mask. In patterning the metal layer, the thickness of the metal layer formed on the first insulating layer is set as a target etching target.

The present invention has the following effects.

First, in forming the even and odd metal wirings having the step difference, after forming a metal layer on the insulating film including the recess region, the even and odd metal wirings having the step are formed at a time by a patterning process using a mask, and then the insulating film By forming the metal wires to complete the metal wire forming process, the CMP process for forming the metal wires may be omitted, and the number of metal material deposition and insulating film deposition processes may be reduced to simplify the process.

Second, process simplification can reduce manufacturing costs and improve process yield and productivity.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below, but to those skilled in the art It is preferred that the present invention be interpreted as being provided to more fully explain the present invention.

2A through 2E are cross-sectional views illustrating a method of forming metal wires in a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2A, a semiconductor substrate in which an even drain contact plug DCPe and an odd drain contact plug DCPo are alternately connected to the drain 110 in the first insulating layer 120. 100) is provided. Although not shown, a predetermined result such as a gate is formed on the semiconductor substrate 100 inside the first insulating layer 120. In this case, the even and odd drain contact plugs DCPe and DCPo are formed by a manufacturing method using a conventional damascene pattern. That is, the first insulating film 120 is formed on the semiconductor substrate 100 on which a predetermined result such as a gate and a junction region are formed, and then the first insulating film corresponding to the drain 110 is formed by an etching process using a mask (not shown). 120 is formed to form a contact hole (not shown) exposing the drain 110. Here, the first insulating layer 120 may be applied to any oxide-based material, for example, spin on glass (SOG), undoped silicate galss (USG), boron-phosphorus silicate glass (BPSG), and phosphorus silicalicate glass (PSG). ) And PETEOS (Plasma Enhanced Tetra Ethyl) Ortho Silicate) can be formed using any one selected from. Then, the contact hole is filled with a conductive material such as polysilicon, and then the contact hole is flattened by a chemical mechanical polishing (CMP) process using the first insulating film 120 as a polishing stop film. A drain contact plug is formed inside. Such drain contact plugs are classified into even drain contact plugs DCPe and odd drain contact plugs DCPo. In the case of a flash memory device, even and odd drain contact plugs DCPe and DCPo are formed between drain select lines (not shown).

Referring to FIG. 2B, a recess process for lowering the height of the even drain contact plug DCCP is performed. Here, the recess process uses an etch recipe having a higher etching ratio with respect to the even drain contact plug DCCPe than the first insulating film 120 in order to minimize the loss of the first insulating film 120 during the etching process. Do it.

In this case, the recess process etches the even drain contact plug DCCP by setting the height of the target even metal wiring as a target etching target. As a result, a portion of the sidewall of the first insulating layer 120 is exposed while the height of the even drain contact plug DCP is lowered, and a certain depth is recessed from the upper surface of the first insulating layer 120 on the even drain contact plug DCPe. A recessed region (not shown) is formed.

In addition, the height of the even drain contact plug DCPe is lower than that of the odd drain contact plug DCPo, so that there is a step between the even drain contact plug DCPe and the odd drain contact plug DCPo.

Referring to FIG. 2C, the metal layer 130 is formed on the odd-drain contact plug DCPo including the recess region and the first insulating layer 120. The metal layer 130 may be formed of tungsten (W), aluminum (Al), copper (Cu), or the like so that the even metal wiring and the odd metal wiring may be simultaneously formed. Can be.

In this case, the metal layer 130 fills the recess region on the even drain contact plug DCPe and further deposits the thickness of the target electrode metal wiring over the entire first insulating film 120 and the upper part of the drain drain contact plug DCPo. To form. As a result, the metal layer 130 is in contact with both the even and the odd drain contact plugs DCPe and DCPo.

Referring to FIG. 2D, the even and odd metal wires BLe and BLo corresponding to the even and odd drain contact plugs DCPe and DCPo are formed by a patterning process of the metal layer 130 using a mask (not shown). Here, the patterning process is performed using a mask equal to the line width of the target odd metal wiring BLO only in the region where the odd metal wiring BLO is to be formed. In this case, the patterning process is performed by setting the thickness of the metal layer 130 deposited on the first insulating layer 120 by the thickness of the target odd metal wiring as the target etching target. On the other hand, the mask may be formed of a photoresist pattern, in this case, the photoresist pattern may be formed by applying a photoresist on the metal layer 130 and patterning by exposure and development.

 In addition, the patterning process is performed using an etching recipe having a higher etching selectivity with respect to the first insulating film 120 than the metal layer 130 in order to minimize the loss of the first insulating film 120 in the etching process. That is, the patterning process may be performed by an etching process having a very good etching rate with respect to the metal layer 130 but having a very low etching rate with respect to the first insulating layer 120. According to an embodiment of the present invention, since the first insulating layer 120 is formed of an oxide, the etching process of the metal layer 130 may be performed by using an etching recipe having a higher etching selectivity with respect to the metal material than the oxide. desirable.

 As a result, the metal layer 130 corresponding to the recess region and the odd-drain contact plug DCPo is left by the patterning process of the metal layer 130 to form an even metal wiring BLe on the even-drain contact plug DCPe. At the same time, an odd metal wiring BLo is formed on the odd drain contact plug DCPo.

In this way, the even metal wiring BLe and the odd metal wiring BLO having the stepped structure are formed adjacent to each other. The even and odd metal lines BLe and BLo may be formed as bit lines.

Referring to FIG. 2E, the second insulating layer 140 is formed on the entire structure including the even and odd metal lines BLe and BLo to complete the metal line forming process. Here, the second insulating layer 140 is deposited to have a sufficient thickness for the subsequent contact process.

In the above description, since the expressions of even and adra are merely qualifiers for the purpose of convenience of explanation, those skilled in the art will readily understand that there is no technical difference even if they are actually interchanged.

The structure of the metal wirings BLe and BLo manufactured according to the manufacturing method of the present invention as described above has a desired stepped structure to reduce the resistance between the metal wirings BLe and BLo, while forming the metal wirings BLe and BLo. There is no need for a CMP process. In addition, the metal material deposition process for forming the metal wirings BLe and Bo is sufficient once, and further, the process of laminating an insulating film for insulating the metal wirings BLe and BLo is sufficient. .

As such, the metal wire forming method according to an embodiment of the present invention does not require an expensive CMP process at all, and the number of processes itself is greatly reduced as the metal material deposition process and the insulating film deposition process are omitted once. . Accordingly, the manufacturing cost can be reduced, and the process time can be shortened to improve productivity as well as to improve the process yield.

The present invention is not limited to the above-described embodiments, but may be implemented in various forms, and the above embodiments are intended to complete the disclosure of the present invention and to completely convey the scope of the invention to those skilled in the art. It is provided to inform you. Therefore, the scope of the present invention should be understood by the claims of the present application.

1A to 1G are cross-sectional views illustrating a conventional method for forming a bit line having a step difference.

2A through 2E are cross-sectional views illustrating a method of forming metal wires in a semiconductor device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 110 drain

120: first insulating film 130: metal layer

140: second insulating film

DCPe: Even Drain Contact Plug DCPo: Eod Drain Contact Plug

BLe: Even Metal Wiring BLo: Aude Metal Wiring

Claims (5)

Providing a semiconductor substrate having drain contact plugs in contact with the drain in the first insulating layer; Performing a recess process for lowering heights of drain contact plugs belonging to an even or odd group of the drain contact plugs; Forming a metal layer for forming metal wires belonging to the even and odd groups on the entire structure including the recess region; First metal wires belonging to the even or odd group are formed in the recess region, and second metal wires belonging to the remaining group of the metal wires are formed on the drain insulating plugs planarized with the first insulating layer. Patterning the metal layer; And Forming a second insulating film on the first insulating film including the first and second metal wires. The method of claim 1, And the recess process sets the height of the target metal wiring to the target etching target. The method of claim 1, And the metal layer fills the recess region and is further deposited by a height of a target metal wiring to be formed on the drain insulating plugs planarized with the first insulating layer. The method of claim 1, wherein in the metal layer patterning, And forming a mask corresponding to a line width of a target metal wiring to be formed on the first insulating film and the drain contact plugs planarized as an etching mask. The method of claim 1, wherein in the metal layer patterning, And forming a target etch target as a thickness of the metal layer formed on the first insulating film.

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