KR20090094571A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A semiconductor device and a method for fabricating the same are provided to implement the semiconductor device with a small size and a high yield by vertically stacking a first electronic device and a second electronic device with a three dimensional structure. A first insulating layer is formed on a first semiconductor substrate and includes a first micro electronic device(110) with a wiring layer made of a refractory metal material. A second semiconductor substrate is bonded on the first insulating layer. A second insulating layer is formed on the second semiconductor substrate and includes a second micro electronic device(210) electrically connected to the first micro electronic device. The first micro electronic device is a memory cell device(10) storing the data. The second micro electronic device is a logic device(20) controlling the memory cell device. The memory cell device is a volatile memory cell device or nonvolatile memory cell device. The logic device includes a redundancy circuit recovering a defect of the memory cell device.

Description

Semiconductor device and method for fabricating the same

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a three-dimensional integrated circuit manufactured by a reliable continuous process and a method of manufacturing a semiconductor device that can be easily formed.

With the development of semiconductor manufacturing technology, the demand for miniaturization and high integration of semiconductor devices has been continued, and various methods have been proposed to satisfy these requirements. One of such methods is to provide a semiconductor device having a three-dimensional structure.

On the other hand, the conventional three-dimensional structure semiconductor device is vertically bonded by joining another second semiconductor substrate and another already manufactured semiconductor device having an insulating layer on one semiconductor device composed of a base semiconductor substrate and an insulating layer already produced. Laminated by. In order to connect these semiconductor elements with each other, a technique of joining a semiconductor substrate (or an individual IC chip) prepared in advance using a large and deep connection line passing through the semiconductor substrate or an uneven structure is used. .

However, in order to electrically connect the upper and lower semiconductor elements, the semiconductor substrate should be bonded so that the upper semiconductor device is precisely aligned with the lower semiconductor device.

On the other hand, after completing the lower semiconductor device, a method of forming an upper semiconductor device using a single crystal semiconductor by melting a polycrystalline or amorphous semiconductor on an insulating layer using a laser to form a single crystal, or insulating a single crystal semiconductor substrate A method of forming a semiconductor device after epitaxial growth of a single crystal epitaxial layer over an insulating layer in a single crystal region covering the layer and partially exposed from the insulating layer has also been proposed.

However, in the above methods, since a high temperature process of 1000 ° C. or more is required when using a laser or growing an epitaxial layer, the influence of such a high temperature may be exerted on a prefabricated semiconductor device located below.

The problem to be solved by the present invention is to provide a semiconductor device having a three-dimensional integrated circuit manufactured by a reliable continuous process and a method of manufacturing a semiconductor device that can be easily formed.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to an embodiment of the present invention for solving the above problems, the first semiconductor substrate, the first insulation comprising a first microelectronic device having a wiring layer formed on the first semiconductor substrate and made of a refractory metal material A second insulating layer comprising a layer, a second semiconductor substrate bonded onto the first insulating layer, and a second insulating layer formed on the second semiconductor substrate and including a second microelectronic element electrically connected to the first microelectronic element, The first microelectronic devices are memory cell devices that store data, and the second microelectronic devices are logic devices that control the memory cell devices.

Meanwhile, a semiconductor device according to another embodiment of the present invention may include a first insulating layer and a first insulating layer including a first microelectronic device formed on a first semiconductor substrate and a wiring layer formed of a refractory metal material. A second insulating layer comprising a second semiconductor substrate bonded on the layer, a second insulating layer formed on the second semiconductor substrate and electrically connected to the first microelectronic device, and including a second microelectronic device made of a refractory metal material A third semiconductor substrate and a third microelectronic device formed on the third semiconductor substrate, wherein the first microelectronic device and the second microelectronic device are memory cell devices that store data, and the third microelectronic device. The device is characterized in that the logic devices that control the memory cell device.

In addition, the method for manufacturing a semiconductor device according to an embodiment of the present invention, to provide a first semiconductor substrate, to form a first microelectronic devices having a wiring layer of a refractory metal material on the first semiconductor substrate Forming a first insulating layer stacked in multiple layers to cover the first microelectronic devices, bonding a second semiconductor substrate on the first insulating layer, forming second microelectronic devices on the second semiconductor substrate, and Forming a second insulating layer stacked on the second microelectronic devices to cover the second microelectronic devices, the memory cell devices storing data as the first microelectronic devices, and controlling the memory cell devices with the second microelectronic devices. Forming logic elements.

And, a method for manufacturing a semiconductor device according to another embodiment of the present invention, providing a first semiconductor substrate, forming first microelectronic devices having a wiring layer of a refractory metal material on the first semiconductor substrate, Forming a first insulating layer stacked in multiple layers to cover the first microelectronic devices, bonding a second semiconductor substrate on the first insulating layer, and forming second microelectronic devices made of a refractory metal material on the second semiconductor substrate. And a second insulating layer formed on the second insulating layer to form a second insulating layer that is stacked in multiple layers to cover the second fine electronic devices, and electrically connects with the second fine electronic device on the third semiconductor substrate. Forming a third microelectronic device to be connected, and forming a third insulating layer stacked in multiple layers to cover the third microelectronic devices, wherein the first microelectronic device is formed. And forming memory cell elements for storing data in a second microelectronic element, and forming logic elements for controlling the memory cell element with a third microelectronic element.

Specific details of other embodiments are included in the detailed description and the drawings.

As described above, according to the semiconductor device of the present invention and a method of manufacturing the same, the first and second electronic devices are not disposed in a two-dimensional plane when forming a semiconductor device including the first and second microelectronic devices. The semiconductor device of a fine size can be implemented by vertically stacking the semiconductor device in a three-dimensional structure. Accordingly, the yield of the semiconductor device obtainable from one semiconductor substrate can be improved.

In addition, when the second microelectronic devices are formed on the first microelectronic device by forming the wiring layers and the connection wirings in the first microelectronic device with the refractory metal material, the first microelectronic device under the high temperature may be affected by the high temperature. It is possible to prevent the electrical characteristics and reliability of the deterioration. In particular, when the memory cell is formed at the lower portion and the logic is formed at the upper portion, the memory cell is connected to the refractory metal wiring having high resistivity, and the wiring connecting the logic formed at the upper portion is generally processed at a low temperature of 400 ° C. or lower. Therefore, it is possible to use copper (Cu) or aluminum (Al) wiring with low specific resistance, which has the advantage of enabling the logic element to operate at high speed.

In addition, since the second semiconductor substrate to be bonded on the first microelectronic element is bonded without the second microelectronic element formed thereon, precise substrate alignment is not required. Therefore, the manufacturing process of the semiconductor device can be facilitated, thereby providing additional effects such as shortening the process and reducing the manufacturing cost.

In addition, an additional microelectronic device layer may be laminated as needed, thereby providing an advantage such as manufacturing a semiconductor device capable of performing various functions.

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the technical field to which the present invention belongs. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, recesses, pads, patterns or structures are shown to be larger than actual for clarity of the invention. In the present invention, each layer (film), region, pad, recess, pattern or structure is formed on the substrate, each layer (film), region, pad or patterns "on", "top" or "bottom". When referred to as meaning that each layer (film), region, pad, recess, pattern or structure is formed directly over or below the substrate, each layer (film), region, pad or patterns, or Other layers (films), other regions, different pads, different patterns or other structures may additionally be formed on the substrate.

First, a structure of a semiconductor device according to exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a first microelectronic device 110 is formed on a first semiconductor substrate 100. The first microelectronic device 110 may be a MOS-FET, a DRAM, an SRAM, a PRAM, or a flash memory device. In addition, the first microelectronic device 110 may be part of one semiconductor device such as a DRAM. For example, the first microelectronic device 110 may be a memory cell device of a memory device or a logic device.

The first microelectronic device 110 is insulated over a multilayer interlayer insulating film and includes wiring layers 112 made of a refractory metal material. The wiring layers 112 are formed in multiple layers, and the wiring layers 112 positioned above and below may be electrically connected by a contact.

These wiring layers and contacts 112 are made of a refractory metal material having low resistance, low stress, good step coverage, and good coefficient of thermal expansion, and thus are less susceptible to subsequent high temperature processes. Accordingly, electrical characteristics and reliability of the first microelectronic device 110 may be maintained. Such refractory metal materials include, for example, tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten Nitride (TiN) and alloys thereof.

 On the other hand, the second semiconductor substrate 200 for forming the second microelectronic element 210 is bonded to the first microelectronic element 110. Specifically, the bonding layer 120 is formed on the interlayer insulating film covering the first fine electronic element 110, and the second semiconductor substrate 200 is bonded on the interlayer insulating film.

An insulating film 202 penetrating the second semiconductor substrate 200 is formed in a predetermined region of the second semiconductor substrate 200. Specifically, the insulating film 202 is formed on a region electrically connected to the first microelectronic element 110 below.

The second microelectronic devices 210 are formed on the second semiconductor substrate 200, and the wiring layers included in the second microelectronic devices 210 are also formed of a refractory metal material.

Here, the second microelectronic device 210 may be a semiconductor device having the same or similar function as the first microelectronic device 110 including, for example, a MOS-FET, a DRAM, an SRAM, a PRAM, or a flash memory device. However, in the exemplary embodiment of the present invention, the second microelectronic device 210 is a part of one semiconductor device, that is, a logic device for controlling the first microelectronic device 110 when the first microelectronic device 110 is a memory cell device of the memory device. It may be preferable to constitute such.

Meanwhile, the first microelectronic device 110 and the second microelectronic device 210 are electrically connected to each other in the insulating film 202 positioned between the first microelectronic device 110 and the second microelectronic device 210. The connection wiring 205 which connects is formed. The connection wiring 205 extends up and down in the insulating film 202 to be connected to the wiring layers of the first and second fine electronic devices 110 and 210.

In addition, according to the semiconductor device according to another exemplary embodiment of the present invention, the third semiconductor substrate 30 is bonded to the second microelectronic device 210 so that the third semiconductor substrate 300 is formed on the third semiconductor substrate 300. A semiconductor device including the fine electronic device 310 may be provided.

That is, the semiconductor substrates 200 and 300 may be sequentially stacked on the first semiconductor substrate 100, and thus, a plurality of microelectronic devices 210 and 310 may be provided in three dimensions. .

Such a three-dimensional semiconductor device may include fine electronic devices that perform different functions, and the stacked electronic devices may form one semiconductor device.

For example, the first microelectronic device 110 may include a volatile memory device, the second microelectronic device 120 may include a nonvolatile memory device, and the third microelectronic device 130 may include a first device. And a control logic circuit capable of controlling the second microelectronic devices 110 and 210.

As another example, the cell devices are provided as the first and second microelectronic devices 110 and 210, and the third microelectronic device 310 includes logic devices for controlling the first and second electronic devices. Can also constitute a semiconductor memory device.

The reason why such a configuration is preferable is that when the third fine electronic device 310 is formed on the upper part of the third electronic device 310, the wiring layers and the connection wirings in the microelectronic devices 110 and 210 formed on the lower part are formed of a refractory metal material. This is because the electrical characteristics and the reliability of the lower first and second microelectronic devices 110 and 210 may be prevented from being lowered due to the influence of the lower and upper surfaces. That is, when the memory cell is formed at the bottom and the logic is formed at the top, the memory cells are connected by refractory metal wiring having high resistivity, and the wiring connecting logic elements that are processed in a low temperature environment of 400 ° C. or lower is copper having low resistivity. (Cu) or aluminum (Al) wiring can be used, providing the advantage of enabling logic to operate at high speeds.

However, it is a matter of course that the embodiments of the present invention may be modified in various forms that are not limited thereto.

Next, a semiconductor device according to another exemplary embodiment of the present invention will be described with reference to FIG. 2.

2 is a cross-sectional view of a semiconductor device according to another embodiment of the present invention.

First, another embodiment of the present invention will be described with an example of forming a dynamic random access memory (DRAM) element as a volatile memory element on the first semiconductor substrate 100. However, the present invention is not limited thereto, and in another embodiment of the present invention, a semiconductor device formed on the first semiconductor substrate 100 may include a MOSFET, a logic circuit, an SRAM, a PRAM, or a flash memory. It will be apparent to those skilled in the art that a highly integrated semiconductor device may be included.

Referring back to FIG. 1, cell elements 10 of a semiconductor memory device are formed on a first semiconductor substrate 100. The cell elements 10 formed on the first semiconductor substrate 100 are covered by the interlayer insulating layers 120, 130, and 140 formed in multiple layers, and the bonding layer 150 is formed on the uppermost interlayer insulating layer 140. have. The second semiconductor substrate 200 is bonded on the bonding layer 150, and the logic elements 20 of the semiconductor memory device are positioned on the second semiconductor substrate 200.

In more detail, as shown in FIG. 1, a first semiconductor substrate 100 having an active region defined by the device isolation layer 102 is provided. The device isolation layer 102 is formed in the first semiconductor substrate 100 to have a predetermined depth. The first semiconductor substrate 100 may include a well region 104 ion-implanted with n-type or p-type impurities for each predetermined region.

Transistors formed through a conventional CMOS process are positioned on the active region of the semiconductor substrate 100. Specifically, gate electrodes 110 having a structure in which a gate insulating layer and a conductive layer are stacked are positioned, and source / drain regions 112 doped with impurities are formed in the first semiconductor substrate 100 at both sides of the gate electrodes 110. Formed.

The plurality of transistors formed on the first semiconductor substrate 100 are covered by the first interlayer insulating layer 120, and the contacts 122 electrically connected to the lower transistors are formed in the first interlayer insulating layer 120. It is. Capacitors 124 and 126 and wirings 132 are formed on the contacts 122 in the first interlayer insulating layer 120.

The capacitors 124 and 126 formed on the first interlayer insulating layer 120 may have a cylinder type structure or a stack type structure. In an embodiment of the present invention, a cylindrical structure will be described as an example.

In detail, a cylindrical lower electrode 124 may be formed on the first interlayer insulating layer 120, and a dielectric film (not shown) and an upper electrode 126 are conformally formed along the lower electrode 124. have. The lower electrode 124 and the upper electrode 126 of the capacitor may be formed of polysilicon or a metal material, and the dielectric layer (not shown) may be a single layer of tantalum oxide (Ta ₂ O ₅ ) or aluminum oxide (Al ₂ O ₃ ). Film or a tantalum oxide film / titanium oxide film or an aluminum oxide film / titanium oxide film.

The second interlayer insulating layer 130 covering the capacitors 124 and 126 is positioned on the first interlayer insulating layer 120, and the upper interconnections 132 connected to the lower wirings 132 on the second interlayer insulating layer 130. ) Is located.

As such, the contacts 122 and the wirings 132 included in the cell elements 10 of the semiconductor memory device formed on the first to second interlayer insulating layers 120 and 130 are formed of a refractory metal material. It is. For example, tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride film (TiN), tantalum nitride film (TaN), zirconium nitride film (ZrN), tungsten nitride film (TiN) and these materials Alloys thereof, and the like. These refractory metals have low resistance, low stress, excellent step coverage and excellent thermal expansion coefficient, and thus can maintain excellent reliability without changing the properties of the material even at high temperature subsequent processes.

As such, a third interlayer insulating layer 140 is formed on the second interlayer insulating layer 130 to completely cover the cell elements 10 of the semiconductor memory device and to planarize the upper portion thereof.

The second semiconductor substrate 200 is bonded to the third interlayer insulating layer 140 positioned on the uppermost layer on the first semiconductor substrate 100. Accordingly, the bonding layer 150 may be interposed between the third interlayer insulating layer 140 and the second semiconductor substrate 200.

Here, as the bonding layer 150, various curable adhesives, such as a photo-setting adhesive, such as a reaction hardening adhesive, a thermosetting adhesive, and an ultraviolet curing adhesive, and an anaerobic adhesive, are mentioned, for example. Can be. The bonding layer may be made of, for example, metal (Ti, TiN, Al), epoxy, acrylate, silicon, or the like.

As such, the logic elements 20 of the semiconductor memory device are positioned on the second semiconductor substrate 200 stacked on the cell elements 10 of the semiconductor memory device. The logic elements 20 formed on the second semiconductor substrate 200 may have redundancy circuits or errors that may be used instead of the selected defective cells when a defective cell occurs in the memory cell elements 10 formed below. An error correction circuit (ECC) or the like can be configured.

In more detail, the second semiconductor substrate 200 bonded on the third interlayer insulating layer 140 may include an insulating layer 202 formed to penetrate from an upper surface to a lower surface in a predetermined region. That is, the insulating layer 202 is positioned above the region electrically connected to the cell elements 10 below. The insulating layer 202 insulates the lower cell elements 10 and the connection wiring 221 electrically connecting the upper logic elements 20.

In addition, device isolation layers 204 defining an active region are formed in the second semiconductor substrate 200, and transistors 210 and 212 are formed on the active region of the second semiconductor substrate 200. . The transistors 210 and 212 formed on the second semiconductor substrate 200 may constitute the logic elements 20 of the semiconductor memory device.

As such, the fourth to sixth interlayer insulating layers 220, 230, and 240 formed over the multilayer are formed on the second semiconductor substrate 200 on which the transistors 210 and 212 are formed. In addition, the fourth to sixth interlayer insulating layers 220, 230, and 240 include wiring layers 232. In this case, the wiring layers 232 positioned on the second semiconductor substrate 200 may be made of a metal material such as aluminum (Al) or copper (Cu). In addition, the wiring layers 232 may be made of a refractory metal material such as titanium (Ti), titanium nitride (TiN), or tungsten (W).

In addition, the wiring layers 232 formed on the second semiconductor substrate 200 may be electrically connected to the wiring layers 132 disposed below through the connection wiring 221. The interconnection line 221 selectively connects the interconnection layer 132 of the memory cell element 10 and the interconnection layer of the logic element 20 through the insulating layer 202 included in the predetermined region of the second semiconductor substrate 200. Here, the connection wiring 221 may be made of a refractory metal material having excellent properties even at high temperatures. Accordingly, the memory cell devices 10 on the first semiconductor substrate 100 and the logic devices 20 on the second semiconductor substrate 200 may be electrically connected to each other.

As described above, the advantage of the three-dimensional circuit that configures the logic elements 20 through the process including the cell elements 10 and the heat treatment thereon is, as described above, the upper wiring layer 232 connecting the logic elements. Since silver can be manufactured at a low temperature, it is easy to use a metal wiring layer 232 such as aluminum (Al) or copper (Cu) with low specific resistance. Therefore, since the logic elements 20 can have a high circuit operation speed, logic elements are present in the lower layer, and can provide a higher circuit operation speed than the three-dimensional device in which cell elements are installed in the upper layer.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. 3 to 10.

3 to 10 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

First, referring to FIG. 3, a first semiconductor substrate 100 is prepared. The first semiconductor substrate 100 may be bulk silicon, bulk silicon-germanium, or a semiconductor substrate on which a silicon or silicon-germanium epi layer is formed. In addition, the first semiconductor substrate 100 may include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) ), Doped and undoped semiconductors, silicon epitaxial layers supported by the underlying semiconductor, and other semiconductor structures well known to those skilled in the art.

Then, the well region 104 is formed in the first semiconductor substrate 100 for each predetermined region. The well region 104 may be formed by ion implanting impurities into the surface of the first semiconductor substrate 100. The well region 104 may form a p-type well region by implanting ions such as boron in a region where an NMOS device is to be formed, and form an n-type well region by implanting ions such as phosphorus in a region where the PMOS device is to be formed. Can be.

Afterwards, device isolation layers 102 for defining an active region are formed on the first semiconductor substrate 100. The device isolation layers 102 may be formed by forming trenches in the first semiconductor substrate 100 and filling an insulating material such as an HDP (High Density Plasma) oxide film in the trench.

After defining an active region in the first semiconductor substrate 100, the gate insulating layer and the gate conductive layer are stacked and patterned on the first semiconductor substrate 100 to form the gate electrode 110. After the gate electrode 110 is formed, impurities are ion implanted into the first semiconductor substrate 100 on both sides of the gate electrode 110 to form the source / drain region 112. Accordingly, the transistors are completed on the first semiconductor substrate 100.

Subsequently, referring to FIG. 4, after the transistors are formed on the first semiconductor substrate 100, an insulating material having excellent step coverage is deposited to form the first interlayer insulating layer 120.

In the first interlayer insulating layer 120, contacts 122 electrically connected to lower transistors are formed. The contacts 122 selectively anisotropically etch the first interlayer insulating film 120 to form a contact hole exposing the source / drain region 112 or the gate electrode 110, and then filling the conductive material in the contact hole. Can be formed.

Thereafter, capacitors 124 and 126 and wirings 132 for storing data in the memory device are formed on the first interlayer insulating film 120. At this time, the capacitors 124 and 126 are stacked. It may be formed in various forms such as a cylinder type, etc. In an embodiment of the present invention, the cylindrical capacitors 124 and 126 are formed as an example.

The manufacturing method of the cylindrical capacitor will be briefly described. A sacrificial film (not shown) for a mold is formed on the first interlayer insulating film 120, the conductive film for the lower electrode is deposited on the sidewalls and the upper part of the mold, and then gap filling is performed. An insulating film (not shown) having good gap filling properties is deposited. Thereafter, the mold is planarized until the sacrificial film (not shown) is exposed, and the insulating film and the sacrificial film for the mold are removed to form the lower electrode 124 in the form of a cylinder. A dielectric film (not shown) and a conductive film for the upper electrode are deposited on the surface of the lower electrode 124 and then patterned to complete the capacitor.

After the capacitors 124 and 126 are formed, an insulating film made of oxide is deposited on the entire surface of the resultant. The planarization process such as chemical mechanical polishing or etch back is performed to form the second interlayer insulating layer 130.

After the second interlayer insulating film 130 is formed, the second interlayer insulating film 130 is patterned so as to be electrically connected to the capacitors 124 and 126 or the wiring layers 132 in the second interlayer insulating film 130. Form contacts. The interconnection layers 132 connected to the contacts are formed on the second interlayer insulating layer 130.

As such, when forming the contact and interconnect layers 132, a refractory metal material is used to reduce the thermal effects of subsequent processes. In other words, the contact and wiring layers 132 may include, for example, tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta) titanium nitride (TiN), tantalum nitride (TaN), and zirconium nitride (ZrN). , Tungsten nitride film (TiN), and an alloy made of a combination thereof.

Next, referring to FIG. 5, the third interlayer insulating layer 140 finally covering the cell elements of the semiconductor memory device formed on the first semiconductor substrate 100 is formed and planarized.

As such, the interlayer insulating films 120, 130, and 140 are formed on the first semiconductor substrate 100 over the multilayer. For example, as the interlayer insulating films 120, 130, and 140, a borosilicate glass (BSG) film, PhosphoSilicate Glass (PSG) film, BoroPhosphoSilicate Glass (BPSG) film, USG (Undoped Silicate Glass) film, TEOS (TetraEthlyOrthoSilicate Glass) film, O3-TEOS film or PE (Plasma Enhanced) -TEOS film.

Meanwhile, after forming the third interlayer insulating layer 140 positioned on the top layer on the first semiconductor substrate 100, the second semiconductor substrate 200 for forming the logic elements 20 is bonded to each other. Form layer 150.

Here, as the bonding layer 150, for example, various curable adhesives such as photo-setting adhesives such as reaction curable adhesives, thermosetting adhesives, ultraviolet curable adhesives, and anaerobic curable adhesives (anaerobe adhesives) may be used. It is available. The bonding layer 150 may be made of, for example, metal (Ti, TiN, Al), epoxy, acrylate, silicon, or the like, and may be formed of titanium (Ti) having excellent stability even at high temperature. have.

The bonding layer 150 may increase the bonding strength when the second semiconductor substrate 200 is adhered to the upper portion, and may serve to reduce fine defects that may occur during bonding.

Next, referring to FIG. 6, the second semiconductor substrate 200 is adhered to the bonding layer 150.

In more detail, first, the single crystal semiconductor substrate 203 including the impurity layer 200 doped with impurities uniformly to a predetermined depth is prepared. The impurity layer 200 may be formed by ion implanting impurities into the single crystal semiconductor substrate 203 or by adding impurities during the epitaxial layer growth process for forming the single crystal semiconductor substrate 203.

A separation layer 201 is formed in contact with the impurity layer 200 within a predetermined depth of the single crystal semiconductor substrate 203.

In the present invention, the separation layer 201 is a deformation caused by a difference between the crystal lattice (for example, Si-Ge) of a bubble layer (Porous) having fine pores, an insulating film such as an oxide film or a nitride film, an organic adhesive layer, or a substrate. It refers to a layer (Strained Layer).

Conventional representative techniques for forming the separation layer 201 is a method of separating the wafer by ion implantation (exfoliating implant) such as hydrogen (Hydrogen), such a conventional method is excessively used ion implantation In this case, the lattice structure of the impurity layer 200 may be destroyed. In addition, in order to recover the fractured lattice structure, a heat treatment process is required for a certain time in a very high temperature environment, and the heat treatment process in such a very high temperature environment causes severe changes in the cell elements located below.

Therefore, the separation layer 201 in the present invention is not formed by the ion implantation method using the above-mentioned vaporizable gas, but is a bubble layer (Porous) in which the fine pores are formed as described above, or an oxide film or a nitride film. It may be limited to an insulating layer, an organic adhesive layer, or a strained layer resulting from a difference (eg, Si-Ge) of the crystal lattice of the substrate.

The separation layer 201 prevents the impurity layer 200 from being removed when the second semiconductor substrate 200 is attached to the bonding layer 150 and then the region of the single crystal semiconductor substrate 203 is removed. can do. In addition, the isolation layer 201 serves to allow the single crystal semiconductor substrate 203 to be separated accurately and easily, leaving only the impurity layer 200.

Thereafter, the surface of the impurity layer 200 faces the bonding layer 150 to bond the single crystal semiconductor substrate 203. After the single crystal semiconductor substrate 203 is bonded onto the bonding layer 150, heat treatment may be performed while applying a constant pressure to increase the bonding strength.

As such, when the single crystal semiconductor substrate 203 including the impurity layer 200 is adhered to the first semiconductor substrate 100 on which the cell devices 10 are formed, other semiconductor devices may be formed on the single crystal semiconductor substrate 203. Since it is not formed, it is not required to exactly align the single crystal semiconductor substrate 203 on the bonding layer 150.

After the impurity layer 200 of the single crystal semiconductor substrate 203 is completely bonded, all portions other than the impurity layer 200 are removed. That is, the second semiconductor substrate 200 corresponds to a semiconductor substrate doped with impurities.

In more detail, a grinding or polishing process is performed from the top surface of the bonded single crystal semiconductor substrate 203 until the separation layer 201 is exposed. After the separation layer 201 is exposed, the impurity layer 200 is exposed by performing an anisotropic or isotropic etching process. Exposing the impurity layer 200 may be performed by selective etching of the semiconductor substrate since the impurity concentration gradients of the impurity layer 200 and the separation layer 201 are different in the semiconductor substrate. Alternatively, a physical impact may be applied to the separation layer 201 to cause cracks along the separation layer 201 where the crystal lattice is weak to separate the single crystal semiconductor substrate 203 and the impurity layer 200.

Meanwhile, the single crystal semiconductor substrate 203 may be a medium such as a glass wafer in some cases. For example, when the impurity layer is provided, it may be provided to the glass wafer and again to another semiconductor substrate.

As such, by removing a portion of the single crystal semiconductor substrate 203, the second semiconductor substrate 200 having a thickness of about 0.1 μm to 10 μm may be obtained.

Accordingly, as shown in FIG. 7, the second semiconductor substrate 200 including the impurity layer 200 which is completely bonded on the bonding layer 150 and has a uniform upper surface may be obtained. Accordingly, the logic elements 20 of the semiconductor device may be formed on the second semiconductor substrate 200.

Subsequently, referring to FIG. 8, an insulating film 202 is formed in a predetermined region of the bonded second semiconductor substrate 200. That is, a portion of the second semiconductor substrate 200 and a portion of the bonding layer 150 positioned on the wiring layer 132 of the cell elements 10 positioned below the second semiconductor substrate 200 are removed.

An insulating material is embedded in the removed region to form a continuous insulating film 202 with the insulating material covering the cell elements 10.

Next, referring to FIG. 9, an isolation region 204 is formed in the second semiconductor substrate 200 except for the region where the insulating layer 202 is formed, thereby defining an active region. The device isolation layer 204 may be formed by performing an STI process as described above.

Then, transistors forming the logic elements 20 of the semiconductor memory device are formed on the second semiconductor substrate 200. Transistors may be formed by going through the manufacturing process of conventional NMOS and / or PMOS transistors. Accordingly, gate electrodes 210 may be formed on the second semiconductor substrate 200, and source / drain regions 212 may be formed in the second semiconductor substrate 200 on both sides of the gate electrodes 210. .

That is, in the process of manufacturing the semiconductor device according to the embodiment of the present invention, in the process of forming the transistors on the second semiconductor substrate 200 as described above, for example, when a process such as ion implantation is performed. Even if the process is performed at a high temperature, since the wiring layers 132 disposed under the second semiconductor substrate 200 are made of refractory metal, the influence on the lower cell elements 10 can be minimized. It will be able to provide.

Thereafter, as shown in FIG. 10, a fourth interlayer insulating layer 220 covering the transistors is formed on the second semiconductor substrate 200.

The fourth interlayer insulating film 220 is the same as the first to third interlayer insulating films 120, 130, and 140 formed on the first semiconductor substrate 100, a BSG (Borosilicate Glass) film, and a PSG (PhosphoSilicate Glass) film. , Silicon oxide such as a BPSG (BoroPhosphoSilicate Glass) film, an Undoped Silicate Glass (USG) film, a TetraEthlyOrthoSilicate Glass (TEOS) film, an O3-TEOS film, or a PLA (Plasma Enhanced) -TEOS film.

Then, an anisotropic etching process is performed over the fourth interlayer insulating film 220, the insulating film 202, and the third interlayer insulating film 140 to expose the contact hole exposing the wiring layer 132 of the lower cell element 10. Form. Subsequently, a conductive material is filled in the contact hole to form a connection wiring 221 electrically connecting the lower cell element 20 and the upper logic elements 20. Here, the connection wiring 221 is formed of a refractory metal material having a small change in characteristics even at a high temperature. That is, it may be formed of a material such as tungsten (W), titanium (Ti), molybdenum (Mo) and tantalum (Ta).

At the same time, in the fourth interlayer insulating film 220 on the second semiconductor substrate 200 where the insulating film 202 is not formed, contacts electrically connected to transistors formed on the second semiconductor substrate 200 ( 22).

After the contacts 222 and the connection wirings 221 are formed in the fourth interlayer insulating film 220, the contacts 222 and the connection wiring (on the fourth and fifth interlayer insulating films 220 and 230) are formed. Wiring layers 232 selectively connected to 221 are formed.

Accordingly, logic devices 20 capable of controlling data stored in the lower cell devices 10 may be completed. After completing the logic devices 20, an insulating material is finally applied to form the sixth interlayer insulating film 240.

As such, when forming a DRAM device including the cell elements 10 and the logic elements 20, the cell elements 10 and the logic elements 20 are vertically stacked without being disposed in a two-dimensional plane. By arranging in three-dimensional structure, a semiconductor device of fine size can be obtained. As a result, the yield of the semiconductor device obtained from one semiconductor substrate can be improved.

When the logic elements 20 are formed on the cell elements 10, the wiring layers 132 and the connection lines 221 of the cell element 10 are made of a refractory metal material, and thus, high temperature heat. When the logic devices 20 are formed by the process, the reliability of the lower cell devices 10 may be prevented from being lowered due to the influence of high temperature.

In addition, by bonding the second semiconductor substrate 200 on the cell elements 10 without the semiconductor elements being formed on the second semiconductor substrate 200, it is not necessary to precisely align the substrate. Therefore, the manufacturing process of the semiconductor device can be simplified.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention.

3 to 10 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

<Description of the code | symbol about the principal part of drawing>

10: memory cell element 20: memory logic element

100: first semiconductor substrate 110: first fine electronic device

120 and 220: bonding layer 200: second semiconductor substrate

205 and 305: Connection wiring 210: Second fine electronic element

300: third semiconductor substrate 310: third fine electronic device

Claims (34)

A first semiconductor substrate; A first insulating layer formed on the first semiconductor substrate and including a first microelectronic element having a wiring layer made of a refractory metal material; A second semiconductor substrate bonded onto the first insulating layer; And A second insulating layer formed on the second semiconductor substrate and including a second microelectronic device electrically connected to the first microelectronic device, The first microelectronic device is a memory cell device that stores data, and the second microelectronic device is a logic device that controls the memory cell device. The method of claim 1, And the memory cell element is a volatile memory cell element or a nonvolatile memory cell element. The method of claim 1, The logic device includes a redundancy circuit that recovers a defect of the memory cell device. The method of claim 1, And a first connection wire penetrating the second semiconductor substrate to electrically connect the first microelectronic element and the second microelectronic element and made of a refractory metal material. The method of claim 4, wherein The refractory metal materials include tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (TiN) and these Semiconductor device made of any one of the alloy consisting of a combination of. The method of claim 1, The second microelectronic device includes a wiring layer formed of a metal material or a refractory metal material. The method of claim 1, And a bonding layer interposed between the first insulating layer and the second semiconductor substrate. A first semiconductor substrate; A first insulating layer formed on the first semiconductor substrate and including a first microelectronic element having a wiring layer made of a refractory metal material; A second semiconductor substrate bonded onto the first insulating layer; A second insulating layer formed on the second semiconductor substrate and electrically connected to the first microelectronic device and including a second microelectronic device having a wiring layer made of a refractory metal material; A third semiconductor substrate bonded on the second insulating layer; And Including a third microelectronic device formed on the third semiconductor substrate, The first microelectronic device and the second microelectronic device are memory cell devices for storing data, and the third microelectronic device are logic devices for controlling the memory cell device. The method of claim 8, And the memory cell element is a volatile memory cell element or a nonvolatile memory cell element. The method of claim 8, And the logic device comprises a redundancy circuit to recover a defect of the memory cell device. The method of claim 8, A first connection wire penetrating the second semiconductor substrate to electrically connect the first microelectronic element and the second microelectronic element and be made of a refractory metal material; And And a second connection wiring penetrating through the third semiconductor substrate to electrically connect the second microelectronic element and the third microelectronic element and made of a refractory metal material. The method of claim 11, The refractory metal materials include tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), zirconium nitride (ZrN), tungsten nitride (TiN) and these Semiconductor device made of any one of the alloy consisting of a combination of. The method of claim 8, The third microelectronic device includes a wiring layer formed of a metal material or a refractory metal material. The method of claim 8, And a bonding layer interposed between the first insulating layer and the second semiconductor substrate and between the second insulating layer and the third semiconductor substrate. Providing a first semiconductor substrate, Forming first fine electronic elements having a wiring layer made of a refractory metal material on the first semiconductor substrate, Stacked in multiple layers to form a first insulating layer covering the first microelectronic elements, Bonding a second semiconductor substrate onto the first insulating layer, Forming second microelectronic devices on the second semiconductor substrate, Forming a second insulating layer laminated on the multilayer to cover the second fine electronic devices, Forming memory cell elements for storing data in the first microelectronic element, and forming logic elements for controlling the memory cell element with the second microelectronic element. The method of claim 15, The forming of the memory cell elements may form a volatile or nonvolatile memory element. The method of claim 15, Forming the logic element comprises forming a redundancy circuit that recovers a defect of the memory cell. The method of claim 15, Bonding the second semiconductor substrate, and then penetrating the second semiconductor substrate to electrically connect the first microelectronic element and the second microelectronic element, and to form a first connection wiring with a refractory metal material. The manufacturing method of the semiconductor device which further contains. The method of claim 18, The refractory metal material used to form the wiring layer or the first connection wiring includes tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride film (TiN), tantalum nitride film (TaN), A method of manufacturing a semiconductor device comprising any one of an alloy consisting of a zirconium nitride film, a tungsten nitride film (TiN), and a combination thereof. The method of claim 15, Forming the second fine electronic device includes forming a wiring layer formed of a metal material or a refractory metal material. The method of claim 15, And forming a bonding layer on the first insulating layer before bonding the second semiconductor substrate. The method of claim 15, Bonding the second semiconductor substrate provides a single crystal semiconductor substrate, Forming an impurity layer doped with impurities uniformly from an upper surface of the single crystal substrate to a predetermined depth, In the single crystal semiconductor substrate, a separation layer is formed at a depth in contact with the impurity layer, Bonding the single crystal semiconductor substrate to the upper surface of the first insulating layer and the impurity layer; Removing a portion of the single crystal semiconductor substrate until the impurity layer surface is exposed. The method of claim 22, And the separation layer prevents the impurity layer from being removed when a portion of the single crystal semiconductor substrate is removed. The method of claim 15, After bonding the second semiconductor substrate, a portion of the second semiconductor substrate positioned on the wiring layer of the first microelectronic device is removed; And embedding an insulating material in a portion of the removed second semiconductor substrate to form an insulating film. The method of claim 24, And forming the insulating film, and then penetrating the insulating film to electrically connect the first microelectronic element and the second microelectronic element, and to form a first connection line made of a refractory metal material. Manufacturing method. Providing a first semiconductor substrate, Forming first fine electronic elements having a wiring layer made of a refractory metal material on the first semiconductor substrate, Stacked in multiple layers to form a first insulating layer covering the first microelectronic elements, Bonding a second semiconductor substrate onto the first insulating layer, Forming second microelectronic elements having a wiring layer made of a refractory metal material on the second semiconductor substrate, Stacked in multiple layers to form a second insulating layer covering the second microelectronic elements, Bonding a third semiconductor substrate onto the second insulating layer, Forming a third microelectronic device electrically connected to the second microelectronic device on the third semiconductor substrate, Forming a third insulating layer stacked in multiple layers to cover the third fine electronic devices; Forming memory cell elements for storing data in the first microelectronic element and the second microelectronic element, and forming logic elements for controlling the memory cell element with the third microelectronic element. The method of claim 26, The forming of the memory cell elements may form a volatile or nonvolatile memory element. The method of claim 26, Forming the logic element comprises forming a redundancy circuit that recovers a defect of the memory cell. The method of claim 26, Bonding the second semiconductor substrate, and penetrating the second semiconductor substrate to electrically connect the first microelectronic element and the second microelectronic element, and to form a first connection wiring using a refractory metal material; Bonding the third semiconductor substrate and then penetrating the third semiconductor substrate to electrically connect the second microelectronic element and the third microelectronic element and form a second connection wiring made of a refractory metal material. The manufacturing method of the semiconductor device which further contains. The method of claim 29, The refractory metal material used to form the wiring layer, the first connection wiring or the second connection wiring includes tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride film (TiN), A method of manufacturing a semiconductor device comprising any one of an alloy consisting of a tantalum nitride film (TaN), a zirconium nitride film, a tungsten nitride film (TiN), and a combination thereof. The method of claim 26, Forming the third microelectronic element includes forming a wiring layer formed of a metal material or a refractory metal material. The method of claim 26, And forming a bonding layer on the second insulating layer before bonding the third semiconductor substrate. The method of claim 26, Bonding the third semiconductor substrate provides a single crystal semiconductor substrate, Forming an impurity layer doped with impurities uniformly from an upper surface of the single crystal substrate to a predetermined depth, In the single crystal semiconductor substrate, a separation layer is formed at a depth in contact with the impurity layer, Bonding the single crystal semiconductor substrate to the upper surface of the second insulating layer and the impurity layer; Removing a portion of the single crystal semiconductor substrate until the impurity layer surface is exposed. The method of claim 33, wherein And the separation layer prevents the impurity layer from being removed when a portion of the single crystal semiconductor substrate is removed.

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