KR101022580B1 - Mass storage semiconductor memory device and method for fabricating the same - Google Patents

Abstract

A large capacity semiconductor memory device having a three-dimensional structure and a method of manufacturing the same are provided. The semiconductor memory device includes a plurality of logic elements formed on a semiconductor substrate, a first interlayer insulating layer covering the logic elements, a bonding layer formed on the first interlayer insulating layer, and a plurality of memory elements stacked on the bonding layer and connected to the logic elements. For example, the semiconductor device may include an input / output metal pad formed on the second interlayer insulating layer covering the memory elements and the second interlayer insulating layer and electrically connected to the logic elements.

3d structure, junction, SSD

Description

Mass storage semiconductor memory device and method for fabricating the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor large capacity semiconductor memory device and a manufacturing method thereof, and more particularly, to a large capacity semiconductor memory device having a three-dimensional structure capable of high capacity and high integration and a manufacturing method thereof.

Magnetic disks have traditionally been used as data storage devices in electronic systems such as computer systems. However, with the development of semiconductor technology, solid state disks using non-volatile memory of EEPROM-based (eg, NAND-type EEPROM or NOR-type EEPROM) as data storage devices instead of magnetic disks in computer systems and portable devices. State Disk (SSD) is increasingly being used.

Since the SSD does not include a mechanical driving device such as a motor which is essentially used in a hard disk drive (HDD), the SSD hardly generates heat and noise during operation. SSDs are also preferred as data storage devices because of their fast access rate, high density, and stability against external shocks. In addition, the data transfer speed of SSD is considerably faster than that of HDD.

Accordingly, an object of the present invention is to provide a large-capacity semiconductor memory device having a three-dimensional structure capable of high capacity and high integration.

Another object of the present invention is to provide a method of manufacturing a large-capacity semiconductor memory device having a three-dimensional structure capable of high capacity and high integration.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

In accordance with an aspect of the present invention, a large capacity semiconductor memory device includes a plurality of logic elements formed on a semiconductor substrate, a first interlayer insulating layer covering the logic elements, a bonding layer formed on the first interlayer insulating layer, and a junction A plurality of memory elements stacked on the layer and connected to the logic elements, a second interlayer insulating layer covering the memory elements and a second interlayer insulating layer, the input and output metal pads electrically connected to the logic elements, and including logic The elements may correspond to input / output control circuits that control input / output of data through the input / output metal pads, each of the memory devices, and control a plurality of memory device control circuits and memory input / output control circuits and memory device control circuits to control the memory devices. It includes a central control circuit.

According to another aspect of the present invention, there is provided a method of manufacturing a large-capacity semiconductor memory device, including: providing a first semiconductor substrate, forming a logic element on the first semiconductor substrate, and covering the logic elements; Forming a first interlayer insulating film, forming a bonding layer on the first interlayer insulating film, stacking a plurality of memory elements connected with logic elements on the bonding layer, and forming a second interlayer insulating film covering the memory elements, Forming an input / output metal pad electrically connected to the logic elements on the two interlayer insulating layers, wherein forming the logic elements may include an input / output control circuit and a memory element for controlling input / output of data through the input / output metal pad, respectively. A plurality of memory element control circuits and input / output control circuits and memory element control circuits that control the memory elements. It includes forming the central control circuit for controlling.

Specific details of other embodiments are included in the detailed description and the drawings.

According to the large-capacity semiconductor memory device of the present invention and a manufacturing method thereof, the main memory, the buffer memory, and the control circuits are arranged in a three-dimensional structure in one semiconductor chip, whereby the integration density and storage capacity of the semiconductor memory device can be further improved. .

Advantages and features of the present invention, and methods for achieving them will be apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the dimensions of the substrates, layers (films), regions, recesses, pads, patterns or structures are shown to be larger than actual for clarity of the invention. In the present invention, each layer (film), region, pad, recess, pattern or structure is formed on the substrate, each layer (film), region, pad or patterns "on", "top" or "bottom". When referred to as meaning that each layer (film), region, pad, recess, pattern or structure is formed directly over or below the substrate, each layer (film), region, pad or patterns, or Other layers (films), other regions, different pads, different patterns or other structures may additionally be formed on the substrate.

1, 2A and 2B, a large capacity semiconductor memory device according to a first embodiment of the present invention will be described in detail. 1 is a cross-sectional view of a large capacity semiconductor memory device according to a first embodiment of the present invention. 2A and 2B are cross-sectional views of semiconductor devices included in a large-capacity semiconductor memory device according to a first embodiment of the present invention.

The large-capacity semiconductor memory device according to the first embodiment of the present invention includes a dynamic random access memory (DRAM), ferroelectrics random access memory (FRAM), a static random access memory (SRAM), a phase-change random access memory (PRAM), and an MRAM. It is a solid state drive (SSD), a memory-based data storage device such as magnetic random access memory (RRAM), resistive random access memory (RRAM), and flash memory.

Referring to FIG. 1, logic devices 10 are disposed on a semiconductor substrate 100, and memory devices 20, 30, and 40 are disposed on the logic devices 10. The memory devices 20, 30, and 40 disposed on the logic devices 10 include a buffer memory device 20 and main memory devices 30 and 40. As such, the logic elements 10 and the memory elements 20, 30, and 40 formed on the semiconductor substrate 100 constitute one chip.

In more detail, the logic elements 10 on the semiconductor substrate 100 may include NMOS and PMOS transistors 110, a wiring 122, a resistor (not shown), a diode (not shown), and the like. . The logic elements 10 control input / output of data, read, write, and delete operations of data. Specifically, the logic elements 10 include an input / output control circuit 10a, a central control circuit 10b, a buffer memory control circuit 10b, and a main memory control circuit 10d.

The input / output control circuit 10a controls the input and output of data from the outside, the central control circuit 10b controls the operation between the logic element 10 and the memory elements 20, 30, 40, and the entire storage device. Control the operation. The buffer memory control circuit 10b and the main memory control circuit 10d control the buffer memory element 20a and the main memory element 20b, respectively.

Such logic elements 10 may be formed over the first multilayer interlayer insulating layers 120, 130, and 140. The bonding layer 150 is positioned on the first interlayer insulating layer 140 of the uppermost layer covering the logic elements 10.

The bonding layer 150 is for bonding a semiconductor substrate (see FIGS. 2A and 2B) to form semiconductor memory devices on the interlayer insulating layer 140. For example, the bonding layer 150 may use various curable adhesives such as photo-setting adhesives such as reaction curable adhesives, thermosetting adhesives, and ultraviolet curable adhesives, and anaerobic adhesives. Or metal-based Ti, TiN, Al, etc.), epoxy-based, acrylate-based, silicon-based, and the like.

In this case, when the bonding layer 150 is formed of a metal material, the bonding layer 150 may be operated as a wiring. The bonding layer 150 may be locally removed from predetermined regions in which the contacts 222 connecting the logic element 10 and the buffer memory element 20 are formed.

The buffer memory device 20a may be disposed on the bonding layer 150. The buffer memory device 20a is provided on a layer separate from the main memory devices 20b in order to efficiently write and read data in the main memory device 20b. The buffer memory element 20a is connected to the central control circuit 10b and the buffer memory control circuit 10c disposed below, so that its operation can be controlled. The buffer memory device 20 is covered by a plurality of second interlayer insulating layers 220, 230, and 240, and a bonding layer 250 is formed on the second interlayer insulating layer 240 of the uppermost layer.

The main memory device 20a is stacked on the buffer memory device 20 through the bonding layer 250. The main memory device 20b is connected to the lower central control circuit 10b and the main memory control circuit 10d through the contacts 222, 322, and 422, so that the operation thereof may be controlled. In addition, the main memory device 20b may include first and second main memory devices 30 and 40 that are sequentially stacked.

The first main memory device 30 is covered by the third interlayer insulating films 320, 330, and 340, and the second main memory device 40 is formed through the bonding layer 350 on the third interlayer insulating film 340. Are stacked.

In an embodiment of the present invention, the main memory devices 30 and 40 are described as being stacked over two layers. However, the main memory devices 30 and 40 may be stacked over two or more layers. That is, by stacking the main memory elements 30 and 40 over a plurality of layers, the memory capacity can be increased without increasing the area of the large-capacity semiconductor memory device.

As such, the input / output metal pad 500 may be disposed on the uppermost layers of the logic element 10, the buffer memory element 20a, and the main memory element 20b stacked on the semiconductor substrate 100. That is, data may be output and input through the input / output metal pad 500. The input / output metal pad 500 is input / output through the contacts 222, 322, and 422 penetrating through the first to fourth interlayer insulating layers 120 to 140, 220 to 240, 320 to 340, and 420 to 430. It is connected with the control circuit 10a.

Meanwhile, the buffer memory device 20a and the main memory device 20b disposed on the logic device 10 are disposed on different layers, and the order in which they are arranged is not limited to the embodiments of the present invention.

In addition, the buffer memory device 20a and the main memory device 20b stacked on the logic device 10 may include dynamic random access memory (DRAM), ferroelectrics random access memory (FRAM), static random access memory (SRAM), It may be composed of a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), a resistive random access memory (RRAM) and / or a flash memory. That is, the buffer and main memory elements 20a and 20b may be composed of switching elements (see FIGS. 2A and 2B) and data storage elements (not shown). In addition, the buffer and main memory elements 20a and 20b may be formed of a charge storage layer and control gates.

The structures of the buffer memory element 20a and the main memory element 20b included in the first embodiment of the present invention will be described in more detail with reference to FIGS. 2A and 2B.

Referring to FIG. 2A, the buffer memory device 20a and the main memory device 20b may include a transistor 210 having a vertical channel and a data storage device 224.

In more detail, a plurality of semiconductor patterns SP having a structure in which different conductive impurity layers 202, 204, and 206 are alternately stacked on the junction layer 150 are disposed. In the semiconductor patterns SP, the first conductive semiconductor patterns 202 and 206 and the second conductive semiconductor pattern 204 are alternately stacked. Then, the first conductivity type semiconductor patterns 202 and 206 are disposed on the lowermost layer and the uppermost layer. In the first embodiment of the present invention, when the vertical channel transistors 210, 310, and 410 are NMOS transistors, the first conductivity type is n type and the second conductivity type is p type. When the vertical channel transistors 210, 310, and 410 are PMOS transistors, the first conductivity type is p-type and the second conductivity type is n-type. In addition, the first conductive semiconductor layer patterns 202 and 206 positioned at the lowermost layer and the uppermost layer correspond to source / drain regions of the transistors, and the second conductive layer between the first conductive semiconductor layer patterns 202 and 206. The type semiconductor layer pattern 204 corresponds to a channel region.

In addition, each semiconductor pattern SP may have a pillar shape, and a gate electrode 208 having a spacer shape is formed at the center of the sidewall of the semiconductor pattern SP. A gate insulating film (not shown) is interposed between the semiconductor pattern SP and the gate electrode 208.

The gate electrode 208 formed around the semiconductor pattern SP may contact the gate electrodes 208 formed around the adjacent semiconductor patterns SP. That is, the semiconductor patterns SP are spaced apart from each other so that the gate electrodes 208 formed on the sidewalls may contact each other. Accordingly, one gate electrode line may be formed by the gate electrodes 208 formed around the plurality of columnar semiconductor patterns SP.

In addition, contact plugs and wires 224 are connected to upper surfaces of the columnar semiconductor patterns SP, respectively. The wiring 224 may be a data storage electrode of the data storage element.

Referring to FIG. 2B, the buffer memory device 20a and the main memory device 20b may include transistors 210, 310, and 410 having a horizontal channel and a data storage device 224.

In more detail, the bonded single crystal semiconductor substrate 200 is positioned on the bonding layer 150. In the junction semiconductor substrate 200, an active region is defined by device isolation regions 203, and transistors having horizontal channels are formed on the active region. Here, the device isolation layers 203 may be formed through the junction semiconductor substrate 200. The transistors include gate patterns 208 formed on the junction semiconductor substrate 200 and source / drain regions 202 formed in the junction semiconductor substrate 200 on both sides of the gate patterns 208. In this case, the source / drain regions 202 may be formed by implanting impurities into the junction semiconductor substrate 200 at a predetermined depth or by implanting impurities to the bottom of the junction semiconductor substrate 200. In addition, on the junction semiconductor substrate 200, transistors 210, 310, and 410 adjacent to each other may share the source / drain region 202 between the gate patterns 210.

In addition, contact plugs and wires 224 may be connected to the source / drain regions, and the wires 224 may be data storage electrodes of the data storage device. In detail, when the buffer or main memory devices 20a and 20b are DRAM devices, capacitors (not shown) are connected to the transistors 210, 310, and 410 as data storage devices. In addition, when the buffer or main memory devices 20a and 20b are PRAM devices, a phase change material film is connected to the transistors 210, 310, and 410 as data storage devices. In addition, when the buffer or main memory elements 20a and 20b are FRAM elements, a ferroelectric material film is connected as a data storage element.

A method of manufacturing a large capacity semiconductor memory device according to a first embodiment of the present invention will be described in detail with reference to FIGS. 1 and 3 to 7.

Referring to FIG. 3, logic elements including an input / output control circuit 10a, a central control circuit 10b, a buffer memory control circuit 10b, and a main memory control circuit 10d on a first semiconductor substrate 100 may be used. To form (10). That is, on the first semiconductor substrate 100, NMOS and / or PMOS transistors 110 are formed with resistors (not shown), diodes (not shown), and wirings 122 to form logic elements.

In more detail, device isolation layers (not shown) are formed in the first semiconductor substrate 100 to define an active region. Here, the first semiconductor substrate 100 may be bulk silicon, bulk silicon-germanium, or a semiconductor substrate on which a silicon or silicon-germanium epi layer is formed. In addition, the first semiconductor substrate 100 may include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) ), Doped and undoped semiconductors, silicon epitaxial layers supported by the underlying semiconductor, and other semiconductor structures well known to those skilled in the art.

Gate electrodes are formed on the first semiconductor substrate 100 and source / drain regions are formed by ion implanting impurities into the first semiconductor substrate 100 on both sides of the gate electrode 110. Accordingly, the transistors 110 may be formed on the first semiconductor substrate 100.

The first interlayer insulating layers 120 to 140 are formed on the transistors 110 by depositing an insulating material having excellent step coverage. In this case, contacts and wires 122, resistors (not shown), and diodes (not shown) may be buried in the first interlayer insulating layers 120 to 140.

In this case, the contacts and wires 122 embedded in the first interlayer insulating layers 120 to 140 may be formed of a refractory metal material having low resistance, low stress, excellent step coverage, and excellent thermal expansion coefficient. Can be. Accordingly, the formation of subsequent memory elements is less affected by the high temperature process. Accordingly, electrical characteristics and reliability of the logic elements 10 may be maintained. Examples of such refractory metal materials include tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), titanium nitride film (TiN), tantalum nitride film (TaN), zirconium nitride film, and tungsten nitride film (TiN). And alloys thereof.

Subsequently, a bonding layer 150 is formed on the first interlayer insulating layer 140 positioned on the uppermost layer to bond the semiconductor substrate for forming the memory devices. Specifically, for example, the bonding layer 150 may use various curable adhesives, such as photo-setting adhesives such as reaction curable adhesives, thermosetting adhesives, and ultraviolet curable adhesives, and anaerobic adhesives. Can be. Or metal-based Ti, TiN, Al, etc.), epoxy-based, acrylate-based, silicon-based, and the like.

Here, when the bonding layer 150 is formed of a metal material, the metal material is a material that melts at a lower temperature than the conductive materials forming the contacts and the wirings 122 embedded in the first interlayer insulating films 120 to 140. Can be formed. In addition, the bonding layer 150 is formed of a material that can be reflowed at a low temperature during the planarization process in order to prevent voids that may be formed due to fine non-uniformity of the surface when bonding to the semiconductor substrate. That is, the bonding layer 150 may increase the bonding strength when the semiconductor substrate is adhered to the upper portion, and may serve to reduce fine defects that may occur during bonding.

Referring to FIG. 4, a second semiconductor substrate 209 is prepared on the bonding layer 150. In more detail, the second semiconductor substrate 209 is a single crystal semiconductor substrate, and may include one impurity layer 200 from a surface to a predetermined depth or may include a plurality of impurity layers 200. Here, the plurality of impurity layers 200 may be formed by ion implanting impurities into the single crystal semiconductor substrate 209 or by adding impurities during the epitaxial growth process for forming the single crystal semiconductor substrate.

In this case, one impurity layer 200 included in the second semiconductor substrate 209 may be a single crystal semiconductor impurity layer 201 doped with n-type or p-type impurities. In addition, the plurality of impurity layers 200 included in the second semiconductor substrate 209 may be formed by alternately implanting impurities so that the n-type impurity layer and the p-type impurity layer may be alternately positioned.

In addition, the second semiconductor substrate 200 including the impurity layers 200 includes a separation layer 201 at an interface between the impurity layer 200 and the single crystal semiconductor substrate 209. The separation layer 201 is a strained layer that is formed by a difference between (eg, Si-Ge) a microporous bubble layer (Porous), an insulating film such as an oxide film or a nitride film, an organic adhesive layer, or a crystal lattice of a substrate. Say In addition, the separation layer 201 may be formed by ion implanting a vaporizable gas such as hydrogen (Hydrogen). The separation layer 201 may prevent the removal of the impurity layers 200 when the single crystal semiconductor substrate region is removed after the second semiconductor substrate 200 is bonded onto the bonding layer 150. Can be. In addition, the separation layer 201 leaves only the impurity layers 200 and serves to accurately and easily separate the single crystal semiconductor substrate.

Thereafter, the second semiconductor substrate 200 is bonded on the bonding layer 150 such that the surface of the impurity layer 200 faces the bonding layer 150. After the second semiconductor substrate 200 is bonded onto the bonding layer 150, the second semiconductor substrate 200 may be heat treated while applying a predetermined pressure to increase the bonding strength.

As such, when the second semiconductor substrate 209 including the impurity layers 200 is adhered to the bonding layer 150, other semiconductor elements are not formed on the second semiconductor substrate 209. It is not required to accurately align the two semiconductor substrates 209 on the bonding layer 150.

After the second semiconductor substrate 209 is completely bonded onto the bonding layer 150, all portions other than the impurity layer 200 are removed. Accordingly, the impurity layer 200 may be formed on the bonding layer 150 made of a metal material.

In more detail, the single crystal semiconductor region is ground or polished until the separation layer 201 is exposed in the bonded second semiconductor substrate 200. After the separation layer 201 is exposed, an anisotropic or isotropic etching process is performed to expose the surface of the impurity layer 200.

Exposing the impurity layer 200 may be performed by selective etching of the semiconductor substrate since the impurity concentration gradients of the impurity layers 200 and the separation layer 201 are different in the second semiconductor substrate 209. Alternatively, a physical impact may be applied to the separation layer 201 to cause cracks along the separation layer 201 where the crystal lattice is weak to separate the single crystal semiconductor region and the plurality of impurity layers 200.

Referring to FIG. 5, memory devices are formed on the bonding layer 150 using a single crystal semiconductor impurity layer formed through the bonding of a single crystal semiconductor substrate. The memory devices may be buffer memory devices or main memory devices. In the first embodiment of the present invention, the buffer memory device 20a is first formed on the logic devices 10. The memory devices 20a may be formed of DRAM, FRAM, SRAM, PRAM, MRAM, and / or flash memory. For example, the memory elements 20a may be composed of transistors and data storage elements having vertical or horizontal channels.

Forming the memory elements 20a shown in FIG. 5 is described in more detail with reference to FIGS. 2A and 2B.

That is, when a plurality of impurity layers are formed on the junction layer 150, the plurality of impurity layers are patterned to form pillar-shaped semiconductor patterns SP for forming transistors, as shown in FIG. 2A. . In more detail, the photolithography process may be performed on the plurality of semiconductor layers to form the semiconductor layer patterns SP. That is, an n / p / n type or a p / n / p type semiconductor pattern SP may be formed. The pillar-shaped semiconductor patterns SP may correspond to the channel region 204 and the source / drain regions 202 and 206 of the vertical transistor.

After forming the semiconductor patterns SP on the bonding layer 150, a gate electrode 208 having a spacer shape is formed on both sides of the impurity layer 204 located in the middle of the semiconductor patterns SP. . The gate electrode 208 in the form of a spacer may be formed by conformally forming a gate conductive film along a surface of a semiconductor pattern and then anisotropically etching. In this case, the gate electrode 208 is formed to contact the gate electrodes 208 formed on the sidewall of the adjacent semiconductor pattern SP.

Meanwhile, after the bonding layer 150 is formed of the single crystal semiconductor impurity layer, that is, the second semiconductor substrate 200, transistors having horizontal channels may be formed, as shown in FIG. 2B.

In detail, an isolation region 203 is formed in the bonded single crystal second semiconductor substrate 200 to define an active region. Then, the gate insulating film and the gate conductive film patterns are formed on the single crystal second semiconductor substrate 200 to form the gate electrodes. The source / drain regions 202 are formed by doping impurities into the second semiconductor substrate 200 at both sides of the gate electrodes. Here, a common source region 202 may be formed between adjacent gate electrodes.

Referring to FIG. 6, after forming the buffer memory devices 20a having the transistors 210 of the vertical or horizontal channel on the junction layer 150, a second interlayer insulating film 220 covering the memory devices is formed. Contacts and wires 224 connected to the buffer memory devices 20a are formed. Then, the contacts 222 connected to the logic elements 10 under the buffer memory elements 20a are formed. Specifically, contacts 222 connected to the input / output control circuit 10a, the buffer memory control circuit 10c, and the main memory control circuit 10d are formed. In this case, the contacts 222 may be formed of a refractory metal material. By forming the contacts 222, the buffer memory elements 20a are electrically connected to the lower buffer memory control circuit 10c.

Referring to FIG. 7, a bonding layer 250 is formed on a surface of the second interlayer insulating layers 220 to 240 of the uppermost layer covering the buffer memory devices 20a. Thereafter, a single crystal semiconductor substrate for forming main memory devices is bonded on the bonding layer 250. As described above with reference to FIGS. 4 to 5, a contact for forming main memory devices 20b using a single crystal semiconductor substrate and connecting the main memory devices 20b and the main memory control circuit 10d. Form the field 322.

Meanwhile, the main memory devices 20b may be stacked vertically over the multilayer through the bonding of the semiconductor substrate by repeating the above process.

After forming the memory devices 20b stacked vertically, referring to FIG. 1 again, the input / output metal pad 500 is formed on the uppermost layer of the semiconductor substrate 100. The input / output metal pad 500 is in contact with the contacts 222, 322, and 422 connected to the lower input / output control circuit 10a.

Hereinafter, a large capacity semiconductor memory device according to a second embodiment of the present invention will be described in detail with reference to FIG. 8. For the second embodiment, detailed description of technical features overlapping with the first embodiment of the present invention will be omitted, and differences from the first embodiment will be described in detail.

Referring to FIG. 8, in the large-capacity semiconductor memory device according to the second embodiment of the present invention, a first chip 1 and a second chip 2 are stacked through a junction, and through silicon vias 510 are formed. The first chip 1 and the second chip 2 are electrically connected to each other through. That is, the logic device 10 and the first and second chips 1 and 2 including the memory devices 20 and 30 on the logic device 10 are vertically stacked through the junction.

In more detail, the first chip 1 disposed below includes the logic devices 10 disposed on the semiconductor substrate 100 and the memory devices 20 and 30 on the logic devices 10. do.

The logic elements 10 control input / output of data, read, write, and delete operations of data. Specifically, the logic elements 10 include an input / output control circuit 10a, a central control circuit 10b, a buffer memory control circuit 10b, and a main memory control circuit 10d. Here, the input / output control circuit 10a may be provided in plural, and may be connected to the first chip 1 positioned below and the second chip 2 positioned above.

The buffer memory device 20a and the main memory device 30a are sequentially stacked on the logic devices 10. The buffer memory device 20a and the main memory device 30a may be sequentially stacked on the logic device 10 through the bonding layers 150 and 250. The bonding layers 150 and 250 may be formed of a conductive adhesive material to operate as a wiring. The bonding layers 150 and 250 may be locally removed from predetermined regions in which the contacts 222 connecting the logic element 10 and the memory elements 20a and 30a are formed.

The buffer memory element 20a is connected to the central control circuit 10b and the buffer memory control circuit 10c disposed below through the contact 222 so that its operation can be controlled. In addition, the main memory device 30a may be connected to the lower central control circuit 10b and the main memory control circuit 10d through the contacts 222 and 322 so that its operation may be controlled.

Meanwhile, the main memory device 30a on the buffer memory device 20a may be stacked over a plurality of layers through bonding. That is, other main memory elements (not shown) may be bonded on the main memory element 30a.

In addition, in the first chip 1, bonding pads 355 and 357 are formed on the uppermost third interlayer insulating layer 330 covering the main memory device 30a. The bonding pads 355 and 357 may be connected to the input / output control circuit 10a and the main memory control circuit 10e of the first chip 1 through contact plugs, respectively. In addition, the bonding pads 355 and 357 are bonded to the lower surface of the semiconductor substrate 100 of the second chip 2.

The second chip 2 may be substantially the same as the first chip 1 except for the input / output control circuit 10a. That is, the second chip 2 includes logic elements 10 and memory elements 20a and 30a formed in a three-dimensional structure on the semiconductor substrate 100.

Specifically, the logic elements 10 on the semiconductor substrate 100 in the second chip 2 include a central control circuit 10b and a main memory control circuit 10d. In addition, a plurality of memory devices 20a and 30a are stacked on the logic device 10. The memory devices 20 and 30 may be formed by stacking a plurality of main memory devices 20a and 30a. That is, unlike the first chip 1, the second chip 2 may be omitted from the buffer memory device. However, the second embodiment of the present invention is not limited thereto and may include a buffer memory element.

In addition, the second chip 2 penetrates through the semiconductor substrate 100 and the first to third interlayer insulating layers 120 to 140, 220 to 240, 320 to be in contact with the bonding pads 355 and 357. Silicon via 510. That is, the through silicon via 510 is electrically connected to the wiring 400 connected to the input / output control circuit 10a in the first chip 1.

In addition, an input / output metal pad 520 commonly used for the first and second chips 1 and 2 is formed on the uppermost layer of the second chip 2. The input / output metal pad 520 may be connected to the input / output control circuit 10a of the first chip 1, and data may be output to the first and second chips 1 and 2 through the input / output metal pad 520. And may be input.

As described above, a high-capacity and highly integrated semiconductor memory device may be implemented by stacking the first and second chips 1 and 2 having a three-dimensional structure to form a large-capacity semiconductor memory device.

Hereinafter, a method of manufacturing a large-capacity semiconductor memory device according to a second embodiment of the present invention will be described in detail with reference to FIGS. 8 and 9 through 11. The manufacturing method of the large capacity semiconductor memory device according to the second embodiment of the present invention will not be described in detail with respect to the technical features overlapping with the manufacturing method of the large capacity semiconductor memory device according to the first embodiment of the present invention. Differences from the embodiments will be described in detail.

Referring to FIG. 9, first a first chip 1 is formed. Forming the first chip 1 is substantially the same as the manufacturing method of the large capacity semiconductor memory device according to the first embodiment. In brief, logic elements including an input / output control circuit 10a, a central control circuit 10b, a buffer memory control circuit 10c, and main memory control circuits 10d and 10e on the semiconductor substrate 100 may be described. 10) form. Logic elements 10 may be formed of a plurality of transistors 10, contacts, and wirings 122. The logic elements 10 are filled by the first interlayer insulating layers 120 to 140, and a bonding layer 150 is formed on the first interlayer insulating layer 140 of the uppermost layer.

Thereafter, after the single crystal semiconductor substrate is bonded on the bonding layer 150, the buffer and / or main memory devices 20a and 30a are formed. The contacts 222 and 322 are formed to connect the buffer and / or main memory elements 20a and 30a to the buffer and / or main memory control circuits 10c, 10d and 10e.

The stacked buffer and / or main memory devices 20a and 30a may be buried in the second and third interlayer insulating layers 220 to 240 and 320 to 330, and the third interlayer insulating layer 330 may be disposed on the uppermost layer. Contact pads 400 are formed to be connected to the second chip to be bonded to the upper portion.

In addition, a second chip (see 2 in FIG. 10) is bonded to the third interlayer insulating layer 330 disposed on the uppermost layer, and for electrical connection between the second chip (see 2 in FIG. 10) and the first chip 1. And bond pads 355 and 357. The bonding pads 355 and 357 are connected to the contact pads 400 connected to the input / output control circuit 10a and the main memory control circuit 10e, respectively.

Referring to FIG. 10, a second chip 2 to be bonded to the first chip (1 of FIG. 9) is separately formed. Forming the second chip 2 is substantially the same as the method of forming the first chip 1. In brief, on the semiconductor substrate 100 of the second chip 2, the central control circuit 10b for controlling the operation of the second chip 2 and the buffer or main memory elements 20a and 30a are placed. The main memory control circuit 10d for controlling is formed. In addition, on the logic elements 10, as described above, the buffer and / or main memory elements 20a and 30a are stacked by bonding the single crystal semiconductor substrate using the bonding layers 150 and 250. In addition, contact plugs 222 and 322 are formed to connect the main memory control circuit 10d to the buffer and / or the main memory devices 20a and 30a.

Thereafter, the semiconductor substrate 100 and the first to third interlayer insulating layers 120 to 140, 220 to 240, and 320 are sequentially etched from the lower surface of the semiconductor substrate 100 of the second chip 2, thereby contacting the semiconductor chip 100. A hole is formed, and a conductive material is filled in the contact hole to form through silicon vias 510. The through silicon via 510 may be connected to the contact plugs 222 and 322 to be electrically connected to the main memory control circuit 10d of the second chip 2. In addition, the through silicon via 510 may be an independent structure that is not electrically connected to the logic elements 10b and 10d and the memory elements 20a and 30a in the second chip 2.

Subsequently, bonding pads 520 and 530 are formed on the bottom surface of the semiconductor substrate 100 of the second chip 2 in contact with the respective through silicon vias 510.

Referring to FIG. 11, the bonding pads 355 and 357 of the first chip 1 and the bonding pads 52 and 530 of the second chip 2 face each other, so that the first chip 1 And the second chip 2 are bonded. Specifically, the third interlayer insulating film 330 of the first chip 1 and the bottom surface of the semiconductor substrate 100 of the second chip 2 are bonded to each other.

Referring again to FIG. 8, as the first chip 1 and the second chip 2 are bonded, the bonding pads 355 and 357 are bonded to each other. Accordingly, the through silicon vias 510 of the second chip 2 may be connected to the input / output control circuit 10a and the main memory control circuit 10e of the first chip 1, respectively.

Subsequently, an input / output metal pad 550 connected to the through silicon via 510 is formed on the uppermost layer of the second chip 1. The input / output metal pad 520 is connected to the input / output control circuit 10a of the first chip 1 through the through silicon via 510.

Hereinafter, a high-capacity semiconductor memory device according to a third embodiment of the present invention will be described in detail with reference to FIG. 12. For the third embodiment, a detailed description of technical features overlapping with the second embodiment of the present invention will be omitted, and the difference from the second embodiment will be described in detail.

Referring to FIG. 12, a large capacity semiconductor memory device according to a third embodiment of the present invention includes a first chip 1 and a second chip 2, and the first chip 1 and the second chip 2. It is electrically connected through this solder bump 450.

Specifically, the first chip 10 has a three-dimensional structure in which the logic elements 10 and the memory elements 20 and 30 are sequentially stacked on the semiconductor substrate 100, and each logic and memory element 10, 20 and 30 are joined via bonding layers 150 and 250.

In the first chip 1, the logic element 10 includes an input / output control circuit 10a, a central control circuit 10b, a buffer memory control circuit 10b, and a main memory control circuit 10d. In addition, in the first chip 1, the memory elements 20 and 30 on the logic elements 10 include a buffer memory element 20a and a main memory element 30a. The buffer and main memory elements 20a and 30a are connected to the corresponding buffer and main memory control circuits 10c and 10d through contacts 222 and 322, respectively.

In addition, an input / output metal pad 410 and a connection pad 420 for connecting the chips are positioned on the third interlayer insulating layer 330 positioned on the uppermost layer of the first chip 1.

The input / output metal pad 410 may be connected to a lead 470 of another external semiconductor device through the solder bump 450. That is, data may be output to or received from another external semiconductor device through the input / output metal pad 410. In addition, the connection pad 420 may be electrically connected to another second chip 2 through the solder bumps 450.

The second chip 2 may be substantially the same as the first chip 1 except for the input / output control circuit 10a provided in the first chip 1. That is, the second chip 2 includes logic elements 10 and memory elements 20a and 30a formed in a three-dimensional structure on the semiconductor substrate 100. In the logic elements 10, the main memory control circuit 10d is connected to the main memory elements 20a and 30a of each layer through the contacts 222 and 322.

In addition, a connection pad 420 may be positioned on the third interlayer insulating layer 330 located at the uppermost layer in the second chip 2. The connection pad 420 is connected to the main memory control circuit 10d formed on the semiconductor substrate 100 through the contacts 222 and 322.

The connection pads 420 formed on the first chip 1 and the second chip 2 may be connected to each other through the solder bumps 450. As such, as the first and second chips 1 and 2 are electrically connected through the solder bumps 450, input / output of data to the second chip 2 may be controlled through the first chip 1. have.

Hereinafter, a method of manufacturing a large capacity semiconductor memory device according to a third embodiment of the present invention will be described in detail with reference to FIGS. 12 to 14. The manufacturing method of the large-capacity semiconductor memory device according to the third embodiment of the present invention will not be described in detail with respect to the technical features overlapping with the manufacturing method of the high-capacity semiconductor memory device according to the second embodiment of the present invention. Differences from the embodiments will be described in detail.

Referring to FIG. 13, the first chip 1 is formed. Forming the first chip 1 is substantially the same as the manufacturing method of the large capacity semiconductor memory device according to the first embodiment. In brief, logic elements including an input / output control circuit 10a, a central control circuit 10b, a buffer memory control circuit 10c, and main memory control circuits 10d and 10e on the semiconductor substrate 100 may be described. 10) form. Logic elements 10 may be formed of a plurality of transistors 10, contacts, and wirings 122.

The logic devices 10 may be embedded with the first interlayer insulating layers 120 to 140, and the buffer and / or main memory devices 20a may be formed on the uppermost first interlayer insulating layer 140 through the bonding layer 150. 30a) are laminated.

The input / output metal pad 410 and the connection pads 420 are formed on the uppermost third interlayer insulating layer 330. The input / output metal pad 410 is connected to the lower input / output control circuit 10a through the contacts 222 and 322, and the connection pad 420 is connected to the lower main memory control circuit through the contacts 222 and 322. 10e).

Referring to FIG. 14, a second chip 2 to be bonded to the first chip (1 of FIG. 9) is separately formed. Forming the second chip 2 is substantially the same as the method of forming the first chip 1. In brief, on the semiconductor substrate 100 of the second chip 2, the central control circuit 10b and the buffer and / or main memory elements 20a and 30a controlling the operation of the second chip 2 are provided. To form a buffer and / or main memory control circuit 10d.

The buffer and / or main memory elements 20a and 30a are stacked on the logic elements 10, and the buffer and / or main memory elements 20a and 30a are disposed through the contacts 222 and 322. And / or electrically connect with the main memory control circuit 10d.

Then, connection pads 420 are formed on the third interlayer insulating layer 330 of the uppermost layer to be connected to the lower main memory control circuit 10d through the contacts 222 and 322.

Referring to FIG. 12 again, the third interlayer insulating film 330 of the first chip 1 and the third interlayer insulating film 330 of the second chip 2 face each other, so that the first and second chips ( The connection pads 420 of 1 and 2 are bonded to each other. The connection pads 420 may be interconnected through the solder bumps 450.

After the first chip 1 and the second chip 2 are connected to each other, a lead 470 of another external semiconductor device is connected to the input / output metal pad 410 of the first chip 1. .

Hereinafter, a large capacity semiconductor memory device according to a fourth embodiment of the present invention will be described in detail with reference to FIG. 15. For the fourth embodiment, a detailed description of technical features overlapping with the third embodiment of the present invention will be omitted, and the difference from the third embodiment will be described in detail.

Referring to FIG. 15, a large capacity semiconductor memory device according to a fourth embodiment of the present invention is a hybrid semiconductor memory device. Specifically, the large-capacity semiconductor memory device includes a first chip 1 that is a solid state drive and a hard disk drive (HDD).

The first chip 1 may be configured substantially the same as the first chip described in detail in the third embodiment. That is, in the first chip 1, the logic device 10 and the semiconductor devices 20 and 30 are stacked in a three-dimensional structure through bonding. The logic element 10 in the first chip 1 further comprises an HDD control circuit 10e for controlling the hard disk drive HDD, unlike in other embodiments. The HDD control circuit 10e is connected to the connection pad 420 through the contacts passing through the first to third interlayer insulating films. The hard disk drive HDD is connected to the connection pad 420 through solder bumps.

FIG. 16 is a schematic diagram illustrating a semiconductor device including a large-capacity semiconductor memory device manufactured from one chip according to embodiments of the present disclosure.

 Referring to FIG. 16, a logic element and a plurality of memory elements may be bonded to each other through a bonding layer, and a high-capacity semiconductor memory device 1000 manufactured as a single chip may be mounted on the printed circuit board 1010. In the large-capacity semiconductor memory device 1000 made of a single chip, a signal may be input and output from an external host (not shown) through an input / output pad 1020 formed on a printed circuit board 1010.

As described above, a large-capacity semiconductor device manufactured by a single chip is mounted on a printed circuit board, such as a compact flash card, a compact digital card (SD), a smart card (SMC), a multimedia card (MMC), and a USB. Or a memory stick.

FIG. 17 is a block diagram of a large-capacity semiconductor memory device manufactured from one chip according to embodiments of the present invention.

Referring to FIG. 17, a large-capacity semiconductor memory device 1000 manufactured as a single chip according to example embodiments may include a processor 1001, a nonvolatile memory interface 1002, and a plurality of nonvolatile memory units, which are central control circuits. 1003, a volatile memory unit 1004, and a buffer unit 1005. The high capacity semiconductor memory device 1000 is connected to the host interface 1100.

The host interface 1100 is directly connected to an external host (not shown) through a bus and receives signals from the external host through the bus. Control signals, addresses and data are input from the external host. The host interface 1100 may interface with an external host according to a predetermined protocol such as ATA.

The signals input from the external host are converted into internal signals for controlling the nonvolatile and volatile memory units 1003 and 1004 in the host interface 1100, and the internal signals are input to the processor 1001. The processor 1001 performs a write / read operation of data to the selected memory units 1003 and 1004 according to the input internal signals.

The buffer unit 1005 temporarily stores frequently accessed data. As the buffer unit 240 is provided, when the external host (not shown) accesses the large-capacity semiconductor memory device 1000 of the one chip, the time required for the data read operation may be reduced.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 to 11 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

12 to 19 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

20 to 27 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a third embodiment of the present invention.

28 to 37 are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with a fourth embodiment of the present invention.

Claims (32)

A plurality of logic elements formed on the semiconductor substrate; A first interlayer insulating layer covering the logic elements; A bonding layer formed on the first interlayer insulating film; A plurality of memory elements stacked on the junction layer and connected to the logic elements; A second interlayer insulating layer covering the memory elements; And An input / output metal pad formed on the second interlayer insulating layer and electrically connected to the logic elements, The logic elements may include an input / output control circuit that controls input / output of data through the input / output metal pad; A plurality of memory element control circuits corresponding to each of the memory elements and controlling the memory elements; And a central control circuit for controlling the input / output control circuit and the memory device control circuits. The method of claim 1, The memory devices may include dynamic random access memory (DRAM), static random access memory (SRAM), phase-change random access memory (PRAM), ferroelectrics random access memory (FRAM), magnetic random access memory (MRAM), and resistive random (RRAM). A large capacity semiconductor memory device including at least two of Access Memory) and flash memory. The method of claim 1, The memory devices include a buffer memory device and a main memory device. The method of claim 3, wherein The buffer memory device is a large capacity semiconductor memory device bonded to the upper or lower portion of the main memory device through a bonding layer. The method of claim 1, The memory device includes a transistor having a vertical channel or a horizontal channel transistor. The method of claim 5, Transistors having the vertical channel, Semiconductor patterns having a pillar shape and alternately stacked with conductive layers opposite to each other; A gate electrode surrounding sidewall center portions of the semiconductor patterns; And And a gate insulating layer formed between sidewalls of the semiconductor patterns and the gate electrode. The method of claim 6, The semiconductor pattern is a large-capacity semiconductor memory device consisting of a p-type / n-type / p-type impurity layer or an n-type / p-type / n-type impurity layer. The method of claim 5, Transistors having the horizontal channel, A single crystal semiconductor substrate bonded on the bonding layer; A gate insulating film and a gate electrode stacked on the single crystal semiconductor substrate; And And an impurity region formed in the gate insulating film and the single crystal semiconductor substrate on both sides of the gate electrode. The method of claim 1, The semiconductor substrate, the plurality of logic elements, the first interlayer insulating layer, the junction layer, the memory elements, and the second interlayer insulating layer constitute one first chip, and the first chip includes a plurality of first chips. But And a second interlayer insulating film of the first chip of any of the plurality of first chips, and a bottom surface of the semiconductor substrate of the other of the first chips. The method of claim 9, And a via penetrating the plurality of first chips vertically, the via electrically connected to the logic elements of the first chips, The input / output metal pad is formed on a first chip positioned on a top layer of the plurality of first chips and is electrically connected to the via. The method of claim 1, The semiconductor substrate, the plurality of logic elements, the first interlayer insulating layer, the junction layer, the memory elements, and the second interlayer insulating layer constitute one first chip, and the first chip includes a plurality of first chips. But Each of the plurality of first chips further includes a connection pad formed on the second interlayer insulating layer and electrically connected to the logic elements. The plurality of first chips is a large capacity semiconductor memory device in which the connection pads are bonded to each other through a bump. The method of claim 11, wherein The input / output metal pad is formed on a first chip of any one of the plurality of first chips. The method of claim 1, A connection pad formed on the second interlayer insulating layer and electrically connected to the logic elements; And And a hard disk drive electrically connected to the connection pad. The method of claim 13, And said hard disk drive is controlled by said logic elements. Providing a first semiconductor substrate, Forming logic elements on the first semiconductor substrate, Forming a first interlayer insulating film covering the logic elements, Forming a bonding layer on the first interlayer insulating film, Stacking a plurality of memory elements connected to the logic elements on the junction layer, Forming a second interlayer insulating film covering the memory elements, Forming an input / output metal pad electrically connected to the logic elements on the second interlayer insulating layers, Forming the logic elements, An input / output control circuit for controlling input and output of data through the input / output metal pad; A plurality of memory element control circuits corresponding to each of the memory elements and controlling the memory elements; And forming a central control circuit for controlling the input / output control circuit and the memory element control circuits. The method of claim 15, Forming the memory elements,  Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Phase-change Random Access Memory (PRAM), Ferroelectrics Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), and A method of manufacturing a large capacity semiconductor memory device comprising forming at least two or more of flash memories. The method of claim 15, Forming the memory elements, A method of manufacturing a large capacity semiconductor memory device comprising forming a buffer memory element and main memory elements. The method of claim 17, And the buffer memory device is formed above or below the main memory device. The method of claim 15, Forming the memory elements, Bonding a single crystal semiconductor substrate on the bonding layer, and forming the memory elements on the single crystal semiconductor substrate. The method of claim 19, Bonding the single crystal semiconductor substrate, Preparing the single crystal semiconductor substrate, Forming a plurality of impurity layers doped with impurities uniformly from an upper surface of the single crystal semiconductor substrate to a predetermined depth, Bonding the single crystal semiconductor substrate to face the bonding layer and the impurity layer; Removing a portion of the single crystal semiconductor substrate until the impurity layer surface is exposed. The method of claim 20, The forming of the plurality of impurity layers comprises forming a p-type / n-type / p-type impurity layer or an n-type / p-type / n-type impurity layer from an upper surface of the single crystal semiconductor substrate. The method of claim 20, After forming the plurality of impurity layers, And forming a separation layer at a depth in contact with the impurity layer in the single crystal semiconductor substrate. The method of claim 22, The method for manufacturing a large-capacity semiconductor memory device wherein the separation layer is formed of a bubble layer. The method of claim 20, After bonding the single crystal semiconductor substrate, Patterning the plurality of impurity layers to form pillar-shaped semiconductor patterns, And forming a gate electrode surrounding the circumference of the semiconductor pattern. The method of claim 19, Bonding the single crystal semiconductor substrate, Preparing the single crystal semiconductor substrate, Providing the single crystal semiconductor substrate including an impurity layer doped with impurities uniformly from an upper surface of the single crystal semiconductor substrate to a predetermined depth, Bonding the single crystal semiconductor substrate to the upper surface of the interlayer insulating film and the impurity layer to face each other; Removing a portion of the single crystal semiconductor substrate until the impurity layer surface is exposed. The method of claim 20, After forming the plurality of impurity layers, And forming a separation layer in the single crystal semiconductor substrate at a depth in contact with the impurity layer. The method of claim 25, After bonding the single crystal semiconductor substrate, Forming gate electrodes on the second semiconductor substrate, and forming impurity regions on both sides of the gate electrodes. The method of claim 15, And forming a single chip by forming the semiconductor substrate, the plurality of logic elements, the first interlayer insulating layer, the junction layer, the memory elements, and the second interlayer insulating layer. Form a plurality, Manufacturing a large-capacity semiconductor memory device further comprising bonding the second interlayer insulating film of the first chip of the plurality of first chips and the bottom surface of the semiconductor substrate of the other first chip to each other. Way. 29. The method of claim 28, Vertically penetrating the plurality of first chips to form vias electrically connected to logic elements of a first chip positioned below one of the plurality of first chips, The input / output metal pad is formed on the second interlayer insulating layers of the first chip positioned on the uppermost layer of the plurality of first chips and connected to the via. The method of claim 15, And forming a single chip by forming the semiconductor substrate, the plurality of logic elements, the first interlayer insulating layer, the junction layer, the memory elements, and the second interlayer insulating layer. Form a plurality, Forming connection pads electrically connected to the logic elements on the second interlayer insulating layer of each of the plurality of first chips, And bonding the connection pads of the plurality of first chips to each other through bumps. 31. The method of claim 30, And forming the input / output metal pads on the second interlayer insulating layer of any one of the plurality of first chips. The method of claim 15, Forming connection pads electrically connected to the logic elements on the second interlayer insulating layer; And forming a hard disk drive electrically connected to the connection pads.

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