JP2006303024A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the yield and reliability of elements in a memory can be improved and the devices of a logic can be made micro, and to provide its manufacturing method. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 11 having a memory 1 and a logic 2 arranged around the memory part 1; a first device isolating insulating film 23 which is buried in the memory 1 and of which width Lt<SB>1</SB>of the upper surface is larger than that Lb<SB>1</SB>of the lower surface; a second device isolating insulating film 22 which is buried in the logic 2 and has a side wall nearly vertical to the main surface of a semiconductor substrate 11, and of which width L2 is smaller than the width Lt<SB>1</SB>of the upper surface of the first device isolating insulating film 23; a tunnel insulating film 25a which is pinched by the first device isolating insulating film 23 and is arranged on the semiconductor substrate 11; a floating gate electrode 27a on the tunnel insulating film 25a; a first control gate electrode 30a which is arranged on the floating gate electrode 27a while being electrically insulated therefrom; a gate insulating film 29b which is pinched by the second device isolating insulating film 22, and is arranged on the semiconductor substrate 11; and a second control gate electrode 30b on the gate insulating film 29b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which element isolation is performed by a shallow trench isolation (STI) technique and a method for manufacturing the semiconductor device.

  As the system scales up, CMOS technology is becoming finer. In semiconductor devices of the design rule 0.25 μm generation and beyond, it is necessary to reduce not only the gate length of the logic part but also the width of the element isolation region. For this reason, element isolation formation technology by shallow trench isolation (STI) is used as a main technology instead of local oxidation (LOCOS) of silicon having a large process conversion difference (see, for example, Patent Document 1).

  In STI, a semiconductor substrate is etched by reactive ion etching (RIE) technology to form a groove, and an insulating film is embedded in the groove to form an element isolation region. STI is advantageous for miniaturization compared to LOCOS isolation in that the process conversion difference is close to 0 and an ideal element isolation shape can be obtained. However, for example, in a region where a non-volatile memory is mounted, a thin tunnel oxide film having a thickness of about 8 nm is formed in contact with a thick STI buried oxide film. For this reason, the region in contact with the buried oxide film becomes insufficient in oxygen supply, and the tunnel oxide film becomes thinner in the oxygen supply insufficient region. When thinning occurs, durability is significantly deteriorated when a high electric field of 10 to 15 MV / cm is applied as compared with the case of separation by LOCOS. Further, there is a problem that stress-induced leakage current is generated due to the thinning of the tunnel oxide film and reliability is lowered.

  Further, when the element isolation formation technology by STI is used instead of LOCOS, stress may be generated near the corner of the upper surface or the lower surface of the buried oxide film, and crystal defects may occur. When a crystal defect occurs, a leak occurs when a high voltage (Vpp) of 10 to 20 V is applied to the substrate during the erase / write operation of the nonvolatile memory, so that the erase / write operation cannot be performed sufficiently and the yield is reduced. .

Japanese Patent Laid-Open No. 2004-56072

  The present invention provides a semiconductor device and a method for manufacturing the semiconductor device that can improve the yield and reliability of the elements in the memory portion and can miniaturize the elements in the logic portion.

  One aspect of the present invention is: (a) a semiconductor substrate having a memory portion and a logic portion arranged around the memory portion; and (b) a first element embedded in the memory portion and having a top surface width greater than a bottom surface width. An isolation insulating film; and (c) a second element isolation insulating film embedded in the logic portion, having a side wall substantially perpendicular to the main surface of the semiconductor substrate, and having a width smaller than the width of the upper surface of the first element isolation insulating film; (D) a tunnel insulating film disposed on a semiconductor substrate sandwiched between first element isolation insulating films, (e) a floating gate electrode on the tunnel insulating film, and (f) a floating gate electrode on the floating gate electrode. A first control gate electrode disposed in an insulating manner; (g) a gate insulating film on a semiconductor substrate sandwiched between second element isolation insulating films; and (h) a second control gate electrode on the gate insulating film. The gist is that the semiconductor device is provided.

  According to still another aspect of the present invention, (a) a first groove having a width larger than that of a bottom surface is formed in a memory portion on a semiconductor substrate, and a first element isolation insulating film is formed in the first groove. And (b) forming a second groove having a width of the opening smaller than the width of the opening of the first groove and having a substantially vertical side wall in the logic portion arranged around the memory portion. Burying a second element isolation insulating film in each of the second trenches; (c) forming a tunnel insulating film on the semiconductor substrate sandwiched between the first element isolation insulating films; and (d) a tunnel insulating film. Forming a floating gate electrode thereon; (e) forming an intergate insulating film on the floating gate electrode; (f) forming a first control gate electrode on the intergate insulating film; G) Gate insulation on the semiconductor substrate sandwiched between the second element isolation insulating films Forming a, and summarized in that a method of manufacturing a semiconductor device and forming a second control gate electrode on the (h) a gate insulating film.

  ADVANTAGE OF THE INVENTION According to this invention, the yield and reliability of the element of a memory part can be improved, and the manufacturing method of a semiconductor device which can miniaturize the element of a logic part, and a semiconductor device can be provided.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and the dimensions and the like of each block are different from the actual ones. It goes without saying that the drawings include parts having different dimensional relationships and ratios. The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is to change the structure and arrangement of components to the following. Not specific. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
As shown in FIG. 1, the semiconductor device according to the first embodiment includes a semiconductor substrate 11 having a memory unit 1 and a logic unit 2 arranged around the memory unit 1.

  As shown in FIG. 2, the memory unit 1 is disposed on a first element isolation insulating film 23 embedded as a plurality of regions in a cross-sectional view, and a semiconductor substrate 11 sandwiched between the plurality of first element isolation insulating films 23. A tunnel insulating film 25a, a floating gate electrode 27a on the tunnel insulating film 25a, an inter-gate insulating film 28a on the floating gate electrode 27a, and a first control gate electrode 30a disposed on the inter-gate insulating film 28a. The first control gate electrode 30a is insulated from the floating gate electrode 27a by the intergate insulating film 28a.

  A source region 31 and a drain region 32 are formed around the surface region of the semiconductor substrate 11 immediately below the tunnel insulating film 25a. The tunnel insulating film 25a, the floating gate electrode 27a, the inter-gate insulating film 28a, the first control gate electrode 30a, the source region 31, and the drain region 32 constitute a memory cell 40a of the memory unit 1 as shown in FIG. . That is, “embedded as a plurality of regions on the cross-sectional view” means that it is embedded as a plurality of regions on the cross-sectional view along the channel region (or gate length direction) of the memory cell 40a as shown in FIG. In reality, it may be an integrated region that is continuous in front of or behind the paper surface of FIG.

As shown in FIG. 3, in the first element isolation insulating film 23, the upper surface width Lt ₁ located at the same level as the main surface of the semiconductor substrate 11 is larger than the lower surface width Lb ₁ . Here, the widths Lt ₁ and Lb ₁ of the upper surface and the lower surface are defined in a direction parallel to the main surface of the semiconductor substrate 11 in the cross-sectional view of FIG. In addition, the angle α between the upper surface of the first element isolation insulating film 23 and the side wall at the corner portion of the upper surface of the first element isolation insulating film 23 in contact with the tunnel insulating film 25a is smaller than 90 degrees. The angle α of the corner portion of the first element isolation insulating film 23 is preferably 80 degrees or less, more preferably about 70 to 80 degrees.

A channel stop region 26 is disposed in the semiconductor substrate 11 below the first element isolation insulating film 23. The channel stop region 26 is an impurity diffusion layer doped with an acceptor of about 1 × 10 ₁₇ cm ₋₃ to 1 × 10 ₁₈ cm ₋₃ . As shown in FIG. 1, the channel stop region 26 is buried perpendicular to the direction in which the high voltage is applied to the memory cell 40a. The arrangement of the channel stop region 26 shown in FIG. 1 is suitable when a byte EEPROM is employed as the memory unit 1. In the case where the memory unit 1 is a flash EEPROM, the channel stop region 26 need not be particularly arranged.

  The logic section 2 is disposed on the semiconductor substrate 11 sandwiched between the second element isolation insulating film 22 embedded as a plurality of regions on the cross-sectional view of FIG. And a second control gate electrode 30b on the gate insulating film 29b. A source region 33 and a drain region 34 are formed around the surface region of the semiconductor substrate 11 immediately below the gate insulating film 29b.

  The gate insulating film 29b, the second control gate electrode 30b, the source region 33, and the drain region 34 constitute a logic cell 50a as shown in FIG. That is, the “second element isolation insulating film 22 embedded as a plurality of regions on the cross-sectional view” means a cross-section along the channel direction (gate length direction) of the transistors constituting the logic cell 50a as shown in FIG. In the figure, it is meant to allow a case where it appears to be embedded as a plurality of regions. In reality, as shown in FIG. 1, even in an integrated region continuous around the transistors constituting the logic cell 50a. Good.

As shown in FIG. 2, the second element isolation insulating film 22 has a side wall substantially perpendicular to the main surface of the semiconductor substrate 11. Here, the “substantially vertical side wall” is defined by the upper surface and the side wall of the second element isolation insulating film 22 at the corner portion of the upper surface of the second element isolation insulating film 22 in contact with the source region 33 and the drain region 34, respectively. It means that the angle β is 80 to 90 degrees. Since the side wall is substantially vertical, the width Lt ₂ of the upper surface of the second element isolation insulating film 22 located at the same level as the main surface of the semiconductor substrate 11 is substantially the same as the width Lb _{2 of} the lower surface. For this reason, the second element isolation insulating film 22 is defined by a common width L2 = Lt ₂ = Lb ₂ .

Here, the width L 2 of the second element isolation insulating film 22 is smaller than the width Lt ₁ of the upper surface of the first element isolation insulating film 23. That is, the width L2 is defined in a direction parallel to the main surface of the semiconductor substrate 11 on the cross-sectional view of FIG. Even if the widths Lt ₂ and Lb ₂ of the second element isolation insulating film 22 are defined in a direction parallel to the main surface of the semiconductor substrate 11 on the cross section of FIG. 3, a certain purpose can be achieved. .

According to the semiconductor device shown in FIGS. 2 and 3, the width Lt ₁ of the upper surface of the first element isolation insulating film 23 of the memory unit 1 is larger than the width Lb ₁ of the bottom surface. The side walls of the first element isolation insulating film 23 are formed so as to be inclined at 90 degrees or less with respect to the main surface of the semiconductor substrate 11, so that the semiconductor substrate 11 is like a buried insulating film of STI generally used. Compared with the case where the side wall perpendicular to the main surface is formed, crystal defects at the corners of the first element isolation insulating film 23 are less likely to occur. As a result, even when a high voltage of 10 to 20 V is applied during the erase / write operation of the memory unit 1, a leakage current due to the high voltage due to the presence of crystal defects can be prevented, and the yield can be improved.

On the other hand, since a low voltage is applied to the logic cell 50a of the logic unit 2 compared to the memory cell 40a, the gate insulating film 29b that insulates the second control gate electrode 30b is thinner than the tunnel insulating film 25a. Is formed. Therefore, a thinning phenomenon due to insufficient oxygen supply during the formation of the tunnel insulating film 25a is unlikely to occur. For this reason, in the semiconductor device shown in FIGS. 2 and 3, the width Lt ₂ of the upper surface of the second element isolation insulating film 22 is made smaller than the width Lt ₁ of the upper surface of the first element isolation insulating film 23, and is approximately on the main surface. By embedding with a vertical side wall, the logic cell 50a can be miniaturized. As a result, it is possible to provide a semiconductor device in which the yield and reliability of the memory cell 40a in the memory unit 1 are increased and the structure of the logic cell 50a in the logic unit 2 is miniaturized.

  A method for manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS. The semiconductor device manufacturing method described below is merely an example, and it is needless to say that the present invention can be realized by various other assembly methods including this modification. Note that the memory unit 1 in FIGS. 4 to 12 shows a cross section as viewed from the BB direction in FIG. 1. The memory unit 1 in FIGS. 13 to 17 shows a cross section viewed from the direction AA in FIG. The logic part 2 of FIGS. 4-17 shows the cross section seen from the AA direction of FIG.

  (A) A first oxide film 12 of about 5 nm is deposited on the surface of the semiconductor substrate 11. A nitride film 13 of about 100 nm is deposited on the surface of the first oxide film 12. On the surface of the nitride film 13, a film sufficiently thicker than the first oxide film 12, for example, a second oxide film 14 of about 150 nm is deposited. Next, a resist film 15 is applied to the surface of the second oxide film 14, and the resist film 15 is patterned by a photolithography technique to partially expose the second oxide film 14 as shown in FIG.

  (B) As shown in FIG. 5, the second oxide film 14 partially exposed from the resist film 15 is removed by anisotropic etching such as RIE. Thereafter, the remaining resist film 15 is peeled off. Using the patterned second oxide film 14 as a mask, as shown in FIG. 6, the nitride film 13 and a part of the first oxide film 12 are selectively removed by RIE. As shown in FIG. 7, a resist film 16 is selectively coated on the memory portion 1, and a part of the semiconductor substrate 11 in the logic portion 2 is etched to form a groove (second groove) 17. At this time, the second side is formed by RIE or the like so that the side wall of the second groove 17 is substantially vertical, that is, the side wall angle β viewed from the main surface of the semiconductor substrate 11 is 90 degrees or 80 to 90 degrees. The groove 17 is formed.

(C) As shown in FIG. 8, a resist film 18 is applied on the logic part 2, and a part of the semiconductor substrate 11 of the memory part 1 is etched to form a groove (first groove) 20. In the etching, the reaction product is gradually deposited on the side wall of the first groove 20 by reducing the flow rate of the etching gas or reducing the time for discharging the gas, and the width Lt ₁ is larger than the width Lb _1. It is formed by RIE or the like so as to widen. Thereafter, the reaction product remaining on the side wall of the first groove 20 is removed. Here, on the cross section of FIG. 8, the angle α of the side wall of the first groove 20 viewed from the main surface side of the semiconductor substrate 11 is preferably 80 degrees or less, or about 70 to 80 degrees. Further, the width Lt ₁ of the opening of the first groove 20 is preferably formed wider than the width Lt ₂ of the opening of the second groove 17 of the logic part 2. For example, the width Lt ₁ of the opening of the first groove 20 can be about 0.7 to 0.8 μm, and the width L2 of the opening of the second groove 17 can be about 0.2 to 0.4 μm. 7 and 8 show an example in which the second groove 17 is formed first. However, before the second groove 17 is formed, the first groove 20 is formed first. Of course, it is also good.

(D) As shown in FIG. 9, a third oxide film 21 of about 550 nm is deposited on the entire surface of the semiconductor substrate 11. Using the nitride film 13 as a stopper layer, planarization is performed until the surface of the nitride film 13 is exposed by chemical mechanical polishing (CMP) or the like. As shown in FIG. 10, the first element isolation insulating film 23 is embedded in the first groove 20 of the memory unit 1, and the second element isolation insulating film 22 is embedded in the second groove 17 of the logic unit 2. Then, a resist film 24 is applied to the surfaces of the nitride film 13, the first element isolation insulating film 23, and the second element isolation insulating film 22. As shown in FIG. 11, a mask is aligned with the center of the first element isolation insulating film 23 of the memory unit 1 and an opening is provided in a part of the resist film 24 by photolithography. For example, p-type impurity ions such as boron (B) are selectively implanted into the semiconductor substrate 11 from the opening. In this manner, the channel stop region 26 extending in the direction in which the high voltage is applied to the memory cell 40a is formed in the semiconductor substrate 11 below the first element isolation insulating film 23. Thereafter, the resist film 24 is removed.

(E) Further, the nitride film 13 and the first oxide film 12 on the surface of the semiconductor substrate 11 are peeled off, and a tunnel insulating film 25 of about 8 nm is formed on the surface of the semiconductor substrate 11 of the memory unit 1. As the tunnel insulating film 25, an oxide film, an oxynitride (SiO _x N _y ) film or the like is suitable. On the surface of the tunnel insulating film 25, as shown in FIG. 12, a first polysilicon film 27 to be a floating gate is deposited to about 100 nm. The first polysilicon film 27 and the tunnel insulating film 25 are etched by RIE to form a pattern of the tunnel insulating film planned region 25A and the floating gate electrode planned region 27A of the memory cell 40a. Thereafter, an inter-gate insulating film 28 is deposited on the surface of the semiconductor substrate 11 by about 15 nm as shown in FIG. As the inter-gate insulating film 28, for example, an oxide film, an ONO film or the like is suitable.

  (F) As shown in FIG. 14, the inter-gate insulating film 28, the first polysilicon film 27, and the tunnel insulating film 25 deposited in the logic unit 2 are selectively peeled off. As shown in FIG. 15, a gate insulating film 29 is deposited on the surface of the semiconductor substrate 11 in the logic section 2 by about 3 nm, and a second polysilicon film of about 200 nm is formed on the entire surface of the gate insulating film 29 and the memory section 1. A film 30 is deposited. Thereafter, the second polysilicon film 30, the intergate insulating film 28, the floating gate electrode planned region 27A, and the tunnel insulating film planned region 25A of the memory unit 1 are etched together. As a result, as shown in FIG. 16, a tunnel insulating film 25a, a floating gate electrode 27a, an intergate insulating film 28a, and a first control gate electrode 30a are formed on the semiconductor substrate 11. In the logic part 2, the second polysilicon film 30 and the gate insulating film 29 are etched by RIE to form the gate insulating film 29b and the second control gate electrode 30b of the logic cell 50a. As shown in FIG. 17, if n-type impurity ions such as phosphorus (P) and arsenic (As) are selectively implanted into the semiconductor substrate 11 and the implanted ions are activated by heat treatment, the source region 31 is obtained. 33 and drain regions 32 and 34 are formed, and the semiconductor device shown in FIGS. 1 to 3 is completed.

  According to the method for manufacturing a semiconductor device according to the first embodiment, the first groove 20 in which the angle α formed between the main surface of the semiconductor substrate 11 and the side wall of the first element isolation insulating film 23 is 90 degrees or less is formed. A first element isolation insulating film 23 is buried in the first trench 20 by STI. For this reason, even when the tunnel insulating film 25 of about 8 nm is formed in the memory portion 1 on the semiconductor substrate 11, the oxygen deficiency is lower than that of the STI buried insulating film formed by being buried perpendicularly to the semiconductor substrate 11. Generation of the area can be suppressed. As a result, the thinning phenomenon of the tunnel insulating film 25 in the contact region with the first element isolation insulating film 23 can be suppressed, and the tunnel insulating film 25 having a uniform thickness can be formed on the semiconductor substrate 11. Therefore, according to the manufacturing method of the semiconductor device shown in FIGS. 4 to 17, even when the STI is used for the memory unit 1, reliability and yield equal to or higher than those of LOCOS isolation can be ensured, and stress at the time of applying high voltage Generation of induced leakage current can be prevented.

As shown in FIG. 8, the width Lt ₁ of the first element isolation insulating film 23 is formed larger than the width Lb ₁ . As a result, crystal defects at the corners of the upper surface and the lower surface of the first element isolation insulating film 23 can be made less likely to occur than in the STI embedded insulating film embedded perpendicularly to the semiconductor substrate 11 and the reliability is improved. be able to.

Since the gate insulating film 29 of the logic unit 2 that operates in a lower electric field than the memory unit 1 is formed thinner than the tunnel insulating film 25, the gate insulating film 29 is less likely to be thinned. According to the manufacturing method of the semiconductor device according to the first embodiment, the second groove 17 substantially perpendicular to the main surface of the semiconductor substrate 11 is formed by STI, and the second element isolation insulating film 22 is formed. width Lt ₂ by forming narrower than the width Lt ₁ of the first element isolation insulating film 23 can be further miniaturized logic cell 50a.

(Second Embodiment)
In the semiconductor device according to the second embodiment, as shown in FIG. 18, the first side wall made of a curved surface in which the first element isolation insulating film 38 is formed so that the width gradually decreases from the upper surface toward the lower surface. The semiconductor device according to the first embodiment is different from the semiconductor device according to the first embodiment in that the semiconductor device according to the first embodiment has a second side wall portion 231b that is continuous with the portion 231a and the first side wall portion 231a and is formed of a plane portion substantially perpendicular to the main surface of the semiconductor substrate 11. In the semiconductor device shown in FIG. 18, the width Lt ₁ of the top surface of the first element isolation insulating film 38 is wider than the width Lb ₁ of the bottom surface, as in the semiconductor device shown in FIG. In addition, in the cross section of FIG. 18, an angle α formed by the upper surface of the first element isolation insulating film 37, the main surface of the semiconductor substrate 11, and the first sidewall portion 231a is 90 degrees or less, preferably 70 to 78 degrees. In FIG. 18, the widths Lt ₁ and Lb ₁ are defined in a direction parallel to the cross section viewed from the AA direction in FIG. 1, but the widths Lt ₁ and Lb ₁ are defined in the BB direction in FIG. It is also possible to define parallel sections. Others are substantially the same as those of the semiconductor device according to the first embodiment, and thus description thereof is omitted.

In the semiconductor device according to the second embodiment, since the width Lt ₁ of the upper surface of the first element isolation insulating film 23 is wider than the width Lb ₁ of the lower surface, the tunnel insulating film 25 a disposed on the semiconductor substrate 11. Can be formed uniformly, and the yield and reliability can be improved.

  A method for manufacturing a semiconductor device according to the second embodiment will be described with reference to FIGS. The steps from sequentially depositing the first oxide film 12, the nitride film 13, and the second oxide film 14 on the semiconductor substrate 11 to expose a part of the semiconductor substrate 11 are the same as the steps shown in FIGS. Since there is, description is abbreviate | omitted.

  (A) A resist film 35 is applied on the logic part 2, and a part of the semiconductor substrate 11 of the memory part 1 is subjected to isotropic ion etching such as chemical dry etching (CDE) to obtain a curved surface as shown in FIG. The upper groove 36 whose groove width is gradually narrowed is formed by the first side wall portion 231a having a shape. Thereafter, the resist film 35 is removed. As shown in FIG. 20, the bottom surface of the upper groove 36 is anisotropically etched by RIE or the like, so that a second portion consisting of a flat portion that is continuous with the first side wall portion 231 a and substantially perpendicular to the main surface of the semiconductor substrate 11 is formed. A lower groove 37 having a side wall portion 231b is formed. The logic unit 2 uses RIE or the like so that the side wall of the second groove 17 is substantially vertical, that is, the side wall angle β viewed from the main surface of the semiconductor substrate 11 is 90 degrees or 80 to 90 degrees. Form.

  (B) As shown in FIG. 21, a third oxide film 21 of about 550 nm is deposited on the entire surface of the semiconductor substrate 11 and etched back by RIE or the like. The surface of the nitride film 13 is planarized by CMP or the like, and the first element isolation insulating film 23 is embedded in the upper groove 36 and the lower groove 37 of the memory unit 1 as shown in FIG. A second element isolation insulating film 22 is embedded in the second groove 17 of the logic unit 2. The subsequent steps are substantially the same as the steps shown in FIGS.

  According to the method of manufacturing a semiconductor device according to the second embodiment, when the first element isolation insulating film 38 of the memory unit 1 is formed by STI, as shown in FIG. An upper groove 36 whose groove width is gradually narrowed by 231a is formed in advance by isotropic ion etching. Then, a lower groove 37 having a planar second side wall portion 231b substantially perpendicular to the main surface of the semiconductor substrate 11 from the bottom surface of the upper groove 36 is formed by anisotropic ion etching. At this time, the second groove 17 of the logic unit 2 is also formed at the same time. As a result, even when a thick tunnel insulating film 25 is deposited on the semiconductor substrate 11 in contact with the upper groove 36, the generation of an oxygen-deficient region can be suppressed as compared with the case where a vertical STI buried insulating film is used. A tunnel insulating film 25 having a sufficient thickness can be deposited. Therefore, even when a high voltage is applied to the memory cell 40a of the memory unit 1, a semiconductor device with high yield and high reliability can be manufactured.

(Other embodiments)
Although the present invention has been described according to the above-described embodiments, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  The structure of the semiconductor device according to the first and second embodiments can be applied to an IC card 10 on which a semiconductor integrated circuit 100 including a nonvolatile memory 101 is mounted, for example, as shown in FIG. The semiconductor integrated circuit 100 includes a nonvolatile memory 101, a logic 102, a ROM 103, a RAM 104, a CPU 105, and an I / O unit 106. The IC card 10 may be a contact type IC card or a non-contact type IC card. When the IC card 10 is a non-contact IC card, an antenna unit that functions as the I / O unit 106 is disposed on the IC card 10 outside the semiconductor integrated circuit 100.

  The configuration of the semiconductor device shown in FIG. 3 and FIG. 18 is any of the I / O unit 106 for depositing an oxide film thicker than the gate insulating film 29b of the logic unit 2 and the semiconductor integrated circuit 100 on which the high voltage MOSFET unit is mounted. Of course, it is applicable.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

1 is a plan view showing an outline of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view showing the example of the semiconductor device according to the first embodiment of the present invention as seen from the AA direction in FIG. 1. 1 illustrates an example of a semiconductor device according to a first embodiment of the present invention, in which a memory unit 1 is a cross-sectional view as viewed from a BB direction in FIG. 1 and a logic unit 2 is a cross-sectional view as viewed from a CC direction in FIG. 1A and 1B show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which a memory section 1 is a process sectional view as seen from the BB direction of FIG. 1 and a logic section 2 is seen from the AA direction of FIG. 1A and 1B show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which a memory section 1 is a process sectional view as seen from the BB direction of FIG. 1 and a logic section 2 is seen from the AA direction of FIG. 1A and 1B show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which a memory section 1 is a process sectional view as seen from the BB direction of FIG. 1 and a logic section 2 is seen from the AA direction of FIG. 1A and 1B show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which a memory section 1 is a process sectional view as seen from the BB direction of FIG. 1 and a logic section 2 is seen from the AA direction of FIG. 1A and 1B show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which a memory section 1 is a process sectional view as seen from the BB direction of FIG. 1 and a logic section 2 is seen from the AA direction of FIG. 1A and 1B show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which a memory section 1 is a process sectional view as seen from the BB direction of FIG. 1 and a logic section 2 is seen from the AA direction of FIG. 1A and 1B show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which a memory section 1 is a process sectional view as seen from the BB direction of FIG. 1 and a logic section 2 is seen from the AA direction of FIG. 1A and 1B show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which a memory section 1 is a process sectional view as seen from the BB direction of FIG. 1 and a logic section 2 is seen from the AA direction of FIG. 1A and 1B show a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which a memory section 1 is a process sectional view as seen from the BB direction of FIG. 1 and a logic section 2 is seen from the AA direction of FIG. FIG. 3 is a process sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention, as viewed from the AA direction in FIG. 1. FIG. 3 is a process sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention, as viewed from the AA direction in FIG. 1. FIG. 3 is a process sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention, as viewed from the AA direction in FIG. 1. FIG. 3 is a process sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention, as viewed from the AA direction in FIG. 1. FIG. 3 is a process sectional view showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention, as viewed from the AA direction in FIG. 1. FIG. 4 is a cross-sectional view showing a semiconductor device according to a second embodiment of the present invention, as viewed from the AA direction in FIG. 1. FIG. 9 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention, as viewed from the AA direction in FIG. 1. FIG. 9 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention, as viewed from the AA direction in FIG. 1. FIG. 9 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention, as viewed from the AA direction in FIG. 1. FIG. 9 is a process cross-sectional view illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention, as viewed from the AA direction in FIG. 1. It is a block diagram which shows an example of an IC card suitable for the semiconductor device which concerns on embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Memory part 2 ... Logic part 11 ... Semiconductor substrate 17 ... 2nd groove | channel 20 ... 1st groove | channel 22 ... 2nd element isolation insulating film 23 ... 1st element isolation insulating film 25a ... Tunnel insulating film 26 ... Channel stop area | region 27a ... floating gate electrode 28a ... inter-gate insulating film 29b ... gate insulating film 30a ... first control gate electrode 30b ... second control gate electrode 31, 33 ... source region 32, 34 ... drain region 36 ... upper groove 37 ... lower groove 38 ... 1st element isolation insulating film 40a ... Memory cell 50a ... Logic cell 231a ... 1st side wall part 231b ... 2nd side wall part

Claims (5)

A semiconductor substrate having a memory portion and a logic portion arranged around the memory portion;
A first element isolation insulating film embedded in the memory unit and having a top surface width greater than a bottom surface width;
A second element isolation insulating film embedded in the logic portion, having a side wall substantially perpendicular to the main surface of the semiconductor substrate, and having a width smaller than the width of the upper surface of the first element isolation insulating film;
A tunnel insulating film disposed on the semiconductor substrate sandwiched between the first element isolation insulating films;
A floating gate electrode on the tunnel insulating film;
A first control gate electrode disposed on the floating gate electrode and insulated from the floating gate electrode;
A gate insulating film on the semiconductor substrate sandwiched between the second element isolation insulating films;
And a second control gate electrode on the gate insulating film.   The first element isolation insulating film is continuous with the first side wall portion and the first side wall portion formed of a curved surface so that the width gradually decreases from the upper surface toward the lower surface, and is substantially perpendicular to the main surface. The semiconductor device according to claim 1, further comprising a second side wall portion formed of a planar portion.   3. The semiconductor device according to claim 1, wherein a channel stop region is disposed in the semiconductor substrate under the first element isolation insulating film. Forming a first groove in the memory portion on the semiconductor substrate, the width of the opening being larger than the width of the bottom surface, and embedding the first element isolation insulating film in the first groove;
A second groove having a substantially vertical sidewall is formed in the logic portion arranged around the memory portion, the width of the opening being smaller than the width of the opening of the first groove, and the second groove. Embedding a second element isolation insulating film in the trench,
Forming a tunnel insulating film on the semiconductor substrate sandwiched between the first element isolation insulating films;
Forming a floating gate electrode on the tunnel insulating film;
Forming an intergate insulating film on the floating gate electrode;
Forming a first control gate electrode on the inter-gate insulating film;
Forming a gate insulating film on the semiconductor substrate sandwiched between the second element isolation insulating films;
Forming a second control gate electrode on the gate insulating film. A method for manufacturing a semiconductor device, comprising: Forming the first groove comprises:
Forming an upper groove in which the groove width is gradually narrowed by the curved first side wall portion;
The method of manufacturing a semiconductor device according to claim 4, further comprising: forming a lower groove having a planar second side wall portion substantially perpendicular to the main surface from the bottom surface of the upper groove.

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