KR20090070253A - Liquid crystal display device and driving method thereof - Google Patents

Abstract

A liquid crystal display device and a driving method thereof are provided to improving image quality by supplying a second gate voltage lower than a first gate voltage to a gate line. In liquid crystal display device and a driving method thereof, a gate driver supplies a first and a second voltage having a high level to a liquid panel. A data driver(40) supplies data voltage to the liquid crystal panel. The second gate voltage is lower than the first gate voltage. The second gate voltage is 40%-90% of the first gate voltage while the width of first gate voltage is more than at least 1/2 width of a first horizontal section.

Description

Liquid crystal display device and driving method

The present invention relates to a liquid crystal display device, in particular

Due to the development of the information society, display devices capable of displaying information have been actively developed. The display device includes a liquid crystal display device, an organic electro-luminescence display device, a plasma display panel, and a field emission display device.

Among these, the liquid crystal display device has advantages such as light weight, small size, low power consumption, and full color video, and is widely applied to mobile phones, navigation, monitors, and televisions.

The LCD displays an image corresponding to a video signal by adjusting the light transmittance of the liquid crystal cells on the liquid crystal panel.

1 is a view showing a liquid crystal panel of a conventional liquid crystal display device. For convenience of description, FIG. 1 illustrates one pixel area among a plurality of pixel areas defined in the liquid crystal panel.

The liquid crystal panel includes a first substrate, a second substrate, and a liquid crystal layer interposed between these substrates.

As illustrated in FIG. 1, the first substrate has a pixel area defined by a gate line GL and a data line DL.

The thin film transistor TFT is electrically connected to the gate line GL and the data line DL. The pixel electrode, not shown, is electrically connected to the thin film transistor TFT. The storage capacitance Cst is formed by the pixel electrode and the gate line of the front end. The liquid crystal capacitance Clc is formed in the liquid crystal layer interposed between the pixel electrode and the common electrode Vcom formed on the second substrate.

As shown in FIG. 2, a gate high voltage VGH and a gate low voltage VGL are supplied to the gate line GL. The thin film transistor TFT is turned on by the gate high voltage VGH, and the data voltage Vd supplied to the data line DL is charged to the storage capacitance Cst via the pixel electrode.

The gate high voltage VGH is supplied to the gate line GL for one horizontal period 1H, and the gate low voltage VGL is supplied after one horizontal substrate 1H.

In this case, when the gate high voltage VGH supplied to the gate line GL is transitioned to the gate low voltage VGL, the thin film transistor TFT is turned off and the pixel is instantaneously. The data voltage Vd charged in the electrode is dropped by the kickback voltage? Vp by the parasitic capacitance Cgs generated between the gate electrode and the source electrode of the thin film transistor TFT. This kickback voltage is greatly affected by the magnitude of the potential difference between the gate high voltage VGH and the gate low voltage VGL. Therefore, reducing the magnitude of the potential difference between the gate high voltage VGH and the gate low voltage VGL is essential to reduce the kickback voltage Vp.

In the conventional liquid crystal display, flicker and residual images are generated in the image displayed on the liquid crystal panel due to the kickback voltage (Vp), resulting in a problem of deterioration in image quality.

An object of the present invention is to provide a liquid crystal display device and a method of driving the same, which can improve the image quality by minimizing the kickback voltage by supplying the second gate high voltage lower than the first gate high voltage.

According to a first embodiment of the present invention, a liquid crystal display device includes: a liquid crystal panel; A gate driver spaced apart from each other and supplying the first and second gate voltages having a high level to the liquid crystal panel in units of one horizontal period; And a data driver for supplying a data voltage to the liquid crystal panel, wherein the second gate voltage may be at least lower than the first gate voltage.

According to a second exemplary embodiment of the present invention, a method of driving a liquid crystal display includes: supplying first and second gate voltages having a high level to a liquid crystal panel in units of one horizontal period; And supplying a data voltage to the liquid crystal panel, wherein the second gate voltage may be at least lower than the first gate voltage.

According to the present invention, the second gate voltage lower than the first gate voltage is supplied to the gate line to be spaced apart, thereby minimizing the kickback voltage and improving image quality.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

3 is a block diagram illustrating a liquid crystal display according to the present invention.

Referring to FIG. 3, the LCD includes a liquid crystal panel 50, a gate voltage generator 20, a gate driver 30, a data driver 40, and a timing controller 10.

The liquid crystal panel 50 includes a first substrate, a second substrate, and a liquid crystal layer interposed between the first and second substrates.

A plurality of gate lines GL0 to GLn and a plurality of data lines DL1 to DLm cross each other on the first substrate. Pixel regions may be defined by intersections of the gate lines GL0 to GLn and the data lines DL1 to DLm.

A thin film transistor TFT is connected to each of the gate lines GL0 to GLn and the data lines DL1 to DLm, and a pixel electrode is connected to the thin film transistor TFT. The thin film transistor TFT and the pixel electrode may be disposed in each pixel area. The storage capacitance Cst is formed by the overlap between the pixel electrode and the previous gate line. A liquid crystal capacitance Clc is formed by the liquid crystal layer between the pixel electrode and the common electrode to be described later.

The second substrate corresponds to each pixel area of the first substrate, and a color filter layer including a red color filter, a green color filter, and a blue color filter is disposed, and a black matrix is disposed between each color filter. A common electrode may be disposed on the black matrix.

The timing controller 10 generates control signals for controlling the gate driver 30 and the data driver 40. That is, the timing controller 10 controls a gate start pulse GSP, a first gate shift clock GSC1, a second gate shift clock GSC2, and a gate out enable GOE to control the gate driver 30. ), A level shifter control signal (LSC), and the like, and a source start pulse (SSP), a source shift clock (SSC), a source out enable (SOE), and a POL to control the data driver 40. do.

In the present embodiment, the gate start pulse GSP, the first gate shift clock GSC1, the second gate shift clock GSC2, the gate out enable GOE, and the like are generated to control the gate driver 30. The gate driver 30 generates a first gate voltage VGH1 and a second gate voltage VGH2 which is supplied to be spaced apart from the first gate voltage VGH1 by a level shifter control signal LSC. Supply to gate lines GL0 to GLn of 50 is performed.

The gate voltage generator 20 generates first to third gate voltages VGH1, VGH2, and VGL and supplies them to the gate driver 30.

The first gate voltage VGH1 is a voltage having a high level, and is a voltage capable of sufficiently activating each gate line GL0 to GLn of the liquid crystal panel 50.

The second gate voltage VGH2 is a voltage having a high level lower than the first gate voltage VGH1 and is a voltage capable of activating at least each gate line GL0 to GLn of the liquid crystal panel 50. The second gate voltage VGH2 may be lowered in a range of 40% to 90% relative to the first gate voltage VGH1.

The third gate voltage VGL is a voltage having a low level, and is a voltage capable of deactivating the gate lines GL0 to GLn of the liquid crystal panel 50.

The first to third gate voltages VGH1, VGH2, and VGL generated by the gate voltage generator 20 are supplied to the gate driver 30, and the first to third gate voltages are provided by the gate driver 30. Three gate voltages VGH1, VGH2, and VGL may be selectively supplied to the gate line of the liquid crystal panel 50.

As shown in FIG. 4, the gate driver 30 includes a shift register 32, an AND product 34, and a level shifter 36. The gate driver 30 may further include a buffer unit (not shown) that buffers the output of the level shifter 36.

The shift register 32 is controlled by the gate start pulse GSP and the first gate shift clock GSC1 to sequentially output the output signal Sout.

As shown in FIG. 6, the gate start pulse GSP has a high level only for one horizontal period 1H of one frame, and has a low level otherwise. That is, the gate start pulse GSP may have a high level only for one horizontal period 1H at the start of every frame.

The first gate shift clock GSC1 divides one horizontal period 1H into first and second periods, has a high level during the first period, and has a low level during the second period. The first and second sections may have the same width. The first gate shift clock GSC1 repeatedly has a high level and a low level in units of one horizontal period 1H.

Therefore, the gate start pulse GSP is output as the output signal Sout by the first gate shift clock GSC1.

The shift register 32 may output output signals as many as the number of gate lines of the liquid crystal panel 50.

The AND product 34 performs an AND operation on the output signal Sout, the gate out enable GOE, and the second gate shift clock GSC2 output from the shift register 32 to generate an output signal ORout. Output

As illustrated in FIG. 5, the AND product 34 may be an AND gate 38.

As illustrated in FIG. 6, the output signal Sout may have the same high barrel width as the gate start pulse GSP.

The gate out enable GOE may have a substantially high level during one horizontal period 1H, and may have a low level in some sections of the end of the one horizontal period 1H. That is, the gate out enable GOE may have a low level with a very narrow width in some sections between the one horizontal sections 1H.

The second gate shift clock GSC2 is the first high level signal having a high level for at least 1/2 or more of the 1 horizontal section 1H and the low level for at least 1/10 or less of the 1 horizontal section 1H. A first low level signal having a level, a second high level signal having a high level during at least one quarter or less of the first horizontal section 1H, and at least 1/100 of a first horizontal section 1H It may include a second low level signal having a low level during the interval of.

The AND gate 38 outputs an output signal ORout having a high level by a first high level signal, a gate out enable GOE, and an output signal Sout of the second gate shift clock GSC2. The output signal ORout having a low level is output by the first low level signal, the gate out enable GOE, and the output signal Sout of the second gate shift clock GSC2, and the second gate shift clock An output signal ORout having a high level is output by the second high level signal, the gate out enable GOE, and the output signal Sout of the GSC2, and a second low level of the second gate shift clock GSC2. The output signal ORout having a low level is output by the signal, the gate out enable GOE, and the output signal Sout.

Therefore, the output signal ORout output from the AND gate 38 is the same signal as the second gate shift clock GSC2.

The level shifter 36 receives the gate voltages corresponding to the output signal ORout output from the AND product 34 by the level shifter control signal LSC. The first to third gate voltages VGH1, VGH2, VGL) to output it.

The first to third gate voltages VGH1, VGH2, and VGL are generated by the gate voltage generator 20 and supplied to the level shifter 36 of the gate driver 30.

The level shifter 36 receives a level shifter control signal LSC from the timing controller 10. The level shifter control signal LSC may be a control signal for matching the output signal ORout output from the AND product 34 to the first to second gate voltages VGH1, VGH2, and VGL.

The level shifter control signal LSC may be composed of binary bits. Accordingly, the level shifter control signal LSC may be supplied to the level shifter 36 in the order of '00', '01', '10', and '11'.

When the level shifter control signal LSC is '00', the first gate voltage VGH1 corresponding to the output signal ORout of the first high level signal output from the AND product 34 is a level shifter Is output from 36).

When the level shifter control signal LSC is '01', the third gate voltage VGL corresponding to the output signal ORout of the first low level signal outputted from the AND product 34 is a level shifter. Is output from 36).

When the level shifter control signal LSC is '10', the second gate voltage VGH2 corresponding to the output signal ORout of the second high level signal output from the AND product 34 is a level shifter. It is output from 36.

When the level shifter control signal LSC is '11', the third gate voltage VGL corresponding to the output signal ORout of the second low level signal output from the AND product 34 is converted to the level shifter. It is outputted from (36).

Therefore, the gate driver 30 supplies the first and second gate voltages VGH1 and VGH2 to the gate lines GL0 to GLn of the liquid crystal panel 50. A third gate voltage VGL may be supplied between the first and second gate voltages VGH1 and VGH2.

The data driver 40 supplies a data voltage to the liquid crystal panel 50 according to control signals supplied from the timing controller 10.

Referring to FIG. 7, the first and second gate voltages VGH1 and VGH2 are generated by the gate driver 30 during one horizontal period 1H to generate a gate line of the liquid crystal panel 50. To supply. A third gate voltage VGL may be supplied between the first and second gate voltages VGH1 and VGH2. The first and second gate voltages VGH1 and VGH2 may have a high level, and the third gate voltage VGL may have a low level. The second gate voltage VGH2 may be lowered in a range of 40% to 90% of the first gate voltage VGH1.

First, the thin film transistor connected to the gate line of the liquid crystal panel 50 is turned on by the first gate voltage VGH1. Accordingly, the data voltage Vd is supplied from the data driver 40 to the data line of the liquid crystal panel 50. The data voltage Vd is applied to the pixel electrode via the thin film transistor connected to the data line. Since the storage capacitance Cst is formed in the pixel electrode, the data voltage applied to the pixel electrode is gradually charged in the storage capacitance Cst.

The third gate voltage VGL is supplied to the gate line of the liquid crystal panel 50 after the first gate voltage VGH1. Since the third gate voltage VGL is at a low level, the thin film transistor connected to the gate line is turned off. In this case, the first kickback voltage may be generated when the first gate voltage VGH1 transitions from the high level to the low level of the third gate voltage VGL. Since the width of the third gate voltage VGL is very small, the kickback voltage is not large. The kickback voltage decreases the voltage charged in the pixel electrode.

After the third gate voltage VGL, the second gate voltage VGH2 is supplied to the gate line of the liquid crystal panel 50. Accordingly, the thin film transistor connected to the gate line is turned on again by the second gate voltage VGH2 having a high level. Accordingly, the data voltage Vd supplied to the data line is applied again to the pixel electrode via the thin film transistor, so that the voltage of the pixel electrode is increased again. Therefore, the voltage of the pixel electrode can be completely charged with the data voltage Vd.

After the second gate voltage VGH2, the third gate voltage VGL is supplied to the gate line of the liquid crystal panel 50. Accordingly, the thin film transistor connected to the gate line is turned off.

Since the second gate voltage VGH2 has a voltage that is relatively lower than the first gate voltage VGH1, a transition occurs from the second gate voltage VGH2 to the third gate voltage VGL. Kickback voltage [Delta] Vp becomes very small.

Therefore, the present embodiment can improve the image quality by minimizing the kickback voltage by supplying the second gate voltage lower than the first gate voltage to the gate line.

1 is a view showing a liquid crystal panel of a conventional liquid crystal display device.

2 is a view showing generation of a kickback voltage in a conventional liquid crystal display.

3 is a block diagram showing a liquid crystal display device according to the present invention;

4 is a block diagram illustrating the gate driver of FIG. 3.

FIG. 5 illustrates the AND gate of FIG. 4. FIG.

6 is a signal waveform diagram of the liquid crystal display of FIG. 3.

7 is a view showing generation of a kickback voltage in the liquid crystal display of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: timing controller 20: gate voltage generator

30: gate driver 32: shift register

34: logical product operation unit 36: level shifter

38: AND gate 40: data driver

50: liquid crystal panel

Claims (11)

A liquid crystal panel; A gate driver spaced apart from each other and supplying the first and second gate voltages having a high level to the liquid crystal panel in a horizontal period unit; And A data driver for supplying a data voltage to the liquid crystal panel; And the second gate voltage is at least lower than the first gate voltage. The liquid crystal display of claim 1, wherein a third gate voltage having a low level is supplied between the first and second gate voltages. The liquid crystal display of claim 1, wherein the second gate voltage is low in a range of 40% to 90% of the first gate voltage. The liquid crystal display device according to claim 1, wherein the first gate voltage has a width of at least 1/2 of the one horizontal period. The liquid crystal display device according to claim 1, wherein the second gate voltage has a width of at least one quarter or less of the one horizontal period. 3. The liquid crystal display device according to claim 2, wherein the third gate voltage has a width of at least 1/10 or less of the one horizontal period. The method of claim 2, wherein the gate driver, A shift register for sequentially outputting an output signal of one horizontal period by the gate start pulse and the first gate shift clock; An AND operation unit for performing an AND operation on the output signal of the shift register, a gate out enable, and a second gate shift clock; And And a level shifter configured to select and output a gate voltage corresponding to an output signal of the logical product operator from among the first to gate voltages according to a level shifter control signal. 8. The liquid crystal display of claim 7, wherein the first gate shift clock has a high level for one half of the one horizontal period. 8. The method of claim 7, wherein the second gate shift clock includes first to third periods separated from the first horizontal period, wherein the first and third periods have a high level and the second period has a low level. It has a liquid crystal display device characterized by the above-mentioned. 10. The method of claim 9, wherein the first section has the same width as the first gate voltage, the second section has the same width as the third gate voltage, and the third section is the same as the second gate voltage. A liquid crystal display device having a width. Supplying the first and second gate voltages having a high level to the liquid crystal panel in units of one horizontal period; And Supplying a data voltage to the liquid crystal panel; And the second gate voltage is at least lower than the first gate voltage.

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