KR20090058634A - Method for forming gate of semiconductor device - Google Patents
Method for forming gate of semiconductor device Download PDFInfo
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- KR20090058634A KR20090058634A KR1020070125303A KR20070125303A KR20090058634A KR 20090058634 A KR20090058634 A KR 20090058634A KR 1020070125303 A KR1020070125303 A KR 1020070125303A KR 20070125303 A KR20070125303 A KR 20070125303A KR 20090058634 A KR20090058634 A KR 20090058634A
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- South Korea
- Prior art keywords
- film
- gate
- type region
- forming
- polysilicon
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 50
- 229920005591 polysilicon Polymers 0.000 claims abstract description 50
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000011156 evaluation Methods 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 229910021332 silicide Inorganic materials 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- MFRCZYUUKMFJQJ-UHFFFAOYSA-N 1,4-dioxane-2,5-dione;1,3-dioxan-2-one Chemical compound O=C1OCCCO1.O=C1COC(=O)CO1 MFRCZYUUKMFJQJ-UHFFFAOYSA-N 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 16
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 9
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 9
- 238000007689 inspection Methods 0.000 abstract description 2
- 101001027622 Homo sapiens Protein adenylyltransferase FICD Proteins 0.000 abstract 1
- 102100037689 Protein adenylyltransferase FICD Human genes 0.000 abstract 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 abstract 1
- 230000009977 dual effect Effects 0.000 description 9
- 239000002184 metal Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 5
- -1 BF2 ion Chemical class 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- MFOUDYKPLGXPGO-UHFFFAOYSA-N propachlor Chemical compound ClCC(=O)N(C(C)C)C1=CC=CC=C1 MFOUDYKPLGXPGO-UHFFFAOYSA-N 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate of a semiconductor device, and more particularly to a semiconductor device having a simplified single hardmask gate structure of a dual hardmask gate structure formed on a semiconductor substrate. It relates to a gate forming method.
The MOS transistor may be divided into an nMOS transistor and a pMOS transistor according to the type of channel. When the nMOS transistor and the pMOS transistor are formed on one semiconductor substrate, this is called a CMOS transistor.
Polysilicon has typically been used as the gate electrode of such MOS transistors, in which the polysilicon gate electrode is typically doped with either P + or N + to be suitable for doping of source and drain regions. However, as the size of the semiconductor device is reduced, there are various problems in using polysilicon as the gate electrode.
Polysilicon gates must be doped in high concentrations to become conductors close to the metal, with dopant solubility in the polysilicon gate limited to around 5x10 20 atoms / cm 3. Because dopant solubility limits the number of charge carriers in the polysilicon gate, a depletion layer is formed at the interface between the polysilicon gate and the gate dielectric layer when a voltage is applied to the gate electrode. The depletion region in the polysilicon gate increases the equivalent oxide thickness (EOT) of the transistor by at least about 4-5 mA, and thus acts as a factor for greatly reducing the driving current of the transistor.
On the other hand, silicon oxide film or silicon oxynitride film, which has been mainly used as a gate dielectric film, has encountered physical limitations in electrical properties as its thickness is reduced, and it is difficult to secure reliability of the gate dielectric film. For example, when the thickness of the silicon oxide film is lowered to 20 kΩ or less, the gate leakage current increases by direct tunneling, and power consumption also increases. Therefore, when the gate dielectric film is formed of a silicon oxide film or a silicon oxynitride film, there is a limit in decreasing the thickness thereof.
In order to overcome this problem, it is possible to replace the existing silicon oxide film or silicon oxynitride film, and has a high equivalent oxide film thickness (EOT) and high dielectric constant (high-k) that can reduce the leakage current between the gate electrode and the channel region. The research on the dielectric film of) is being actively conducted.
However, according to the MOS transistor formed of a high dielectric constant gate dielectric film and a polysilicon gate electrode, defect states and a large number of bulk traps at the interface between the semiconductor substrate and the gate dielectric film are caused by conduction. By capturing the contributing electrons, the Fermi level is pinned to the center of the energy band located at or near the charge neutral level, thereby increasing the threshold voltage (Vth) significantly. Occurs.
The depletion effect and Fermi level fixation phenomenon of the polysilicon gate electrode as described above are more severe in the pMOS transistor, especially in the case of the pMOS transistor, dopants, i.e., boron (B), from the P + doped polysilicon gate electrode By penetrating through the channel region of the semiconductor substrate, problems such as changing the flat band voltage (Vfb) and the threshold voltage and lowering the reliability of the device also occur.
Accordingly, there is a strong demand to change the gate electrode material from polysilicon to a metallic material. Since the metallic material has an infinite carrier amount (5 × 10 22 atoms / cm 3), the thickness of the depletion region becomes substantially zero. Therefore, there is an advantage that the polysilicon gate can be replaced with a metal gate to eliminate the polysilicon depletion effect and the Fermi level fixation phenomenon. However, metal gates have various process problems such as thermal stability and compatibility with existing processes.
Accordingly, a metal / polysilicon gate stack structure in which a metal gate is inserted between the gate dielectric film and the polysilicon gate has been proposed. According to the metal / polysilicon gate stack structure, the polysilicon depletion effect and the Fermi level fixation phenomenon can be suppressed while maintaining compatibility with the existing process.
The work function of the metal gate determines the threshold voltage of the MOS transistor along with the doping level of the substrate. Thus, in a CMOS device where both nMOS transistors and pMOS transistors require low threshold voltages of about 0.3 to 0.6 V, the metal gate material has a work function of about 4.0 to 4.4 eV for the nMOS transistor and about 4.8 to 5.2 eV for the pMOS transistor. Must have a work function of.
1 is a cross-sectional view of a semiconductor device having a dual gate in the related art.
Referring to FIG. 1, a method of manufacturing a dual gate of a semiconductor device, although not shown first, has a semiconductor substrate having a first region (NMOS) in which an NMOS transistor is formed and a second region (PMOS) in which a PMOS transistor is formed. An isolation layer is formed on (100) to define the active region. Next, a p-type well region and an n-type well region are formed in the first region NMOS and the second region PMOS by performing a normal well forming process. Next, a
A
Next, a
In addition, a gate pattern including the
However, it is difficult to control variation of final inspection critical dimensions (FICD) during the gate process due to the adoption of dual hard masks, which causes a problem in that the distribution of gate-related resistance on the product increases. In addition, when the etching is performed in two steps during the subsequent etching process, the contact etch is adopted to increase the variation of the contact Rc for each section and device, thereby adversely affecting the product.
Therefore, in the present invention, instead of the dual hard mask made of silicon nitride film and PE-TEOS, it is formed as a single hard mask on which PE-TEOS is deposited by optimizing through thickness evaluation, thereby making it easier to control the variation of FICD during the gate process and more stable. It is an object of the present invention to provide a method for forming a gate of a semiconductor device capable of implementing process management.
In order to achieve the above object, the present invention provides a method for forming a semiconductor device, comprising forming an isolation layer, an N-type region, and a P-type region on a semiconductor substrate, and forming a gate insulating film and a polysilicon layer over the entire semiconductor substrate. Forming a first photoresist pattern on the P-type region, implanting P-type impurities into the polysilicon film of the N-type region using the first photoresist pattern as a mask, and forming a second photoresist on the N-type region. Forming a pattern and implanting N-type impurities into the polysilicon film in the P-type region using the second photosensitive film pattern as a mask; forming a Custon silicide (WSix) film over the entire polysilicon film; Forming a hard mask film made of PE-TEOS on the (WSix) film, and patterning the stacked polysilicon film, the Bexton silicide (WSix) film, and the hard mask film to form an N-type A method of forming a gate of a semiconductor device, the method comprising forming a single gate electrode on a region and an upper portion of a P-type region, respectively.
Here, preferably, the polysilicon film is formed to a thickness of 1400 kPa to 1600 kPa, and the Maxon silicide (WSix) film is formed to a thickness of 1100 kPa to 1300 kPa.
More preferably, the hard mask film is formed to an optimized thickness of 900 kPa to 1100 kPa through thickness evaluation.
As described above, according to the gate forming method of the semiconductor device of the present invention, it is possible to control the variation of FICD during the gate process easily by implementing a single hard mask of PE-TEOS deposited by optimization through thickness evaluation, and to implement more stable process management. Has the possible effect.
Hereinafter, the operating principle of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, when it is determined that a detailed description of a known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are terms defined in consideration of functions in the present invention, and may be changed according to intentions or customs of users or operators. Therefore, the definition should be made based on the contents throughout the specification.
2A through 2F are cross-sectional views illustrating a method of forming a gate of a semiconductor device in accordance with an embodiment of the present invention.
As shown in FIG. 2A, an N-
Subsequently, the
The
When the
More preferably, it is formed in the thickness of 1400 kPa-1600 kPa.
Referring to FIG. 2B, the first
It is preferable that P type impurity is 11B ion or BF2 ion. In addition, the 11B ion is preferably implanted to have a dose of 1E15 to 5E15 / cm2 at an ion energy of 3 to 5 KeV, and the BF2 ion is implanted to have a dose of 1E15 to 5E15 / cm2 at an ion energy of 10 to 22 KeV. It is preferable.
Referring to FIG. 2C, the second
It is preferable that N type impurity is 31P ion. In addition, it is preferable to inject 31P ions to have a dose of 1E15 to 5E15 / cm 2 at an ion energy of 10 to 15 KeV.
Referring to FIG. 2D, a tungsten silicide layer (WSix) 200 is formed on the entire surface.
Preferably, the tungsten silicide film (WSix) 200 is formed to a thickness of 1100 kPa to 1300 kPa.
Referring to FIG. 2E, the
Referring to FIG. 2F, a
Subsequently, after forming a photoresist pattern for forming an N-type gate electrode on the P-
Therefore, in the present invention, the problem that occurs in the conventional dual hard mask film, that is, it is difficult to control the fluctuation of the FICD during the process, or the process management was difficult by two etchings during the contact etching process of a single hard mask made of PE-TOES Formation solves the above problems and enables more stable process management.
As described above, the method for forming a gate of a semiconductor device according to the present invention is just one preferred embodiment, and the present invention is not limited to the above-described embodiment, and the scope of the present invention is as claimed in the following claims. Without departing from the technical spirit of the present invention to the extent that any person of ordinary skill in the art to which the present invention pertains various modifications can be made.
1 is a cross-sectional view of a conventional semiconductor device having a dual gate,
2A through 2F are cross-sectional views illustrating a method of forming a gate of a semiconductor device in accordance with an embodiment of the present invention.
<Description of the symbols for the main parts of the drawings>
100
120: N-type region 130: P-type region
140: gate insulating film 150: polysilicon film
160 and 170: first and second photoresist layer patterns 200: a texon silicide (WSix) layer
210: hard mask film 230: P-type gate electrode
240: N-type gate electrode
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070125303A KR20090058634A (en) | 2007-12-05 | 2007-12-05 | Method for forming gate of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020070125303A KR20090058634A (en) | 2007-12-05 | 2007-12-05 | Method for forming gate of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20090058634A true KR20090058634A (en) | 2009-06-10 |
Family
ID=40988977
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020070125303A KR20090058634A (en) | 2007-12-05 | 2007-12-05 | Method for forming gate of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20090058634A (en) |
-
2007
- 2007-12-05 KR KR1020070125303A patent/KR20090058634A/en not_active Application Discontinuation
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