KR20090057934A - Method for manufacturing soi substrate - Google Patents

Abstract

A method for manufacturing a SOI substrate is provided to prevent reuse of a substrate for exfoliation by using the SOI for exfoliation. A second substrate(111) is made of the same material as a first substrate(101), and a second mono-crystalline semiconductor layer(154) is formed on a first mono-crystalline semiconductor film(103). A peeling layer(105) is formed on the second mono-crystalline semiconductor film, and a second insulating layer is formed on the second mono-crystalline semiconductor film. The surface of the second insulating layer is welded into the surface of the second substrate, and a glass substrates is used as the first substrate and the second substrate.

Description

Manufacturing method of SOI substrate {METHOD FOR MANUFACTURING SOI SUBSTRATE}

The present invention relates to a method for manufacturing a silicon on insulator (SOI) substrate and a method for manufacturing a semiconductor device.

In recent years, integrated circuits using a silicon on insulator (SOI) substrate in which a thin single crystal semiconductor film exists on an insulating surface instead of a bulk silicon wafer have been developed. Since the parasitic capacitance between the drain of a transistor and a board | substrate is reduced by using an SOI board | substrate, an SOI board | substrate attracts attention as improving the performance of a semiconductor integrated circuit.

As a method of manufacturing an SOI substrate, the smart cut (registered trademark) method is known (for example, refer patent document 1). The outline | summary of the manufacturing method of the SOI board | substrate by a smart cut method is demonstrated below. First, an ion implantation layer is formed at a predetermined depth from the surface by implanting hydrogen ions into the silicon wafer serving as the substrate for peeling using an ion implantation method. Next, the silicon wafer implanted with hydrogen ions is bonded to a separate (peelable) silicon wafer through a silicon oxide film. Subsequently, by performing heat treatment, the ion implantation layer becomes a cleaved surface, the peeling silicon wafer in which the hydrogen ions are implanted is peeled in a thin film, and a single crystal silicon film is formed on the bonded silicon wafer. can do. In addition, the smart cut method may be called a hydrogen ion implantation peeling method.

Moreover, the method of forming a single crystal silicon layer on the support substrate which consists of glass using this smart cut method is proposed (for example, refer patent document 2).

In addition, in the smart cut method, a method of repeatedly reused by polishing a silicon wafer which is a substrate for peeling after cleavage is proposed (see Patent Document 3, for example).

[Patent Document 1] Japanese Patent Application Laid-Open No. 2000-124092

[Patent Document 2] Japanese Patent Application Laid-Open No. 11-163363

[Patent Document 3] Japanese Patent Application Laid-Open No. 2007-251129

Since a glass substrate can be made larger in area than a silicon wafer and is a cheap board | substrate, it is mainly used for manufacture of a liquid crystal display device. By using a glass substrate as a base substrate (substrate for peeling), a large-area and inexpensive SOI substrate can be produced. In this case, in order to form a single crystal semiconductor film on a glass substrate using the smart cut method, after bonding a silicon wafer as a peeling substrate and a glass substrate as a peeling substrate, a portion of the silicon wafer is left on the glass substrate. The wafer needs to be separated.

However, when the characteristics (thermal expansion coefficient, curvature amount, etc.) of a peeling board | substrate and a to-be-peeled board | substrate differ, there exists a possibility that a bonding defect may arise by heat processing etc. which are performed after joining. In particular, when using a substrate other than a semiconductor substrate (for example, a glass substrate) as the substrate to be peeled off, since the materials of the substrates are different, bonding failures are likely to occur.

In addition, when using (reusing) the same peeling substrate repeatedly, since the heat processing process etc. are performed repeatedly, the quality of a peeling substrate falls and the quality of the SOI board | substrate manufactured using the said peeling substrate is carried out. This may fall. Therefore, there is a fear that a remarkable difference may occur between the quality of the first SOI substrate fabricated with one silicon wafer and the last SOI substrate fabricated. In addition, when trying to fabricate as many SOI substrates as possible using one silicon wafer, the thickness of the substrate becomes smaller as it is reused, and thus, the probability that the peeling substrate may be broken or a bonding failure may occur in the manufacturing process. There is a risk of becoming high.

In view of the above-described problems, the present invention is one of the objectives of reducing the bonding failure when producing an SOI substrate composed of a substrate made of an insulator. Or when producing a some SOI board | substrate, it is made as an objective to suppress the damage of a peeling board | substrate, and to reduce the difference of the quality between some SOI board | substrates.

The present invention fabricates a second SOI substrate having a single crystal semiconductor film formed through an insulating film on a second substrate formed of the same material as the first substrate using a first SOI substrate having a single crystal semiconductor film formed through an insulating film over the first substrate. .

One method of manufacturing the SOI substrate of the present invention is to prepare a first SOI substrate having a first single crystal semiconductor film formed thereon through a first insulating film on a first substrate made of an insulator, and a second substrate formed of the same material as the first substrate. A second single crystal semiconductor film is formed on the first single crystal semiconductor film, ions are added to the second single crystal semiconductor film to form a release layer, a second insulating film is formed on the second single crystal semiconductor film, and the surface of the first SOI substrate is formed. And the surface of the second substrate are opposed to each other, the surface of the second insulating film and the surface of the second substrate are bonded to each other, and subjected to heat treatment, thereby cleaving at the boundary of the release layer, and forming a second through the second insulating film on the second substrate. A second SOI substrate on which a part of the single crystal semiconductor film is formed is formed.

One of the manufacturing methods of the SOI substrate of this invention is the same material as the 1st board | substrate which consists of a semiconductor substrate in which the 1st insulating film was formed in the surface, and the 1st peeling layer was formed in the predetermined depth, the insulator, and the 1st board | substrate. Preparing a second substrate, the surface of the semiconductor substrate and the surface of the first substrate are opposed to each other, the surface of the first insulating film and the surface of the first substrate are bonded to each other, and the heat treatment is performed so that the first release layer is bounded. To form a first SOI substrate having a first single crystal semiconductor film formed thereon on the first substrate through a first insulating film, a second single crystal semiconductor film formed on the first single crystal semiconductor film, and adding ions to the second single crystal semiconductor film. To form a second release layer, to form a second insulating film on the second single crystal semiconductor film, to oppose the surface of the first SOI substrate and the surface of the second substrate, and the surface of the second insulating film and the second The surface of the plate is bonded to each other, and the heat treatment is performed to cleave the second release layer as a boundary, and form a second SOI substrate having a portion of the second single crystal semiconductor film formed on the second substrate via the second insulating film. It is done.

One of the steps for producing the SOI substrate of the present invention is a method for producing an SOI substrate having a first step and a second step, wherein the first step is a first single crystal semiconductor film formed on a first substrate made of an insulator through a first insulating film. A first SOI substrate formed and a second substrate formed of the same material as the first substrate are prepared, a second single crystal semiconductor film is formed on the first single crystal semiconductor film, and ions are added to the second single crystal semiconductor film to form a release layer. And forming a second insulating film on the second single crystal semiconductor film, and the second step opposes the surface of the first SOI substrate and the surface of the second substrate, and the surface of the second insulating film and the surface of the second substrate. By bonding and heat-processing, the hole which cleaves with the peeling layer as a boundary and forms the 2nd SOI substrate in which one part of the 2nd single crystal semiconductor film was formed on the 2nd board | substrate through the 2nd insulating film is formed. It is characterized by using the second SOI substrate formed in the second step as a first SOI substrate in the first step.

In addition, in this specification, a semiconductor device refers to the whole apparatus which can function by using a semiconductor characteristic, and an electro-optical device, a semiconductor circuit, and an electronic device are all contained in a semiconductor device.

In addition, in this specification, a display apparatus includes a light emitting device or a liquid crystal display device. The light emitting device includes a light emitting element, and the liquid crystal display includes a liquid crystal element. The light emitting device includes, in its category, an element whose luminance is controlled in accordance with a current or a voltage. Specifically, an inorganic EL (Electro Luminescence) device and an organic EL device are included.

According to this invention, even when producing the SOI board | substrate comprised from the board | substrate which consists of an insulator, joining defect can be reduced. In addition, even when a plurality of SOI substrates are produced, breakage of the peeling substrate can be suppressed and the difference in quality between the plurality of SOI substrates can be reduced.

EMBODIMENT OF THE INVENTION Below, embodiment of this invention is described based on drawing. However, it can be easily understood by those skilled in the art that the present invention can be embodied in many different forms, and that the form and details of the present invention can be variously changed without departing from the spirit and scope of the present invention. Therefore, this invention is not limited to description of the following embodiment. In addition, in all the drawings for demonstrating embodiment, the same code | symbol is attached | subjected to the same part or the part which has the same function, and the repeated description is abbreviate | omitted.

(Embodiment 1)

In this embodiment, an example of the manufacturing method of the SOI substrate of this invention is demonstrated with reference to drawings.

First, the first SOI substrate 100 is prepared (see FIG. 1A-1).

The first SOI substrate 100 may be formed by forming the first single crystal semiconductor film 103 on the first substrate 101 through the insulating film 102. Here, the 1st SOI substrate 100 becomes a peeling substrate.

The first substrate 101 uses a substrate made of an insulator. Specifically, as the first substrate 101, a glass substrate used for the electronic industry such as aluminosilicate glass, alumino borosilicate glass, barium borosilicate glass is used. In addition, a plastic substrate having heat resistance that can withstand the processing temperature of the present step and having an insulating film (for example, a silicon oxide film or a silicon oxynitride film) formed on the surface can be used. As the first substrate 101, a large area can be increased, and a low cost glass substrate or a plastic substrate can be used, whereby the cost can be reduced compared to the case where a silicon wafer is used. In other words, in the present embodiment, a substrate (non-semiconductor substrate) other than a semiconductor substrate such as a silicon wafer is used as the first substrate 101.

As the insulating film 102, a single layer such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, or the like and a stacked film thereof may be used. In addition, silicon oxynitride has a content of oxygen more than nitrogen as its composition, and preferably, using Rutherford Backscattering Spectrometry (RBS) and Hydrogen Forward Scattering (HFS) When measured, the concentration ranges from 50 at.% To 70 at.% Of oxygen, 0.5 at.% To 15 at.% Of nitrogen, 25 at. To 35 at.% Of silicon and 0.1 to 10 at.% Of hydrogen. Pointer to what is included in the range. In addition, silicon nitride oxide is a composition whose content of nitrogen is larger than oxygen, Preferably when it measures using RBS and HFS, it is 5at.%-30at.% Of oxygen as a concentration range, and 20at of nitrogen. .% To 55 at%, silicon at 25 at% to 35 at%, hydrogen at 10 at% to 30 at%. However, when the total amount of atoms constituting silicon oxynitride or silicon oxynitride is 100 at%, the content ratio of nitrogen, oxygen, silicon and hydrogen is included in the above range.

The first single crystal semiconductor film 103 can be formed of a single crystal silicon film or the like. It is preferable to form a film thickness in 20 nm-250 nm. In addition, in this specification, "monocrystal" refers to a crystal in which the crystal plane coincides with the crystal axis, and indicates that the atoms or molecules constituting it are arranged in a spatially regular manner. However, single crystals are constituted by regularly arranging atoms, but include those having a lattice defect in which some of the arrangements are disturbed, and those having intentional or unintentional lattice distortion.

Next, a semiconductor film 104 is formed over the first single crystal semiconductor film 103 of the first SOI substrate 100 (see Fig. 1A-2).

The semiconductor film 104 can form a silicon film between 20 nm and 250 nm by using a CVD method or the like. In this embodiment, an amorphous semiconductor film (for example, amorphous silicon) is formed on the first single crystal semiconductor film 103 at 20 nm to 250 nm. The film thickness of the semiconductor film 104 may be appropriately set in accordance with the film thickness of the first single crystal semiconductor film 103. For example, when the first single crystal semiconductor film 103 has a film thickness required in a subsequent peeling step, the semiconductor film 104 may not be formed.

Next, heat treatment is performed to epitaxially grow (solid growth) and crystallize the semiconductor film 104 formed on the first single crystal semiconductor film 103 (see Fig. 1A-3). As a result, a second single crystal semiconductor film 154 is formed over the first single crystal semiconductor film 103.

The heat treatment can be used in a heating furnace, laser irradiation, RTA (Rapid Thermal Annealing) or a combination thereof. Here, after the semiconductor film 104 is formed on the first single crystal semiconductor film 103, the semiconductor film 104 is crystallized by performing 5 sec to 180 sec heat treatment at 500 ° C to 800 ° C by RTA.

Next, a release layer 105 is formed in a region of a predetermined depth from the surface of the second single crystal semiconductor film 154, and an insulating film 106 is formed on the second single crystal semiconductor film 154 (see FIGS. 1A-4). ).

The release layer 105 can be formed by irradiating an ion beam 107 made of ions accelerated by an electric field and adding ions to a region of a predetermined depth from the surface of the second single crystal semiconductor film 154. The ion beam 107 is generated by exciting the source gas to generate a plasma of the source gas, and extracting ions contained in the plasma by the action of an electric field from the plasma.

The depth of the region where the release layer 105 is formed can be adjusted according to the acceleration energy and the incident angle of the ion beam 107. Acceleration energy can be adjusted by acceleration voltage, dose amount, and the like. The exfoliation layer 105 is formed in a region approximately the same depth as the average penetration depth of the ions. Depending on the depth at which ions are added, the thickness of the semiconductor film separated from the second single crystal semiconductor film 154 crystallized in a later step is determined. The depth at which the release layer 105 is formed is 10 nm or more and 500 nm or less, and the range of preferable depth is 50 nm or more and 200 nm or less.

For the addition of ions, an ion doping method without mass separation or an ion implantation method with mass separation can be used.

Although source gas used at the time of addition of an ion has hydrogen gas, a rare gas, etc., in this embodiment, it is preferable to use hydrogen gas. When hydrogen gas is used in the ion doping method, the generated ionic species is H ⁺ , H ₂ ^+, and H ₃ ^+, but it is preferable that H ₃ ⁺ is most injected. H ₃ ⁺ is a good injection efficiency of the ions than H ^+, H ₂ ^+, it is possible to shorten the infusion time. In addition, in a subsequent process, a crack arises easily in a peeling layer.

In addition, it is preferable to form an insulating film on the second single crystal semiconductor film 154 before adding ions. By forming the insulating film, it is possible to prevent impurities from adhering to the surface of the second single crystal semiconductor film 154 due to the addition of ions and to prevent the surface from being etched. As the insulating film, a single layer such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film or the like, or a film in which these layers are stacked can be used. In this case, these insulating films are formed below the insulating film 106. In addition, after the insulating film 106 is formed, ions may be added.

The insulating film 106 functions as a layer (bonding layer) to be bonded to the substrate to be peeled, and can be formed of a silicon oxide film or a silicon oxynitride film by a CVD method, a sputtering method, or the like. In addition, since the insulating film 106 functions as a bonding layer, the surface is preferably flat. Here, the silicon oxide layer formed by the CVD method which used organic silane for raw material gas is formed. In addition, the silicon oxide layer or the silicon oxynitride layer formed by CVD method which uses silane as a raw material gas can also be applied.

In addition, in this embodiment, although the peeling layer 105 is formed in the 2nd single crystal semiconductor film 154, the film thickness of the 1st single crystal semiconductor film 103 is larger than the 2nd single crystal semiconductor film 154. In addition, in FIG. In the case of being thick, the release layer 105 may be formed in the first single crystal semiconductor film 103.

Next, the second substrate 111 is prepared (see FIG. 1B).

As the 2nd board | substrate 111, the board | substrate which consists of a material similar to the 1st board | substrate 101 which comprises the 1st SOI board | substrate 100 of a peeling board | substrate is used. For example, a glass substrate can be used as the first substrate 101 and the second substrate 111. In addition, the 2nd board | substrate 111 becomes a to-be-peeled substrate here.

By using a substrate made of the same material as the first substrate 101 as the second substrate 111, even when the heat treatment is performed after joining the first SOI substrate 100 and the second substrate 111, the respective substrates are used. The difference in thermal expansion and shrinkage of the substrate before and after the heat treatment can be reduced. As a result, bonding failure can be suppressed.

Next, the surface of the first SOI substrate 100 and the surface of the second substrate 111 are opposed to each other, and the surface of the insulating film 106 serving as the bonding layer and the surface of the second substrate 111 are bonded to each other (FIG. 1C). Reference). In this bonding, van der Waal's forces are applied, and the hydrogen bonding is performed using Si-H, Si-OH, or the like as a bonding species by bringing the first SOI substrate 100 and the second substrate 111 into close contact with each other. It is possible to form a firm bond by.

In addition, it is preferable to perform megasonic cleaning, megasonic cleaning, and ozone water cleaning on the bonding surface before bonding the first SOI substrate 100 and the second substrate 111. By performing these processes, dust, such as an organic substance of a joining surface, can be removed and a surface can be made hydrophilic.

Subsequently, a heat treatment is performed to separate (clog) the release layer 105 so that a portion of the third single crystal semiconductor film 113 (the second single crystal semiconductor film 154) is formed on the second substrate 111 through the insulating film 106. ) (See FIG. 1D). Here, by performing a heat treatment at 400 ° C to 700 ° C, the volume change of the microcavity occurs in the ions (for example, hydrogen ions) included in the release layer 105, and the release layer 105 is removed. Thus cleavage. As a result, the third single crystal semiconductor film 113 is formed on the second substrate 111 through the insulating film 106, and the second single crystal semiconductor film 154 that does not peel off remains on the first substrate 101.

By the above process, the second SOI substrate 110 having the third single crystal semiconductor film 113 formed on the second substrate 111 through the insulating film 106 can be formed. The 2nd SOI substrate 110 can be used as a peeling substrate in the said FIG. 1A-1.

As described above, by using the SOI substrate as the peeling substrate and using the substrate made of the same material as the substrate constituting the SOI substrate of the peeling substrate as the peeled substrate, an SOI substrate composed of a substrate other than the semiconductor substrate is produced. Even if it does, a poor bonding can be reduced. Moreover, the throughput can be improved in the mass production process of several SOI substrates by using the 2nd SOI substrate 110 formed using the 2nd substrate 111 which is a to-be-peeled substrate as a peeling substrate.

In the above step, the surface of the first SOI substrate 100 ′ and the second SOI substrate 110 after peeling may be planarized (see FIG. 1E). By performing the flattening treatment, even if unevenness occurs on the surfaces of the second single crystal semiconductor film 154 and the third single crystal semiconductor film 113 after peeling, the surface can be flattened.

As a planarization process, it can carry out by CMP (Chemical Mechanical Polishing), an etching process, irradiation of a laser beam, etc. Here, after performing the etching process (etchback process) which combined one or both of dry etching or wet etching, laser beam is irradiated, and recrystallization of a single crystal semiconductor film and planarization of a surface are performed. In the planarization treatment of the first SOI substrate 100, the second single crystal semiconductor film 154 may be removed to expose the first single crystal semiconductor film 103.

The upper surface of the single crystal semiconductor film can be melted by irradiating laser light from the upper surface side of the single crystal semiconductor film. After melting, the single crystal semiconductor film is cooled and solidified, whereby a single crystal semiconductor film having improved flatness on its upper surface can be obtained. By using the laser light, since the first substrate 101 or the second substrate 111 is not directly heated, it is possible to suppress the temperature rise of the first substrate 101 or the second substrate 111. Therefore, a low heat resistance substrate such as a glass substrate can be used for the first substrate 101 or the second substrate 111.

In addition, the melting of the single crystal semiconductor film by laser light irradiation is preferably partial melting. This is because, in the case of complete melting, microcrystallization is caused by disordered nucleation after becoming liquid phase and crystallinity is likely to decrease. On the other hand, by partial melting, crystal growth advances from the solid phase part which is not melted. As a result, defects in the semiconductor film can be reduced. Herein, complete melting means that the single crystal semiconductor film is melted to the vicinity of the lower interface to be in a liquid state. On the other hand, in this case, the partial melting means that the upper part of the single crystal semiconductor film melts to become a liquid phase, but the lower part does not melt but indicates a solid state.

It is preferable to use a pulse oscillation laser for irradiation of the said laser light. This is because it is possible to oscillate high-energy pulsed laser light instantaneously and to easily generate a partial melting state. The oscillation frequency is preferably about 1 Hz or more and about 10 MHz or less.

As above-mentioned, after irradiating a laser beam, you may perform the thinning process which makes the film thickness of a single crystal semiconductor film small. What is necessary is just to apply the etching process (etchback process) which combined one or both of dry etching or wet etching to thin film of a single crystal semiconductor film. For example, when the single crystal semiconductor film is a layer made of a silicon material, SF ₆ and O ₂ can be used as the process gas as the dry etching to thin the single crystal semiconductor film.

In addition, the manufacturing method of the SOI board | substrate shown by this embodiment can be performed in appropriate combination with the manufacturing method shown by other embodiment of this specification.

(Embodiment 2)

In this embodiment, the manufacturing method of a some SOI board | substrate, and the usage method of a board | substrate are demonstrated with reference to drawings.

First, after preparing a first SOI substrate 100 and a second substrate 111 to be a peeling substrate, and forming a second single crystal semiconductor film 154 on the first SOI substrate 100, the second The exfoliation layer 105 is formed on the single crystal semiconductor film 154, and the insulating film 106 is formed on the second single crystal semiconductor film 154 (Figs. 2A-1 to 2A-4, Fig. 2B, hereinafter referred to as “process A ". In addition, the process to FIGS. 2A-1 to 2B may be performed similarly to the said FIGS. 1A-1 to 1B.

Next, after the surface of the insulating film 106 functioning as the bonding layer and the surface of the second substrate 111 are bonded together, heat treatment is performed, and then cleaved with the release layer 105 as a boundary, thereby over the second substrate 111. After the third single crystal semiconductor film 113 is formed through the insulating film 106, planarization is performed on the surfaces of the first SOI substrate 100 ′ and the second SOI substrate 110 after peeling (FIGS. 2C to 2). 2e, hereinafter referred to as "step B"). 2C to 2E may be performed in the same manner as in FIGS. 1C to 1E.

Thereafter, the new SOI substrate is produced by using the second SOI substrate 110 formed in the step B as the first SOI substrate 100 for peeling in the step A. FIG. In addition, semiconductor elements, such as a transistor, are manufactured using the 1st SOI substrate 100 'after peeling in process B. FIG. In this case, the second substrate 111, the insulating film 106, and the third single crystal semiconductor film 113 of the second SOI substrate 110 formed in step B include the first SOI substrate 100 in step A. Correspond to the first substrate 101, the insulating film 102, and the first single crystal semiconductor film 103, respectively. In addition, in the process B, when the surface of the 1st SOI substrate 100 'and the 2nd SOI substrate 110 after peeling are flat, planarization process (refer FIG. 2E) may be abbreviate | omitted.

That is, in this embodiment, the SOI substrate newly manufactured using the SOI substrate for peeling is used as a SOI substrate for peeling once, and the SOI substrate used as a SOI substrate for peeling is used for semiconductor element formation, such as a transistor. It is used as an SOI substrate.

By producing the SOI substrate using the method shown in FIGS. 2A-1 to 2E-2, the peeling substrate does not need to be reused repeatedly over several times. As a result, the fall of the quality of the board | substrate for peeling based on heat processing etc. which are repeatedly performed to a board | substrate for peeling can be suppressed. In addition, damage due to thinning of the peeling substrate can be prevented. In addition, by using the newly manufactured SOI substrate once as a peeling substrate and then using it as a substrate for forming a semiconductor element, when producing a plurality of SOI substrates, the difference in quality between the plurality of SOI substrates can be reduced. have.

In particular, when a glass substrate having a low heat resistance or the like is used as the substrate for peeling, by repeatedly reusing the substrate for peeling several times, heat treatment may be performed a plurality of times, and there is a fear that bonding failure due to a change in the characteristics of the substrate may occur. However, if it is used several times (preferably No. 1) as a board | substrate for peeling, the bonding defect by the change of the characteristic of a board | substrate can be reduced.

2A-1 to 2E-2, when the newly manufactured SOI substrate (second SOI substrate 110) is used as the peeling substrate (first SOI substrate 100 in step A). Although the semiconductor film is formed on the third single crystal semiconductor film 113 after the third single crystal semiconductor film 113 is planarized, the method of crystallizing by epitaxial growth (solid growth) by heat treatment is shown. It is not limited to this.

For example, the semiconductor film 114 is formed without performing the planarization process on the surface of the 3rd single crystal semiconductor film 113 of the 2nd SOI substrate 110 after peeling (refer FIG. 3E-1), and after that The crystallization of the semiconductor film 114 may be performed by performing heat treatment (see FIG. 3A-3). In this case, even when the surface of the third single crystal semiconductor film 113 is uneven, the semiconductor film 114 is formed on the third single crystal semiconductor film 113 and then crystallized to form the second single crystal semiconductor film 154. By forming, the surface of the second single crystal semiconductor film 154 can be made less relaxed than the unevenness of the surface of the third single crystal semiconductor film 113.

Thereafter, the process of FIGS. 3A-4 may be performed or the process of FIGS. 3A-4 may be performed after the planarization treatment is performed on the surface of the second single crystal semiconductor film 154. In addition, even when the second single crystal semiconductor film 154 is planarized, the surface is flat compared to the surface of the third single crystal semiconductor film 113 after peeling, and thus compared with the case where the planarization treatment is performed after peeling. Flattening can be performed easily.

3A-1 to 3E-2, the first SOI substrate 100 used as the peeling substrate for manufacturing the second SOI substrate 110 is subjected to planarization treatment (see FIG. 3E-2) after peeling. Although the case is shown, the heat treatment is performed after forming the semiconductor film on the remaining second single crystal semiconductor film 154 similarly to the second SOI substrate 110 to seed the remaining second single crystal semiconductor film 154. A single crystal semiconductor film may be formed as the layer). It is suitable for forming a thick single crystal semiconductor film of an SOI substrate.

In addition, the manufacturing method of the SOI board | substrate shown by this embodiment can be performed in appropriate combination with the manufacturing method shown by other embodiment of this specification.

(Embodiment 3)

In this embodiment, the manufacturing method of the SOI board | substrate different from the said embodiment is demonstrated with reference to drawings. Specifically, a method different from the above embodiment will be described with respect to a method of forming a semiconductor film on the first single crystal semiconductor film, and epitaxial growth (gas phase growth) to form a second single crystal semiconductor film simultaneously with the film formation. do.

A semiconductor film formed by forming a semiconductor film (e.g., a silicon film) on a single crystal semiconductor film (e.g., a single crystal silicon film) under a predetermined condition by a CVD method, is deposited and epitaxy as a seed layer as a seed layer. Earl growth (weather growth).

For example, after performing the process to FIGS. 2A-1 to 2D, a semiconductor film is formed on the 2nd SOI substrate 110 used as a peeling board | substrate under predetermined conditions using CVD method. As a result, the fourth single crystal semiconductor film 164 can be formed by forming a semiconductor film on the third single crystal semiconductor film 113 of the second SOI substrate 110 while epitaxially growing (vapor growth) (FIG. 4E). -1).

In addition, the conditions of plasma CVD method are performed on the conditions which form a microcrystalline semiconductor film. Specifically, in the atmosphere containing silane gas and hydrogen gas, the flow rate of hydrogen gas is 50 times or more, preferably 100 times or more compared with the flow rate of silane gas. By performing on these conditions, epitaxial growth can be performed simultaneously with film-forming.

In addition, the manufacturing method of the SOI board | substrate shown by this embodiment can be performed in appropriate combination with the manufacturing method shown by other embodiment of this specification.

(Embodiment 4)

In this embodiment, in the manufacturing method of the SOI substrate shown in the said embodiment, an example of the manufacturing method of the SOI substrate used as a peeling substrate is demonstrated with reference to drawings.

Although the said embodiment shows about the case where the SOI substrate (2nd SOI substrate 110) produced using the SOI substrate (1st SOI substrate 100) which functions as a peeling substrate is used as a peeling substrate, In this embodiment, the manufacturing method of the SOI substrate (1st SOI substrate 100) which becomes the base is demonstrated with reference to drawings.

First, an insulating film 102 is formed on the surface, and a single crystal semiconductor substrate 171 (for example, a single crystal silicon substrate) having a release layer 175 formed at a predetermined depth from the surface is prepared (see Fig. 9A).

As the single crystal semiconductor substrate 171, a commercially available semiconductor substrate can be used. Examples of the single crystal semiconductor substrate 171 include a compound semiconductor substrate such as a single crystal silicon substrate, a germanium substrate, gallium arsenide, and indium. Commercially available silicon substrates are typically 5 inches (125 mm) in diameter, 6 inches (150 mm) in diameter, 8 inches (200 mm) in diameter, and 12 inches (300 mm) in diameter. In addition, the shape is not limited to a circular shape, The silicon substrate processed into the rectangular shape etc. can also be used.

The insulating film 102 functions as a bonding layer.

The release layer 175 can be formed by irradiating an ion beam made of ions accelerated by an electric field to introduce ions into a region of a predetermined depth from the surface of the single crystal semiconductor substrate 171.

Next, the first substrate 101 is prepared (see FIG. 9B), the surface of the single crystal semiconductor substrate 171 and the surface of the first substrate 101 are opposed to each other, and the surface of the insulating film 102 serving as a bonding layer The surface of the first substrate 101 is bonded (see FIG. 9C). A junction is formed by bringing the insulating film 102 formed on the single crystal semiconductor substrate 171 into close contact with the surface of the first substrate 101. In this junction, van der Waal's forces are applied, and the single crystal semiconductor substrate 171 and the first substrate 101 are brought into close contact with each other to form a hydrogen bond using Si-H, Si-OH, or the like as a bonding species. It is possible to form a firm bond by.

Next, heat treatment is performed, cleavage is carried out in the release layer 175, and a part of the single crystal semiconductor substrate 171 is peeled off and formed on the first substrate 101 (see FIG. 9D). In this case, by performing a heat treatment at 400 ° C to 700 ° C, a small cavity volume change occurs in the ions (for example, hydrogen ions) included in the release layer 175, and cleavage in connection with the release layer 175. It becomes possible. As a result, the first single crystal semiconductor film 103 is formed on the first substrate 101 through the insulating film 102.

By the above process, the first SOI substrate 100 having the first single crystal semiconductor film 103 formed on the first substrate 101 through the insulating film 102 can be formed.

Thereafter, the first SOI substrate 100 can be used as the peeling substrate in FIGS. 1A-1 to 2E-2.

Thus, in this embodiment, after producing the SOI substrate used later as a peeling substrate using a single crystal semiconductor substrate, the said SOI substrate is used as a peeling substrate. Therefore, when 50 SOI substrates having a single crystal semiconductor film are formed on a non-semiconductor substrate (for example, a glass substrate), in the conventional method, it is necessary to use a single crystal semiconductor substrate as a peeling substrate in the production of all SOI substrates. there was. Therefore, the possibility of joining defects is high by the difference of the characteristic of a peeling board | substrate and a to-be-peeled board | substrate, and there exists a possibility that a yield may fall. In addition, when the semiconductor substrate is repeatedly reused, the quality difference between a plurality of SOI substrates produced is caused by the deterioration of the quality of the semiconductor substrate which becomes the peeling substrate.

On the other hand, in the production method of the SOI substrate of the present invention, a single crystal semiconductor substrate is used as the peeling substrate for the manufacture of the first SOI substrate (here, the first SOI substrate), but for the manufacture of the SOI substrate after the second sheet. As a peeling board | substrate and a to-be-peeled board | substrate, the board | substrate which consists of the same material can be used. As a result, joining defects can be reduced and yield can be improved. As shown in Figs. 2A-1 to 2E-2, by using the manufactured SOI substrate as a peeling substrate, the peeling substrate is prevented from being reused repeatedly, and the plurality of SOI substrates are manufactured. The difference in quality can be reduced.

In addition, the manufacturing method of the SOI board | substrate shown by this embodiment can be performed in appropriate combination with the manufacturing method shown by other embodiment of this specification.

(Embodiment 5)

In this embodiment, a method of manufacturing a semiconductor device using the SOI substrate produced in the above embodiment will be described.

First, an n-channel thin film transistor and a p-channel thin film transistor are described as a method of manufacturing a semiconductor device with reference to FIGS. 5A to 6C. Various semiconductor devices can be formed by combining a plurality of thin film transistors (TFTs).

The case where the SOI substrate produced by the method of Embodiment 1 is used as an SOI substrate is demonstrated. In addition, in this FIG. 1E, the case where the planarization process is performed and the 2nd single crystal semiconductor film 154 is removed and the 1st single crystal semiconductor film 103 is exposed is used for the case where the SOI substrate is used.

5A is a cross-sectional view of an SOI substrate fabricated by the method described using FIGS. 1A-1 through 1E.

By etching, the first single crystal semiconductor film 103 of the SOI substrate is separated and the semiconductor films 251 and 252 are formed as shown in Fig. 5B. The semiconductor film 251 constitutes an n-channel TFT, and the semiconductor film 252 constitutes a p-channel TFT.

As shown in FIG. 5C, an insulating film 254 is formed over the semiconductor films 251 and 252. Next, the gate electrode 255 is formed on the semiconductor film 251 through the insulating film 254, and the gate electrode 256 is formed on the semiconductor film 252.

Further, in order to control the threshold voltage of the TFT before etching the first single crystal semiconductor film 103, an impurity element serving as an acceptor such as boron, aluminum, gallium, or a donor such as phosphorus, arsenic or the like It is preferable to add an element to the first single crystal semiconductor film 103. For example, an acceptor is added to a region where an n-channel TFT is formed, and a donor is added to a region where a p-channel TFT is formed.

Next, as shown in FIG. 5D, an n-type low concentration impurity region 257 is formed in the semiconductor film 251, and a p-type high concentration impurity region 259 is formed in the semiconductor film 252. First, an n-type low concentration impurity region 257 is formed in the semiconductor film 251. Therefore, the semiconductor film 252 to be a p-channel TFT is masked with a resist, and a donor is added to the semiconductor film 251. What is necessary is just to add phosphorus or arsenic as a donor. By adding a donor by an ion doping method or an ion implantation method, the gate electrode 255 becomes a mask, and the n type low concentration impurity region 257 is formed in the semiconductor film 251 in a self-alignment manner. The region overlapping with the gate electrode 255 of the semiconductor film 251 becomes the channel formation region 258.

Next, after removing the mask covering the semiconductor film 252, the semiconductor layer 251 to be an n-channel TFT is covered with a resist mask. Next, the acceptor is added to the semiconductor film 252 by ion doping or ion implantation. As an acceptor, boron can be added. In the addition process of the acceptor, the gate electrode 255 functions as a mask, and the p-type high concentration impurity region 259 is self-aligned in the semiconductor film 252. The p-type high concentration impurity region 259 functions as a source region or a drain region. The region overlapping with the gate electrode 256 of the semiconductor film 252 becomes the channel formation region 260. Here, the method for forming the p-type high concentration impurity region 259 after the n-type low concentration impurity region 257 has been described, but first, the p-type high concentration impurity region 259 may be formed.

Next, after removing the resist covering the semiconductor film 251, an insulating film having a single layer structure or a laminated structure made of a nitrogen compound such as silicon nitride or an oxide such as silicon oxide is formed by a plasma CVD method or the like. By anisotropically etching this insulating film, as shown in FIG. 6A, sidewall insulating layers 261 and 262 in contact with the side surfaces of the gate electrodes 255 and 256 are formed. By this anisotropic etching, the insulating film 254 is also etched.

Next, as shown in FIG. 6B, the semiconductor layer 252 is covered with a resist 265. In order to form a high concentration impurity region functioning as a source region or a drain region in the semiconductor layer 251, a donor is added to the semiconductor layer 251 in a high amount by an ion implantation method or an ion doping method. The gate electrode 255 and the sidewall insulating film 261 are masked to form an n-type high concentration impurity region 267. Next, heat treatment for activation of the donor and acceptor is performed.

After the activation heat treatment, as shown in Fig. 6C, an insulating film 268 containing hydrogen is formed. After the insulating film 268 is formed, heat treatment is performed at a temperature of 350 ° C. or more and 450 ° C. or less to diffuse hydrogen contained in the insulating film 268 into the semiconductor films 251 and 252. The insulating film 268 can be formed by depositing silicon nitride or silicon nitride oxide by a plasma CVD method having a process temperature of 350 ° C. or lower. By supplying hydrogen to the semiconductor films 251 and 252, defects which become trapping centers in the semiconductor films 251 and 252 and at the interface with the insulating film 254 can be effectively compensated.

Thereafter, an interlayer insulating layer 269 is formed. The interlayer insulating layer 269 is an insulating film made of an inorganic material such as a silicon oxide film, a BPSG (Boron Phosphorus Silicon Glass) film, or a single layer structure film or a laminated structure film selected from organic resin films such as polyimide and acryl. Can be formed. After the contact holes are formed in the interlayer insulating film 269, the wiring 270 is formed as shown in Fig. 6C. In the formation of the wiring 270, for example, a low resistance metal film such as an aluminum film or an aluminum alloy film can be formed of a conductive film having a three-layer structure in which a barrier metal film is sandwiched. The barrier metal film can be formed of a metal film such as molybdenum, chromium or titanium.

Through the above steps, a semiconductor device having an n-channel TFT and a p-channel TFT can be manufactured. In the production process of the SOI substrate, since the concentration of the metal element of the semiconductor film constituting the channel formation region is reduced, a TFT with small off current and suppressed fluctuation in threshold voltage can be produced.

Although the manufacturing method of TFT was demonstrated with reference to FIGS. 5A-6C, high value-added semiconductor device can be manufactured by forming various semiconductor elements with TFT, such as a capacitance | capacitance and a resistance other than TFT. Hereinafter, the specific form of a semiconductor device is demonstrated, referring drawings.

First, a microprocessor will be described as an example of a semiconductor device. 7 is a block diagram illustrating a configuration example of a microprocessor 500.

The microprocessor 500 may include an arithmetic logic unit (ALU), an arithmetic circuit controller 502 (ALU controller), an instruction interpreter 503 (Instruction Decoder), and an interrupt controller 504 (interrupt controller). A timing controller 505, a register 506, a register controller 507, a bus interface 508, a bus I / F, a read-only memory 509, and a memory interface 510. Has

The command input to the microprocessor 500 via the bus interface 508 is input to the command interpreter 503 and decoded, and then the arithmetic circuit control unit 502, the interrupt control unit 504, and the register control unit 507. Input to the timing controller 505. The calculation circuit control unit 502, the interrupt control unit 504, the register control unit 507, and the timing control unit 505 perform various controls based on the decoded instructions.

The arithmetic circuit control unit 502 generates a signal for controlling the operation of the arithmetic circuit 501. The interrupt control unit 504 is a circuit for processing interrupt requests from external input / output devices or peripheral circuits during program execution of the microprocessor 500, and the interrupt control unit 504 controls the priority or mask state of interrupt requests. Determine and handle the interrupt request. The register control unit 507 generates an address of the register 506 and reads or writes the register 506 according to the state of the microprocessor 500. The timing controller 505 generates a signal for controlling the timing of the operation of the operation circuit 501, the operation circuit control unit 502, the instruction analysis unit 503, the interrupt control unit 504, and the register control unit 507. For example, the timing controller 505 includes an internal clock generator that generates the internal clock signal CLK2 based on the reference clock signal CLK1. As shown in Fig. 7, the internal clock signal CLK2 is input to another circuit.

Next, an example of a semiconductor device having a function of transmitting and receiving data in a non-contact manner and a calculation function will be described. 8 is a block diagram illustrating a configuration example of such a semiconductor device. The semiconductor device shown in FIG. 8 can be referred to as a computer (hereinafter referred to as "RFCPU") which operates by transmitting and receiving signals to and from an external device by wireless communication.

As shown in FIG. 8, the RFCPU 511 includes an analog circuit portion 512 and a digital circuit portion 513. As the analog circuit unit 512, a resonant circuit 514, a rectifier circuit 515, a constant voltage circuit 516, a reset circuit 517, an oscillation circuit 518, a demodulation circuit 519, and a modulation circuit having a resonance capacitance ( 520). The digital circuit unit 513 includes an RF interface 521, a control register 522, a clock controller 523, a CPU interface 524, a central processing unit 525, a random access memory 526, and a read-only memory ( 527).

The outline of the operation of the RFCPU 511 is as follows. The signal received by the antenna 528 generates induced electromotive force by the resonant circuit 514. The induced electromotive force is charged in the capacitor portion 529 via the rectifier circuit 515. The capacitor portion 529 is preferably formed of a capacitor such as a ceramic capacitor or an electric double layer capacitor. The capacitor portion 529 does not need to be integrated on the substrate constituting the RFCPU 511, but may be combined with the RFCPU 511 as a separate component.

The reset circuit 517 generates a signal for resetting and initializing the digital circuit unit 513. For example, a signal rising in delay with the increase in the power supply voltage is generated as a reset signal. The oscillation circuit 518 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the constant voltage circuit 516. The demodulation circuit 519 is a circuit for demodulating a received signal, and the modulation circuit 520 is a circuit for modulating data to be transmitted.

For example, the demodulation circuit 519 is formed of a low-pass filter, and binarizes a received signal of an amplitude modulation (ASK) system based on the variation of the amplitude thereof. . In addition, since the transmission data is transmitted by varying the amplitude of the transmission signal of the amplitude modulation (ASK) system, the modulation circuit 520 changes the amplitude of the communication signal by changing the resonance point of the resonance circuit 514.

The clock controller 523 generates a control signal for changing the frequency and duty ratio of the clock signal in accordance with the power supply voltage or the current consumption in the central processing unit 525. The power supply management circuit 530 monitors the power supply voltage.

The signal input to the RF CPU 511 from the antenna 528 is demodulated by the demodulation circuit 519 and then decomposed into control commands, data, or the like at the RF interface 521. The control command is stored in the control register 522. The control command includes reading data stored in the read-only memory 527, writing data to the random access memory 526, arithmetic instructions to the central processing unit 525, and the like.

The central processing unit 525 accesses the read-only memory 527, the random access memory 526, and the control register 522 through the CPU interface 524. The CPU interface 524 has a function of generating an access signal for any one of the read-only memory 527, the random access memory 526, and the control register 522 from the address requested by the central processing unit 525. Have

As the calculation method of the central processing unit 525, an OS (operating system) is stored in the read-only memory 527, and a system that reads and executes a program along with startup can be adopted. It is also possible to employ a scheme of configuring arithmetic circuits in dedicated circuits and processing arithmetic processing in hardware. In the method of using hardware and software together, a method of performing some arithmetic processing in a dedicated arithmetic circuit, using a program, and executing the remaining arithmetic operations by the central processing unit 525 can be applied.

Next, a display device as a semiconductor device will be described with reference to FIGS. 10A to 11B.

10A and 10B are diagrams for describing a liquid crystal display device. 10A is a plan view of a pixel of the liquid crystal display, and FIG. 10B is a cross-sectional view of FIG. 10A taken along the line J-K.

As shown in FIG. 10A, the pixel includes a single crystal semiconductor film 320, a scan line 322 crossing the single crystal semiconductor film 320, a signal line 323 crossing the scan line 322, a pixel electrode 324, and a pixel. An electrode 328 is electrically connected between the electrode 324 and the single crystal semiconductor film 320. The single crystal semiconductor film 320 is a layer formed from the single crystal semiconductor film 302 bonded to the SOI substrate, and constitutes the TFT 325 of the pixel.

As the SOI substrate, the SOI substrate shown in the above embodiment is used. As shown in FIG. 10B, an insulating film 102 and a single crystal semiconductor film 320 are stacked on the first substrate 101. The first substrate 101 is glass. The single crystal semiconductor film 320 of the TFT 325 is a film formed by element-separating a semiconductor film of an SOI substrate by etching. The channel formation region 340 and the n-type high concentration impurity region 341 to which the donor is added are formed in the single crystal semiconductor film 320. The gate electrode of the TFT 325 is included in the scan line 322, and one of the source electrode and the drain electrode is included in the signal line 323.

The signal line 323, the pixel electrode 324, and the electrode 328 are formed on the interlayer insulating layer 327. A columnar spacer 329 is formed on the interlayer insulating film 327. An alignment layer 330 is formed by covering the signal line 323, the pixel electrode 324, the electrode 328, and the columnar spacer 329. On the opposing substrate 332, an opposing electrode 333 and an alignment layer 334 covering the opposing electrode 333 are formed. The columnar spacer 329 is formed in order to maintain the gap between the first substrate 101 and the opposing substrate 332. The liquid crystal layer 335 is formed in the gap formed by the columnar spacer 329. Since the connection portion between the signal line 323 and the electrode 328 and the high concentration impurity region 341 generates a step in the interlayer insulating film 327 due to the formation of a contact hole, the alignment of the liquid crystal of the liquid crystal layer 335 is changed at this connection portion. Easy to distract Therefore, the columnar spacer 329 is formed in this step part, and the disturbance of the orientation of a liquid crystal is prevented.

Next, an electroluminescence display device (hereinafter referred to as EL display device) will be described with reference to FIGS. 11A and 11B. Fig. 11A is a plan view of a pixel of the EL display device, and Fig. 11B is a cross-sectional view of Fig. 11A taken along the line J-K.

As shown in FIG. 11A, a pixel includes a selection transistor 401, a display control transistor 402, a scan line 405, a signal line 406, a current supply line 407, and a pixel electrode 408 made of TFTs. Include. A light emitting element having a structure in which a layer (EL layer) formed of an electroluminescent material is sandwiched between a pair of electrodes is formed in each pixel. One electrode of the light emitting element is the pixel electrode 408. In the semiconductor film 403, a channel formation region, a source region, and a drain region of the selection transistor 401 are formed. In the semiconductor film 404, a channel formation region, a source region and a drain region of the display control transistor 402 are formed. The semiconductor films 403 and 404 are films formed of a single crystal semiconductor film 302 bonded to an SOI substrate.

In the selection transistor 401, the gate electrode is included in the scan line 405, one of the source electrode and the drain electrode is included in the signal line 406, and the other is formed as the electrode 411. The display control transistor 402 is formed as an electrode 413 whose gate electrode 412 is electrically connected to the electrode 411, and one of the source electrode and the drain electrode is electrically connected to the pixel electrode 408. The other is included in the current supply line 407.

The display control transistor 402 is a p-channel TFT. As shown in FIG. 11B, a channel formation region 451 and a p-type high concentration impurity region 452 are formed in the semiconductor film 404. As the SOI substrate, the SOI substrate 132 produced by the method of Embodiment 1 is used.

An interlayer insulating film 427 is formed to cover the gate electrode 412 of the display control transistor 402. The signal line 406, the current supply line 407, the electrodes 411, 413, and the like are formed on the interlayer insulating film 427. The pixel electrode 408 electrically connected to the electrode 413 is formed on the interlayer insulating film 427. The peripheral portion of the pixel electrode 408 is surrounded by the insulating barrier rib layer 428. An EL layer 429 is formed over the pixel electrode 408, and an opposite electrode 430 is formed over the EL layer 429. An opposing substrate 431 is formed as a reinforcing plate, and the opposing substrate 431 is fixed to the first substrate 101 by the resin layer 432.

The gray scale control of the EL display device includes a current driving method for controlling the brightness of a light emitting element with a current and a voltage driving method for controlling the brightness with a voltage. When is large, it is difficult to employ, and for that purpose, a correction circuit for correcting the variation in characteristics is required. By fabricating the EL display device by a manufacturing method including a fabrication process of a SOI substrate and a gettering process, the selection transistor 401 and the display control transistor 402 do not have variations in characteristics for each pixel. Can be adopted.

That is, by using an SOI substrate, various electric devices can be manufactured. As an electric apparatus, cameras, such as a video camera and a digital camera, a navigation system, a sound reproducing apparatus (car audio, an audio component, etc.), a computer, a game device, a portable information terminal (mobile computer, a mobile phone, a portable game machine, or an electronic book, etc.) And an image reproducing apparatus provided with a recording medium (specifically, a device provided with a display device capable of reproducing a recording medium such as a digital versatile disc (DVD) and displaying stored image data).

12A-12C, the specific form of an electric device is demonstrated. 12A is an external view illustrating an example of the mobile telephone 901. This mobile phone 901 includes a display unit 902, an operation switch 903, and the like. By applying the liquid crystal display device described in FIGS. 10A and 10B or the EL display device described in FIGS. 11A and 11B to the display portion 902, the display portion 902 with less display unevenness and excellent image quality can be obtained.

12B is an external view showing a configuration example of the digital player 911. The digital player 911 includes a display unit 912, an operation unit 913, an earphone 914, and the like. In place of the earphone 914, headphones or wireless earphones may be used. By applying the liquid crystal display device described in FIGS. 10A and 10B or the EL display device described in FIGS. 11A and 11B to the display portion 912, even when the screen size is about 0.3 inches to about 2 inches, high definition Images and a large amount of text information can be displayed.

12C is an external view of the electronic book 921. This electronic book 921 includes a display unit 922 and an operation switch 923. The electronic book 921 may have a built-in modem, or a built-in RFCPU of FIG. 8 may be configured to transmit and receive information wirelessly. By applying the liquid crystal display device described with reference to FIGS. 10A and 10B or the EL display device described with reference to FIGS. 11A and 11B to the display portion 922, high quality display can be performed.

In addition, the manufacturing method of the SOI board | substrate shown by this embodiment can be performed in appropriate combination with the manufacturing method shown by other embodiment of this specification.

Example 1

In the present embodiment, in the preparation of the SOI substrate, the crystallinity after the heat treatment in the case where the heat treatment is performed after the amorphous semiconductor film is formed on the single crystal semiconductor film of the SOI substrate after peeling will be described.

First, a single crystal semiconductor substrate (herein, a silicon wafer) to be a substrate for peeling was prepared, and a silicon oxynitride film was formed at 100 nm by plasma CVD on the single crystal semiconductor substrate, and then a silicon nitride oxide film was formed at 50 nm. Next, hydrogen ions were introduced into the single crystal semiconductor substrate by using an ion doping method to form a release layer. The hydrogen doping conditions were performed at 25 kV of acceleration voltage, 100 W of RF power, and dose of 2.2 × 10 ¹⁶ ions / cm ² using hydrogen gas. Next, an insulating film functioning as a bonding layer was formed on the silicon nitride oxide film. Here, 50 nm of a silicon oxide film was formed by using organic silane (TEOS: Si (OC ₂ H ₅ ) ₄ ) as a raw material gas as an insulating film functioning as a bonding layer by using a CVD method. Next, a glass substrate is prepared, and the surface of the insulating film which functions as a bonding layer formed on the single crystal semiconductor substrate and the surface of the glass substrate are bonded (see FIG. 13A). Next, a heat treatment (heat treatment at 200 ° C. for 2 hours and then heat treatment at 600 ° C. for 4 hours) was performed and cleaved at the release layer to form a single crystal silicon film on the glass substrate (see FIG. 13B). In addition, a single crystal silicon film was formed on the glass substrate through the silicon oxynitride film, the silicon nitride oxide film, and the silicon oxide film (see FIG. 13C).

Next, an amorphous silicon (a-Si) film was formed by 40 nm on the single crystal silicon film formed on the glass substrate (refer FIG. 13D). Thereafter, heat treatment was performed at 750 ° C. for 3 minutes using a Rapid Thermal Anneal (RTA) apparatus to crystallize the a-Si film (see FIG. 13E).

The result of having performed Raman spectroscopy measurement about the crystallinity before and behind the heat processing of the semiconductor film formed into FIG. 14 is shown.

14, the heat-treated has a gentle peak representing the amorphous peaks of 520.6cm ^-1 small single crystals with a 440cm ^-1 to 500cm ^-1 was observed. On the other hand, after the heat treatment, only a Raman peak (520.6 cm ⁻¹ ) indicating a single crystal of silicon was observed. As a result, it was found that amorphous silicon formed on the single crystal silicon film was crystallized to the single crystal silicon film to which stress was not applied by heat treatment.

Next, the plane orientation of the crystals before and after the heat treatment of the formed semiconductor film will be described with reference to FIGS. 15A to 15C. 15A and 15B are Inverse Pole Figure (IPF) maps obtained from measurement data of an Electron Back Scatter Diffraction Pattern (EBSP) on a silicon film surface. 15A is an IPF map of a silicon film not subjected to heat treatment after amorphous silicon film formation, and FIG. 15B is an IPF map of a silicon film subjected to heat treatment after amorphous silicon film formation. Fig. 15C is a color code map which color codes each orientation of the crystal and shows the relationship between the color scheme of the IPF map and the crystal orientation. In addition, the measurement range was 40 micrometers x 40 micrometers.

In the IPF maps of FIGS. 15A and 15B, it was confirmed that the surface orientation was random after the formation of the a-Si film, but after the heat treatment, there was no grain boundary and a single crystal silicon film having a crystal axis of <100> orientation was obtained.

According to the above results, even when a-Si is formed on the single crystal silicon film without performing the planarization treatment and heat treatment is performed, the a-Si film is grown by epitaxial growth (solid growth) using the single crystal silicon film as a seed layer. Crystallization was confirmed.

Example 2

In the present embodiment, in the preparation of the SOI substrate, the planarization of the surface when heat treatment is performed after the amorphous semiconductor film is formed on the single crystal semiconductor film of the SOI substrate after peeling will be described.

In the present Example, after peeling similarly to the said Example 1, after a-Si film-forming and heat processing (refer FIG. 13E), the surface of a surface was made using a scanning electron microscope (SEM). Observed. In addition, as a comparison, the surface of the single crystal silicon film after peeling (refer FIG. 13C) was observed using SEM.

The SEM image of the surface of the SOI substrate after a-Si film-forming and heat processing after peeling to FIG. 16A is shown, and the SEM image of the surface of the SOI substrate after peeling as a comparative example is shown to FIG. 16B.

As shown to FIG. 16A and 16B, the surface unevenness | corrugation of the surface of the SOI substrate after peeling was observed. On the other hand, it was observed that the surface of the SOI substrate subjected to the heat treatment after the a-Si film formation was flattened by the unevenness being alleviated compared with the surface of the SOI substrate after peeling. This is considered to be because a-Si formed is formed so as to alleviate the unevenness of the surface of the single crystal silicon film.

1A-1E are diagrams showing an example of a method for producing an SOI substrate of the present invention.

2A-1 to 2E-2 are diagrams showing an example of the method for producing the SOI substrate of the present invention.

3A-1 to 3E-2 are diagrams showing an example of the method for producing the SOI substrate of the present invention.

4A-1 to 4E-2 show examples of the method for producing the SOI substrate of the present invention.

5A to 5D are views showing an example of a method of manufacturing a semiconductor device using the SOI substrate of the present invention.

6A to 6C are diagrams showing an example of a method of manufacturing a semiconductor device using the SOI substrate of the present invention.

7 is a diagram showing an example of a semiconductor device using the SOI substrate of the present invention.

8 is a diagram showing an example of a semiconductor device using the SOI substrate of the present invention.

9A to 9F are views showing an example of a method for producing an SOI substrate to be a peeling substrate.

10A and 10B show an example of a display device using the SOI substrate of the present invention.

11A and 11B show an example of a display device using the SOI substrate of the present invention.

12A to 12C show electronic devices using the SOI substrate of the present invention.

13A to 13E illustrate a method of manufacturing the SOI substrate of the present invention.

14 shows the results of Raman spectroscopic measurements of semiconductor films before and after heat treatment.

15A to 15C are diagrams showing the results of EBSP of semiconductor films before and after heat treatment.

16A and 16B show SEM images of a surface of a semiconductor film grown in solid phase.

<Explanation of symbols for the main parts of the drawings>

100: SOI substrate 100 ': first SOI substrate

101: substrate 102: insulating film

103: single crystal semiconductor film 104: semiconductor film

105: release layer 106: insulating film

107: ion beam 110: SOI substrate

111 substrate 113 single crystal semiconductor film

154: second single crystal semiconductor film

Claims (17)

Preparing a first SOI substrate having a first single crystal semiconductor film formed thereon through a first insulating film on a first substrate made of an insulator; Preparing a second substrate formed of the same material as the first substrate; Forming a second single crystal semiconductor film on the first single crystal semiconductor film; Forming a release layer by adding ions to the second single crystal semiconductor film; Forming a second insulating film on the second single crystal semiconductor film; Bonding the surface of the second insulating film to the surface of the second substrate; Performing heat treatment on the exfoliation layer to cause cleavage in the exfoliation layer such that a second SOI substrate, on which a portion of the second single crystal semiconductor film is formed, is formed over the second substrate via the second insulating film. How to make. The method of claim 1, A glass substrate is used as the first substrate and the second substrate. The method of claim 1, And the second single crystal semiconductor film is crystallized by solid phase growth of the semiconductor film after heat treatment after forming the semiconductor film on the first single crystal semiconductor film. The method of claim 3, wherein An amorphous semiconductor film is used as the semiconductor film. The method of claim 1, And the second single crystal semiconductor film is formed by vapor phase growth of a semiconductor film formed on the first single crystal semiconductor film by CVD. Preparing a semiconductor substrate having a first insulating film formed on the surface, a first release layer formed at a predetermined depth, and a first substrate made of an insulator; Preparing a second substrate formed of the same material as the first substrate; Bonding the surface of the first insulating film to the surface of the first substrate; Heat treating the first exfoliation layer to cause cleavage in the first exfoliation layer such that a first SOI substrate on which the first single crystal semiconductor film is formed is formed on the first substrate through the first insulating film; Forming a second single crystal semiconductor film on the first single crystal semiconductor film; Forming a second release layer by adding ions to the second single crystal semiconductor film; Forming a second insulating film on the second single crystal semiconductor film; Bonding the surface of the second insulating film to the surface of the second substrate; Performing heat treatment on the second exfoliation layer to cause cleavage in the exfoliation layer such that a second SOI substrate, on which a portion of the second single crystal semiconductor film is formed, is formed over the second substrate via the second insulating film; Method of making an SOI substrate. The method of claim 6, A glass substrate is used as the first substrate and the second substrate. The method of claim 6, And the second single crystal semiconductor film is crystallized by solid phase growth of the semiconductor film after heat treatment after forming the semiconductor film on the first single crystal semiconductor film. The method of claim 8, An amorphous semiconductor film is used as the semiconductor film. The method of claim 6, And the second single crystal semiconductor film is formed by vapor phase growth of a semiconductor film formed on the first single crystal semiconductor film by CVD. As the first step, Preparing a first SOI substrate having a first single crystal semiconductor film formed thereon through a first insulating film on a first substrate made of an insulator; Preparing a second substrate formed of the same material as the first substrate; Forming a second single crystal semiconductor film on the first single crystal semiconductor film; Forming a release layer by adding ions to the second single crystal semiconductor film; Forming a second insulating film on the second single crystal semiconductor film; And As the second step, Bonding the surface of the second insulating film to the surface of the second substrate; Performing heat treatment on the exfoliation layer to cause cleavage in the exfoliation layer such that a second SOI substrate with a portion of the second single crystal semiconductor film formed on the second substrate is formed through the second insulating film. Including 2 processes, The second SOI substrate formed in the second step is used as the first SOI substrate in the first step. The method of claim 11, A planarization process is a method for producing an SOI substrate, wherein the planarization treatment is performed on one or both of the surface of the second single crystal semiconductor film remaining on the first substrate and the surface of the second single crystal semiconductor film formed on the second substrate. The method of claim 12, The manufacturing method of the SOI substrate which irradiates a laser beam for the said planarization process. The method of claim 11, A glass substrate is used as the first substrate and the second substrate. The method of claim 11, And the second single crystal semiconductor film is crystallized by solid phase growth of the semiconductor film after heat treatment after forming the semiconductor film on the first single crystal semiconductor film. The method of claim 15, An amorphous semiconductor film is used as the semiconductor film. The method of claim 11, And the second single crystal semiconductor film is formed by vapor phase growth of a semiconductor film formed on the first single crystal semiconductor film by CVD.

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