KR20090050702A - Capacitor for semiconductor device and method for fabricating the same - Google Patents

Abstract

An embodiment relates to a capacitor of a semiconductor device and a method of forming the same. The capacitor of the semiconductor device according to the embodiment may include a lower electrode formed on a substrate, a dielectric film pattern formed on the lower electrode, an upper electrode formed on a portion of the dielectric film pattern, and formed on sidewalls of the upper electrode and the dielectric film pattern. Spacers having a smaller dielectric constant. The embodiment can reduce the parasitic capacitance generated at the edge of the capacitor electrode to improve the capacitor characteristics and maintain the capacitance value constant.

Capacitors, Spacers

Description

Capacitor for Semiconductor Device and Forming Method thereof {CAPACITOR FOR SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

An embodiment relates to a capacitor of a semiconductor device and a method of forming the same.

Recently, a semiconductor device in which an analog capacitor in a logic circuit is integrated with a logic circuit by a high integration technology of a semiconductor device has been researched and developed and used as a product. Analog capacitors used in the logic circuit are mainly used in the form of PIP (Polysilicon / Insulator / Polysilicon) and MIM (Metal / Insulator / Metal).

These PIP or MIM type capacitors, unlike metal oxide silicon (MOS) type capacitors or junction capacitors, are bias-independent and are used in analog products requiring capacitor precision.

Here, the MIM capacitor may be manufactured at the bottom electrode and the top electrode when the metal wiring is formed.

Conventional MIM capacitors not only have a capacitance between the upper electrode and the lower electrode, but also parasitic capacitance occurring at the electrode edge. Due to this parasitic capacitance, it is difficult to obtain a desired capacitance value and there is a problem in that the variation in design value occurs.

The embodiment provides a capacitor of a semiconductor device having good capacitor characteristics and a method of forming the capacitor.

The capacitor of the semiconductor device according to the embodiment may include a lower electrode formed on a substrate, a dielectric film pattern formed on the lower electrode, an upper electrode formed on a portion of the dielectric film pattern, and formed on sidewalls of the upper electrode and the dielectric film pattern. Spacers having a smaller dielectric constant.

In the method of forming a capacitor of a semiconductor device according to the embodiment, the steps of sequentially forming a lower electrode film, a dielectric film, an upper electrode film on the substrate, patterning the upper electrode film to form an upper electrode, on the sidewall of the upper electrode Forming a spacer, and patterning the dielectric layer and the lower electrode layer to form a dielectric layer pattern and a lower electrode larger than the spacer and the upper electrode.

The embodiment has the effect of reducing the parasitic capacitance generated at the edge of the capacitor electrode to improve the capacitor characteristics and maintain the capacitance value to improve the semiconductor device characteristics and improve the yield.

Hereinafter, a capacitor and a method of forming the semiconductor device according to the embodiment will be described in detail with reference to the accompanying drawings. However, one of ordinary skill in the art who understands the spirit of the present invention may easily propose another embodiment by adding, adding, deleting, or modifying elements within the scope of the same spirit, but this also belongs to the scope of the present invention. I will say.

A capacitor and a method of forming the semiconductor device according to the embodiments will be described in detail with reference to the accompanying drawings. Hereinafter, when referred to as "first", "second", and the like, this is not intended to limit the members but to show that the members are divided and have at least two. Thus, when referred to as "first", "second", etc., it is apparent that a plurality of members are provided, and each member may be used selectively or interchangeably. In addition, the size (dimensions) of each component of the accompanying drawings are shown in an enlarged manner to help understanding of the invention, the ratio of the dimensions of each of the illustrated components may be different from the ratio of the actual dimensions. In addition, not all components shown in the drawings are necessarily included or limited to the present invention, and components other than the essential features of the present invention may be added or deleted. In the description of an embodiment according to the present invention, each layer (film), region, pattern or structure is “on / above / over / upper” of the substrate, each layer (film), region, pad or patterns or In the case described as being formed "down / below / under / lower", the meaning is that each layer (film), region, pad, pattern or structure is a direct substrate, each layer (film), region, It may be interpreted as being formed in contact with the pad or patterns, or may be interpreted as another layer (film), another region, another pad, another pattern, or another structure being additionally formed therebetween. Therefore, the meaning should be determined by the technical spirit of the invention.

1 is a cross-sectional view illustrating a capacitor of a semiconductor device in accordance with an embodiment.

As shown in FIG. 1, the capacitor of the semiconductor device according to the embodiment includes a lower electrode 120, an upper electrode 130 formed on the lower electrode 120, the upper electrode 130, and the lower electrode ( The dielectric layer pattern 125 may be formed between the spacers 120 and the spacers 140 covering sidewalls of the upper electrode 130.

The pad nitride layer 110 is formed on the substrate 100 on which the lower structure is formed.

The lower electrode 120 is formed in a portion of the pad nitride layer 110.

The lower electrode 120 may be made of at least one material selected from the group consisting of at least Ti, TiN, Ta, TaN, Cu, Al, Pt, Ru, Ir, Rh, Os, and alloys thereof.

The lower electrode 120 may be formed of a single layer structure or may have a multilayer structure.

The dielectric film pattern 125 is formed on the lower electrode 120. The dielectric film pattern 125 is made of a high-K insulating material.

The dielectric layer pattern 125 covers the entire upper surface of the lower electrode 120.

A step may be formed on the top surface of the dielectric film pattern 125.

An upper electrode 130 is formed on the dielectric layer pattern 125.

The upper electrode 130 may be formed on the top of the dielectric layer pattern 125 having a relatively high step.

The upper electrode 130 may be made of at least one material selected from the group consisting of at least Ti, TiN, Ta, TaN, Cu, Al, Pt, Ru, Ir, Rh, Os, and alloys thereof.

The spacer 140 is formed to contact a portion of the dielectric layer pattern 125 and cover sidewalls of the upper electrode 130.

The dielectric layer pattern 125 in contact with the spacer 140 may be a sidewall of the step portion and a lower portion of the dielectric layer pattern 125.

The spacer 140 is made of an insulating film, and the spacer 140 is made of a low-K (low dielectric constant) dielectric material.

The spacer 140 is for reducing parasitic capacitance generated between the edge of the upper electrode 130 and the lower electrode 120.

A capacitor having the above structure is formed on the substrate 100, and the first insulating layer 150 and the second insulating layer 160 are sequentially formed on the substrate 100 to cover the capacitor.

The first insulating layer 150 may be a capping insulator to protect the capacitor. For example, the first insulating layer 150 may be a silicon nitride layer.

The second insulating layer 160 is formed flat on the first insulating layer 150.

The first wiring 171 and the second wiring 172 contacting the upper electrode 130 and the second wiring 172 penetrating the second insulating film 160 and the second insulating film 160 are in contact with each other. Formed.

The first wiring 171 and the second wiring 172 may be made of copper wiring or aluminum and tungsten.

2 to 9 are cross-sectional views illustrating a process of manufacturing a capacitor of a semiconductor device according to an embodiment.

As shown in FIG. 2, the pad nitride film 110, the lower electrode film 120a, the dielectric film 125a, and the upper electrode film 130a are sequentially formed on the substrate 100 on which the lower structure is formed.

The pad nitride layer 110 may be used as an etch stop layer or a film for protecting the capacitor when a via hole for interlayer connection is formed.

The lower electrode layer 120a and the upper electrode layer 130a may be made of a metal material or polysilicon.

The dielectric layer 125a may be made of a high dielectric constant material.

As shown in FIG. 3, a first photoresist pattern 191 for patterning the upper electrode layer 130a is formed on the upper electrode layer 130a.

Thereafter, the upper electrode layer 130a is etched using the first photoresist pattern 191 as a mask to form the upper electrode 130.

A step may be formed in the dielectric layer 125a by overetching the upper electrode layer 130a to etch the dielectric layer 125a under the upper electrode layer 130a by a predetermined thickness.

The first photoresist pattern 191 is removed.

As shown in FIG. 4, a third insulating layer 140a made of a low dielectric constant material is formed on the entire surface of the substrate 100 on which the upper electrode 130 is formed.

The third insulating layer 140a may be, for example, an oxide layer.

As shown in FIG. 5, the entire surface of the third insulating layer 140a is dry-etched to form spacers 140 on sidewalls of the upper electrode 130.

Dry etching the entire surface of the third insulating layer 140a may cause anisotropic etching, and thus the third insulating layer 140a may not be etched, but remains in contact with a portion of the dielectric layer 125a on the sidewall of the upper electrode 130. The spacer 140 is formed.

Since the spacer 140 is an insulating film having a low dielectric constant, parasitic capacitance generated between the edge of the upper electrode 130 and the lower electrode may be reduced.

6 and 7, a second photoresist pattern 192 is formed on the dielectric layer 125a to cover the upper electrode 130 and the spacer 140.

The dielectric layer 125a and the lower electrode layer 120a are etched using the second photoresist pattern 192 as a mask to form the dielectric layer pattern 125a and the lower electrode 120.

The dielectric layer pattern 125 and the lower electrode 120 are formed larger than the upper electrode 130 to secure a contact area with the second wiring 172 that applies an electrical signal to the lower electrode 120. do.

Thereafter, the second photoresist pattern 192 is removed.

As shown in FIG. 8, the first insulating layer 150 is formed on the entire surface of the substrate 100 on which the lower electrode 120, the dielectric layer pattern 125, the upper electrode 130, and the spacer 140 are formed. To form.

Thereafter, a second insulating layer 160 is formed on the first insulating layer 150.

The first insulating film 150 and the second insulating film 160 include at least one of an oxide film and a nitride film.

As illustrated in FIG. 9, the second insulating layer 160 and the first insulating layer 150 are selectively etched to form vias that expose a portion of the upper electrode 130 and a portion of the lower electrode 120. The metal is filled in each via to form a first wiring 171 in contact with the upper electrode 130 and a second wiring 172 in contact with the lower electrode 120, respectively.

The embodiment has the effect of reducing the parasitic capacitance generated at the edge of the capacitor electrode to improve the capacitor characteristics and maintain the capacitance value to improve the semiconductor device characteristics and improve the yield.

Although described above with reference to the embodiments, which are merely examples and are not intended to limit the present invention. Those skilled in the art to which the present invention pertains are not exemplified above without departing from the essential characteristics of the present invention. It will be appreciated that many variations and applications are possible. For example, each component specifically shown in the embodiment of the present invention can be modified. And differences relating to such modifications and applications will have to be construed as being included in the scope of the invention defined in the appended claims.

1 is a cross-sectional view illustrating a capacitor of a semiconductor device in accordance with an embodiment.

2 to 9 are cross-sectional views illustrating a process of manufacturing a capacitor of a semiconductor device according to an embodiment.

Claims (8)

A lower electrode formed on the substrate; A dielectric film pattern formed on the lower electrode; An upper electrode formed on a portion of the dielectric film pattern; And And a spacer formed on sidewalls of the upper electrode and having a dielectric constant smaller than that of the dielectric layer pattern. The method of claim 1, An insulating layer covering the lower electrode, the dielectric layer pattern, the upper electrode, and the spacer; And And a second wiring connected to the upper electrode and the second wiring connected to the upper electrode through the insulating film. The method of claim 1, The upper surface of the spacer has a top and a bottom, the upper electrode is formed on the top, the spacer is a semiconductor device capacitor, characterized in that the contact with the sidewall and the bottom portion between the top and bottom. Sequentially forming a lower electrode film, a dielectric film, and an upper electrode film on a substrate; Patterning the upper electrode layer to form an upper electrode; Forming a spacer on sidewalls of the upper electrode; And Patterning the dielectric film and the lower electrode film to form a dielectric film pattern and a lower electrode larger than the spacer and the upper electrode. The method of claim 4, wherein In forming the spacer, Applying a dielectric material covering the upper electrode and having a dielectric constant smaller than that of the dielectric film; And Dry etching the dielectric material to form the spacers in contact with the sidewalls of the upper electrode and a portion of the dielectric film that extends from the sidewalls. The method of claim 4, wherein And the spacer is formed of an oxide film. The method of claim 4, wherein After forming the lower electrode, Forming a first insulating film and a second insulating film formed on an entire surface of the substrate; And forming a first wiring and a second wiring penetrating the second insulating film and connected to a portion of the upper electrode and the lower electrode, respectively. The method of claim 4, wherein In the forming of the upper electrode, And overetching a portion of the dielectric film.

Images