KR20090049696A - Reference voltage generation circuit and circuit for generating internal voltage of semiconductor memory apparatus using the same - Google Patents

Reference voltage generation circuit and circuit for generating internal voltage of semiconductor memory apparatus using the same Download PDF

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Publication number
KR20090049696A
KR20090049696A KR1020070115901A KR20070115901A KR20090049696A KR 20090049696 A KR20090049696 A KR 20090049696A KR 1020070115901 A KR1020070115901 A KR 1020070115901A KR 20070115901 A KR20070115901 A KR 20070115901A KR 20090049696 A KR20090049696 A KR 20090049696A
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South Korea
Prior art keywords
voltage
external
level
driving
enabled
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KR1020070115901A
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Korean (ko)
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강길옥
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020070115901A priority Critical patent/KR20090049696A/en
Publication of KR20090049696A publication Critical patent/KR20090049696A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators

Abstract

According to an embodiment of the present invention, a voltage sensing unit for enabling a first sensing signal and a second sensing signal sequentially as an external voltage rises, and driving the external voltage by dropping the external voltage whenever the first and second sensing signals are enabled. A driving voltage generator for outputting a voltage and a reference voltage generator for receiving the driving voltage to generate a reference voltage of a target level.

External voltage, internal voltage, reference voltage

Description

Reference Voltage Generation Circuit and Circuit for Generating Internal Voltage of Semiconductor Memory Apparatus Using the Same}

The present invention relates to a semiconductor memory device, and more particularly, to a reference voltage generator circuit and an internal voltage generator circuit of the semiconductor memory device using the same.

The semiconductor memory device operates by receiving an external voltage. However, since the external voltage has a problem that the level may be changed by the influence of noise, an internal voltage having a constant voltage level is used inside the semiconductor memory device. 1 is a block diagram of an internal voltage generation circuit for generating an internal voltage.

The first reference voltage generator 10 receives the external voltage VDD as a driving voltage to generate the first reference voltage Vref1.

The second reference voltage generator 20 receives an external voltage VDD as a driving voltage and receives the first reference voltage Vref1 to drop the level of the first reference voltage Vref1 internally so as to lower the second reference voltage. Output as (Vref2).

The internal voltage generator 30 generates an internal voltage V_int corresponding to the level of the second reference voltage Vref2.

As illustrated in FIG. 2, the first reference voltage generator 10 may include a first comparator com1, a first MOS transistor P1, first to third resistors R1, R2, and R3. First and second bipolar junction transistors (BJT1, BJT2).

The first comparator com1 compares the first divided voltage V_div1 and the second divided voltage V_div2 and outputs a first comparison signal com_s1. The first MOS transistor P1 applies an external voltage VDD to the first and second resistors R1 and R2 in response to the first comparison signal com_s1. The first division voltage V_div1 is generated according to the impedance distribution ratio of the first resistance element R1 and the first bipolar junction transistor BJT1. The second divided voltage V_div2 is generated according to the distribution ratio of the impedance of the third resistance element R3 and the second bipolar junction transistor BJT2 and the impedance of the second resistance element R2.

As illustrated in FIG. 3, the second reference voltage generator 20 includes a second comparator com2, a second MOS transistor P2, and fourth and fifth resistors R4 and R5.

The second comparator com2 compares the voltage level of the first reference voltage Vref with node A and outputs a second comparison signal com2. The second MOS transistor P2 applies an external voltage VDD to the node A in response to the second comparison signal com2. The fourth resistor element R4 and the fifth resistor element R5 are connected in series between the node A and the ground terminal VSS, and the second reference voltage Vref2 is connected to the fourth resistor element R4. The node R4 and the fifth resistor R5 are output from the node connected thereto.

The first reference voltage generator 10 and the second reference voltage generator 20 configured as described above have the first reference voltage Vref1 and the second output voltage corresponding to each output voltage as the external voltage VDD increases. The reference voltage Vref2 level becomes high. The reason is that the first reference voltage generator 10 and the second reference voltage generator 20 structurally output an external voltage VDD through the first and second MOS transistors P1 and P2. to be. In the case of the first reference voltage generator 10, as the output terminal of the first MOS transistor P1 is directly connected to the output terminal of the first reference voltage generator 10, the external voltage VDD level is increased. The first reference voltage Vref1 is increased. In addition, in the case of the second reference voltage generator 20, an output terminal of the second MOS transistor P2 is connected to an output terminal of the second reference voltage generator 20 through the fourth resistor element R4. The second reference voltage Vref2 is affected by the external voltage VDD. In addition, the second reference voltage generator 20 generates the second reference voltage Vref2 based on the first reference voltage Vref1 having a higher level as the external voltage VDD increases. The level of the second reference voltage Vref2 is greater than the level of the first reference voltage Vref1. Accordingly, the internal voltage generator 30 generating the internal voltage V_int based on the second reference voltage Vref2 generates the internal voltage V_int at a level higher than a target level so that a semiconductor memory device may be used. Prevents normal operation

The present invention has been made to solve the above-described problem, and an object thereof is to provide a reference voltage generation circuit that generates a reference voltage having a constant voltage level even when an external voltage is high. It is also an object of the present invention to provide an internal voltage generation circuit for generating an internal voltage of a target level by generating a reference voltage of a constant voltage level.

According to an embodiment of the present invention, a reference voltage generation circuit may include a voltage detector configured to sequentially enable a first sensing signal and a second sensing signal as an external voltage increases, and the first and second sensing signals may be enabled. A driving voltage generator for dropping the external voltage and outputting the driving voltage as a driving voltage each time; and a reference voltage generator for generating the reference voltage at a target level by receiving the driving voltage.

According to another embodiment of the present invention, a reference voltage generation circuit may include a voltage detector configured to generate an enabled sensing signal when an external voltage is higher than a predetermined voltage level, and drop the external voltage when the sensing signal is enabled to drive a driving voltage. And a driving voltage generator configured to output the driving voltage, and a reference voltage generator configured to receive the driving voltage and generate a reference voltage at a target level.

The internal voltage generation circuit using the reference voltage generation circuit according to the embodiment of the present invention receives a driving voltage generating circuit and a driving voltage applied to drop the external voltage and output the driving voltage when the external voltage is higher than a predetermined target level. A first reference voltage generator configured to generate a first reference voltage, a second reference voltage generator configured to operate by receiving the driving voltage and generate the second reference voltage based on the first reference voltage, and the second reference And an internal voltage generator configured to receive a voltage and generate an internal voltage.

The reference voltage generation circuit according to the present invention has an effect of increasing the stability of the semiconductor memory device by generating a reference voltage having a constant voltage level even when the external voltage level increases. In addition, by generating an internal voltage using the reference voltage generation circuit, malfunction of the semiconductor memory device may be prevented, thereby improving operation reliability and stability.

As illustrated in FIG. 4, the internal voltage generation circuit of the semiconductor memory device according to the embodiment of the present invention may include a voltage detector 100, a driving voltage generator 200, a first reference voltage generator 10, and a first voltage generator. And a second reference voltage generator 20 and an internal voltage generator 30.

The voltage detector 100 senses an external voltage VDD level to generate a first sensing signal DET1 and a second sensing signal DET2.

The driving voltage generator 200 generates a driving voltage V_drv in response to the first and second sensing signals DET1 and DET2.

The first reference voltage generator 10 receives the driving voltage V_drv to generate a first reference voltage Vref1.

The second reference voltage generator 20 generates the second reference voltage Vref2 by distributing the driving voltage V_drv based on the first reference voltage Vref1.

The internal voltage generator 30 receives the second reference voltage Vref2 to generate an internal voltage V_int.

As illustrated in FIG. 5, the voltage detector 100 includes a voltage divider 110 and a sense signal generator 120.

The voltage divider 110 divides the external voltage VDD by a distribution ratio according to a resistance ratio to generate a first divided voltage V_div1 and a second divided voltage V_div2.

The voltage divider 110 includes first to third resistance elements R11, R12, and R13. The first to third resistance elements R11, R12, and R13 are connected between an external voltage terminal VDD and a ground terminal VSS to which an external voltage VDD is applied in series. The first division voltage V_div1 is output from a node to which the first resistance element R11 and the second resistance element R12 are connected. The second division voltage V_div2 is output from a node to which the second resistance element R12 and the third resistance element R13 are connected.

When the external voltage VDD is higher than the first predetermined voltage level, the sensing signal generator 120 enables the first sensing signal DET1 by the first divided voltage V_div1 and external voltage VDD. When the voltage exceeds the second predetermined voltage level, the second detection signal DET2 is enabled by the second division voltage V_div2. In this case, the second predetermined voltage level is higher than the first predetermined voltage level.

The detection signal generator 120 includes a first signal generator 121 and a second signal generator 122.

When the external voltage VDD is higher than the first predetermined voltage level, the first signal generator 121 enables the first detection signal DET1 by the first division voltage V_div1.

When the external voltage VDD is higher than the second predetermined voltage level, the second signal generator 122 enables the second detection signal DET2 by the second division voltage V_div2.

The first signal generation unit 121 and the second signal generation unit 122 differ only in the type of the applied voltage and the output signal, but have the same internal configuration, so only the internal circuit of the first signal generation unit 121 is different. Explain.

As illustrated in FIG. 6, the first signal generator 121 includes first to fourth transistors P11, N11, P12, and N12. The first transistor P11 has a ground terminal VSS connected to a gate and an external voltage VDD applied to a source. In the second transistor N11, a first division voltage V_div1 is applied to a gate, a drain of the first transistor P11 is connected to a drain, and a ground terminal VSS is connected to a source. The third transistor P12 is connected to a node connected to the first transistor P11 and the second transistor N11 to a gate thereof, and receives an external voltage VDD from a source. The fourth transistor N11 has a gate connected to a node connected to the first transistor P11 and a second transistor N11, a drain connected to a drain of the third transistor P12, and a ground terminal ( VSS) is connected. In this case, the first sensing signal DET1 is output from a node to which the third transistor P12 and the fourth transistor N12 are connected.

As shown in FIG. 7, the driving voltage generator 200 includes a first voltage output unit 210, a second voltage output unit 220, and a third voltage output unit 230.

The first voltage output unit 210 outputs the external voltage VDD as the driving voltage V_drv when the first sensing signal DET1 is disabled.

The first voltage output unit 210 includes a fifth transistor P21. The fifth transistor P21 receives the first sensing signal DET1 at a gate, receives an external voltage VDD at a source, and a drain thereof is an output terminal of the first voltage output unit 210.

The second voltage output unit 220 drops the external voltage VDD from when the first sensing signal DET1 is enabled to high until the second sensing signal DET2 is enabled. It outputs as the said drive voltage V_drv.

The second voltage output unit 220 includes a first inverter IV21, a NAND gate ND21, a sixth transistor P22, and a fourth resistor R21. The first inverter IV21 receives the second sensing signal DET2. The NAND gate ND21 receives an output signal of the first inverter IV21 and the first sensing signal DET1. The sixth transistor P22 receives an output signal of the NAND gate ND21 to a gate and receives an external voltage VDD to a source. One end of the fourth resistor R21 is connected to the drain of the sixth transistor P22 and the other end is an output terminal of the second voltage output unit 220.

When the second detection signal DET2 is enabled high, the third voltage output unit 230 drops the external voltage VDD and outputs the external voltage VDD as the driving voltage V_drv.

The third voltage output unit 230 includes a second inverter IV22, a seventh transistor P23, and a fifth resistor element R22. The second inverter IV22 receives the second detection signal DET2. The seventh transistor P23 receives an output signal of the second inverter IV22 at a gate and an external voltage VDD is applied to a source. The fifth resistor element R22 has one end connected to a drain of the seventh transistor P23, and the other end is an output terminal of the third voltage output unit 230. Each output terminal of the first voltage output unit 210, the second voltage output unit 220, and the third voltage output unit 230 is connected to one node, and the driving voltage V_drv is Is output.

The internal voltage generation circuit of the semiconductor memory device according to the embodiment configured as described above operates as follows.

Referring to FIG. 5, the voltage divider 110 divides the external voltage VDD to generate a first divided voltage V_div1 and a second divided voltage V_div2. In this case, the first division voltage V_div1 is higher than the second division voltage V_div2.

When the external voltage VDD is higher than the first predetermined voltage level, the first signal generator 121 enables the first sensing signal DET1 by the first divided voltage V_div1.

The second signal generator 122 enables the second sensing signal DET2 by the second divided voltage V_div2 when the external voltage VDD is higher than the second predetermined voltage level.

As a result, the first sensing signal DET1 is enabled at an external voltage VDD having a lower level than the second sensing signal DET2.

An operation in which the first signal generator 121 enables the first detection signal DET1 will be described in more detail with reference to FIG. 6. In this case, since the second signal generator 122 has the same configuration as the first signal generator 121, the operation thereof is not different. Therefore, the description of the operation of the second signal generator 122 is replaced with the description of the operation of the first signal generator 121.

When the first division voltage V_div1 is not at a voltage level at which the second transistor N11 is turned on, that is, when the external voltage VDD is lower than the first predetermined voltage level, the first transistor P11 is disposed. The external voltage VDD is applied to the gate of the fourth transistor N11. When the external voltage VDD is applied to the gate of the fourth transistor N11, the fourth transistor N11 connects the output terminal of the first signal generator 121 to the ground terminal VSS. That is, when the external voltage VDD is lower than the first predetermined voltage level, the first signal generator 121 outputs the first detection signal DET1 disabled to a low level.

When the first division voltage V_div1 becomes a voltage level capable of turning on the second transistor N11, that is, when the external voltage VDD is higher than the first predetermined voltage level, the second transistor N11. The ground terminal VSS is connected to the gate of the third transistor P12 through the gate. The third transistor P12 having the ground terminal VSS connected to the gate is turned on and outputs an external voltage VDD as the first sensing signal DET1. That is, the first sensing signal DET1 is enabled at a high level.

An operation of the driving voltage generator 200 receiving the first and second sensing signals DET1 and DET2 will be described with reference to FIG. 7.

The first voltage output unit 210 outputs an external voltage VDD as a driving voltage V_drv when the first sensing signal DET1 is disabled at a low level. That is, in the embodiment of the present invention, when the external voltage VDD level is the lowest, that is, when the external voltage VDD is lower than the first predetermined voltage level, the external voltage VDD is output as the driving voltage V_drv. The first voltage output unit 210 is turned off when the first sensing signal DET1 is enabled at a high level. That is, the fifth transistor P21 is turned off and does not output the external voltage VDD as the driving voltage V_drv.

The second voltage output unit 220 drops the external voltage VDD from when the first sensing signal DET1 is enabled to the high level until the second sensing signal DET2 is enabled to the high level. And output as the driving voltage V_drv. That is, when the fifth transistor P21 of the first voltage output unit 210 is turned off, the sixth transistor P22 of the second voltage output unit 220 is turned on and the third voltage output unit 230 is turned on. When the seventh transistor P23 is turned on, the sixth transistor P22 is turned off. When the sixth transistor P22 is turned on, the second voltage output unit 220 operates.

When the second detection signal DET2 is enabled at a high level, the third voltage output unit 230 drops the external voltage VDD and outputs the driving voltage V_drv. In this case, the resistance value of the fifth resistance element R22 is greater than that of the fourth resistance element R21, so that the third voltage output part is higher than the level at which the second voltage output part 220 drops the external voltage VDD. The level at which 230 drops the external voltage VDD is high.

The driving voltage V_drv level described above has the same result as that of FIG. 8 as the external voltage VDD rises.

Referring to FIG. 8, the external voltage VDD rises with a constant slope.

The driving voltage V_drv according to the present invention rises with the same slope as the external voltage VDD when the external voltage VDD is lower than the first predetermined voltage V1 level. That is, the first voltage output unit 210 outputs the external voltage VDD as the driving voltage V_drv.

When the external voltage VDD is higher than the first predetermined voltage V1 level, the driving voltage V_drv is lowered and then raised again. That is, the second voltage output unit 220 drops the external voltage VDD and outputs the external voltage VDD as the driving voltage V_drv. However, as the level of the external voltage VDD continues to increase, the level of the driving voltage V_drv, which was first dropped, increases again.

When the external voltage VDD becomes higher than the second predetermined voltage V2 level, the driving voltage V_drv whose level is increased again becomes lower and then becomes higher again. That is, the third voltage output unit 230 drops the external voltage VDD and outputs the external voltage VDD as the driving voltage V_drv. However, as the external voltage level continues to increase, the driving voltage V_drv level, which has fallen second, is increased again.

The present invention includes a plurality of voltage output units for generating a plurality of sensing signals according to the external voltage level, and accordingly dropping the external voltage level, thereby outputting a driving voltage swinging to a constant level from an external voltage level desired by a designer or a user. You can get it. In addition, by lowering the level at which the external voltage drops, the swing width of the driving voltage can be reduced, thereby obtaining a constant level of the driving voltage. Therefore, the voltage detector 100 and the driving voltage generator 200 illustrated in FIG. 4 may be referred to as a driving voltage generator circuit.

The first reference voltage generator 10, which receives the driving voltage V_drv and generates the first reference voltage Vref1, has a slope of the first reference voltage Vref1 that has increased as the external voltage VDD increases. The first reference voltage Vref1 rising with a lower slope is output. That is, the change amount of the first reference voltage Vref1 according to the present invention is smaller than the change amount of the first reference voltage Vref1 according to the prior art. The first reference voltage Vref1 generated according to the present invention is more stable than the first reference voltage Vref1 according to the prior art.

Referring to FIG. 4, the second reference voltage generator 20 receives the first reference voltage Vref1 having a small level change and outputs a second reference voltage Vref2 having a more stable level than a conventional level. The internal voltage generator 30 receiving the second reference voltage Vref2 generates an internal voltage V_int having a stable level. Therefore, the semiconductor memory device using the stable level of the internal voltage V_int is guaranteed stable operation even when the external voltage increases.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above are exemplary in all respects and are not intended to be limiting. You must do it. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of an internal voltage generation circuit of a semiconductor memory device of the prior art;

2 is a detailed circuit diagram of a first reference voltage generator of FIG. 1;

3 is a detailed circuit diagram of a second reference voltage generator of FIG. 1;

4 is a block diagram of an internal voltage generation circuit of a semiconductor memory device according to an embodiment of the present invention;

5 is a circuit diagram of a voltage sensing unit of FIG. 4;

6 is a detailed circuit diagram of a first signal generator of FIG. 5;

7 is a detailed circuit diagram of a driving voltage generator of FIG. 4;

8 is a graph comparing a reference voltage according to an embodiment of the present invention with a conventional reference voltage.

<Description of the symbols for the main parts of the drawings>

10: first reference voltage generator 20: second reference voltage generator

30: internal voltage generation unit 100: voltage detection unit

200: driving voltage generator

Claims (18)

A voltage sensing unit that sequentially enables the first sensing signal and the second sensing signal as the external voltage increases; A driving voltage generator for dropping the external voltage and outputting the external voltage as a driving voltage each time the first and second sensing signals are enabled; And And a reference voltage generator configured to receive the driving voltage to generate a reference voltage at a target level. The method of claim 1, The voltage detector And enable the first sensing signal when the external voltage level is higher than a first predetermined voltage level, and enable the second sensing signal when the external voltage level is higher than a second predetermined voltage level. A reference voltage generation circuit of a semiconductor memory device. The method of claim 2, And the second predetermined voltage is higher than the first predetermined voltage level. The method of claim 3, wherein The voltage detector A voltage divider configured to divide the external voltage to produce a first divided voltage and a second divided voltage, and Outputting the first sensing signal enabled by the first division voltage when the external voltage is higher than the first predetermined voltage level; and second division voltage when the external voltage is higher than the second predetermined voltage level. And a sense signal generator configured to output the second sense signal enabled by the second memory signal. The method of claim 4, wherein The voltage divider And the first division voltage is higher than the second division voltage level. The method of claim 5, wherein The detection signal generator A first signal generator configured to generate the first sense signal enabled by the first divided voltage when the external voltage is higher than the first predetermined voltage level, and And a second signal generator configured to generate the second sensed signal enabled by the second divided voltage when the external voltage is higher than the second predetermined voltage level. Circuit. The method of claim 1, The driving voltage generator When both of the first and second sensing signals are disabled, the external voltage is output as the driving voltage, and the first or second sensing signals are enabled or both of the first and second sensing signals are enabled. And dropping the external voltage to output the driving voltage as the driving voltage. The method of claim 7, wherein And the second sensed signal is enabled when the external voltage level is higher than the first sensed signal. The method of claim 8, The driving voltage generator A first voltage output unit configured to output the external voltage as the driving voltage when the first sensing signal is disabled; A second voltage output unit for dropping the external voltage and outputting it as the driving voltage from when the first sensing signal is enabled to when the second sensing signal is enabled, and And a third voltage output unit configured to drop the external voltage and output the driving voltage when the second sensing signal is enabled, and output the driving voltage as the driving voltage. A voltage detector configured to generate an enabled sensing signal when the external voltage becomes higher than a preset voltage level; A driving voltage generator configured to drop the external voltage and output the driving voltage when the sensing signal is enabled; And And a reference voltage generator configured to receive the driving voltage to generate a reference voltage at a target level. The method of claim 10, The voltage detector A voltage divider for dividing the external voltage to generate a divided voltage; and And a sensing signal generator configured to generate the sensing signal enabled by the division voltage when the external voltage is higher than the predetermined voltage level. The method of claim 10, The driving voltage generator A first voltage output unit configured to output the external voltage as the driving voltage when the sensing signal is disabled, and And a second voltage output unit configured to drop the external voltage and output the driving voltage as the driving voltage when the sensing signal is enabled. A driving voltage generation circuit for dropping the external voltage and outputting the external voltage as a driving voltage when the external voltage becomes higher than a predetermined target level; A first reference voltage generator configured to receive the driving voltage to generate a first reference voltage; A second reference voltage generator configured to operate by receiving the driving voltage and generate the second reference voltage based on the first reference voltage; And And an internal voltage generator configured to receive the second reference voltage and generate an internal voltage. The method of claim 13, The driving voltage generation circuit A voltage detector configured to detect the external voltage level to generate a plurality of sensing signals; And a driving voltage generator configured to generate a driving voltage having a predetermined level in response to the plurality of sensing signals. The method of claim 14, The voltage detector And the number of sense signals enabled among the plurality of sense signals increases as the external voltage level increases. The method of claim 15, The driving voltage generator And increasing the drop level of the external voltage as the number of enabled sensing signals of the plurality of sensing signals increases to output the dropped external voltage as the driving voltage. The method of claim 13, The first reference voltage generator And the first reference voltage level is applied to the driving voltage so that the first reference voltage level is not increased. The method of claim 13, The second reference voltage generator And a voltage divider, wherein the driving voltage is applied to the voltage divider at the first reference voltage level, and the voltage divider divides the applied voltage and outputs the voltage as the second reference voltage. Internal voltage generation circuit of the device.
KR1020070115901A 2007-11-14 2007-11-14 Reference voltage generation circuit and circuit for generating internal voltage of semiconductor memory apparatus using the same KR20090049696A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101039868B1 (en) * 2009-07-02 2011-06-09 주식회사 하이닉스반도체 Generating circuit and control method for internal voltage of semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101039868B1 (en) * 2009-07-02 2011-06-09 주식회사 하이닉스반도체 Generating circuit and control method for internal voltage of semiconductor memory device

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