KR20090048180A - Method of forming a isolation layer in semiconductor device - Google Patents

Method of forming a isolation layer in semiconductor device Download PDF

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Publication number
KR20090048180A
KR20090048180A KR1020070114443A KR20070114443A KR20090048180A KR 20090048180 A KR20090048180 A KR 20090048180A KR 1020070114443 A KR1020070114443 A KR 1020070114443A KR 20070114443 A KR20070114443 A KR 20070114443A KR 20090048180 A KR20090048180 A KR 20090048180A
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KR
South Korea
Prior art keywords
film
device isolation
insulating film
forming
insulating
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KR1020070114443A
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Korean (ko)
Inventor
심정명
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주식회사 하이닉스반도체
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Priority to KR1020070114443A priority Critical patent/KR20090048180A/en
Publication of KR20090048180A publication Critical patent/KR20090048180A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

The present invention provides a semiconductor substrate including a trench, the semiconductor substrate having a tunnel insulating film, a first conductive film, and a device isolation mask pattern formed on the active region, filling the inside of the trench with the first insulating film and the second insulating film, and a second insulating film. Forming a protective film along the surface of the substrate, forming a third insulating film on top of the protective film, performing a planarization process to expose the device isolation mask pattern, removing the third insulating film, and oxidizing the protective film. It consists of the element isolation film formation method of the semiconductor element containing.

Device Separation, EFH, Nitride, Oxide, Treatment

Description

Method of forming a isolation layer in semiconductor device

The present invention relates to a method of forming a device isolation layer of a semiconductor device, and in particular, a method of forming a device isolation layer of a semiconductor device capable of easily controlling the effective field oxide height (EFH) of the device isolation layer by forming a protective film during the formation process of the device isolation layer. It is about.

As the degree of integration of semiconductor devices increases, the width of device isolation regions and active regions decreases. Referring to the flash device as an example, the flash device includes a plurality of strings. Each of the strings includes memory cells connected in series, a drain select transistor (DST), and a source select transistor (SST). Among them, the memory cell includes a floating gate in which data is stored and a control gate for applying a voltage.

On the other hand, each string is arranged in parallel to each other, the device isolation layer is formed in the device isolation region between the string to electrically insulate between the string and the string. In this case, an isolation layer is formed in the isolation region. As described above, the device isolation layer electrically insulates between the strings, but also affects the capacitance between the control gate and the floating gate. That is, as the height of the device isolation layer increases, the electrical insulation characteristics between neighboring devices improve, but the capacitance between the control gate and the floating gate may decrease. Accordingly, the height of the device isolation layer must be appropriately adjusted. The height of the device isolation layer is referred to as an effective field oxide height (EFH).

In general, the EFH adjusting process of the device isolation film is performed by filling the insulating film for device isolation film in the trench and then performing an etching process. However, as the degree of integration of semiconductor devices increases, the width of device isolation films also decreases, making it difficult to uniformly adjust EFH of a plurality of device isolation films.

SUMMARY OF THE INVENTION An object of the present invention is to form first and second insulating films in a device isolation trench, and to form a protective film of a material having a different etching selectivity from the second insulating film along the surface of the second insulating film for subsequent EFH control. During the etching process, the EFH of the device isolation layer may be adjusted to a uniform height by preventing over etching.

The present invention relates to a method of forming a device isolation film of a semiconductor device, and comprises a semiconductor substrate including a trench and having a tunnel insulating film, a first conductive film, and a device isolation mask pattern formed on an active region. The inside of the trench is filled with a first insulating film and a second insulating film. A protective film is formed along the surface of the second insulating film. A third insulating film is formed on the protective film. The planarization process is performed to reveal the device isolation mask pattern. The third insulating film is removed. A device isolation film forming method of a semiconductor device comprising the step of oxidizing a protective film.

The protective film is formed of a film having a different etching selectivity from the second insulating film, and the protective film is formed of a nitride film. The protective film is formed to a thickness of 10 kPa to 200 kPa.

The first insulating film is formed of a spin on dielectric (SOD) film, and the SOD film is formed of a polysilazane (PSZ) film.

The second insulating film is formed of an HDP film, and the third insulating film is formed of an HDP film. At this time, the HDP film is formed by injecting a mixed gas of SiH 4 , O 2 , He and H 2 , SiH 4 is 10sccm to 200sccm, O 2 is 10sccm to 500sccm, H 2 is 10sccm to 1000sccm, H 2 is 10sccm to 1000sccm Inject at the dose.

The HDP film is formed by applying low frequency (LF) of 10W to 10000W and high frequency (HF) of 10W to 10000W.

The step of oxidizing the protective film is carried out by a treatment process, which converts the protective film into an oxidative protective film.

The method may further include performing a cleaning process prior to performing the treatment process.

According to the present invention, the first and second insulating films are formed in the isolation trench, and a protective film of a material having a different etching selectivity from the second insulating film is formed along the surface of the second insulating film, so that the etching process for subsequent EFH control is performed. By preventing etching, the EFH of the device isolation layer may be adjusted to a uniform height. As a result, deterioration in electrical characteristics of the semiconductor device can be prevented, and reliability can be improved.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1A to 1H are cross-sectional views for illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.

Referring to FIG. 1A, a flash device is described as follows.

The tunnel insulating layer 102, the first conductive layer 104 for the floating gate, and the device isolation mask pattern 106 are sequentially formed on the semiconductor substrate 100. The tunnel insulating film 102 may be formed of an oxide film, and the first conductive film 104 may be formed of a polysilicon film. Preferably, the first conductive film 104 may be formed by stacking an undoped polysilicon film and a doped polysilicon film. The device isolation mask pattern 106 may form a nitride film, and a buffer layer (not shown) that protects the surface of the first conductive film 104 between the first conductive film 104 and the device isolation mask pattern 106. ) May be further formed.

Subsequently, an etching process is performed on the device isolation mask pattern 106 to sequentially pattern the first conductive layer 104 and the tunnel insulating layer 102, and remove a portion of the exposed semiconductor substrate 100 to form a trench 107. ).

Referring to FIG. 1B, in order to prevent generation of voids or seams due to an increase in the aspect ratio of the trench 107, it is preferable to sequentially fill the inside of the trench 107 with a plurality of insulating films. For this purpose, the first insulating film 108 for the device isolation film is filled in the bottom surface of the trench 107. Specifically, it is preferable that the first insulating film 108 form a flowable spin on dielectric (SOD) film. For example, the SOD film may be formed of a PSZ (polysilazane) film. As such, after the bottom surface of the trench 107 is filled with the first insulating film 108, the second insulating film 110 for device isolation film is formed on the semiconductor substrate 100 including the first insulating film 108. It is preferable that the second insulating film 110 form a high density plasma (HDP) film having physically denser characteristics than the first insulating film 108. Specifically, the HDP film may be formed by injecting a mixed gas of SiH 4 , O 2 , He, and H 2 in order to suppress the occurrence of overhang on the trench 107. For example, SiH 4 may be injected in an amount of 10 sccm to 200 sccm, O 2 to 10 sccm to 500 sccm, H 2 to 10 sccm to 1000 sccm, and H 2 to 10 sccm to 1000 sccm. In addition, the low frequency (LF) may add 10W to 10000W, and the high frequency (HF) may add 10W to 10000W.

Subsequently, an etching process for adjusting the EFH of the device isolation layer is performed. Specifically, the EFH adjustment process may be performed by lowering the height of the second insulating layer 110 formed in the trench 107 region. For example, it is preferable to perform an etching process so that the upper portion of the second insulating film 110 formed in the trench 107 reaches a point at which half of the first conductive film 104 is reached. In addition, since the thickness of the second insulating layer 110 formed on the upper and sidewalls of the device isolation mask pattern 106 may be reduced during the EFH control etching process, the upper width W of the trench 107 may be widened.

Referring to FIG. 1C, the passivation layer 112 is formed along the surface of the second insulating layer 110. The protective layer 112 serves to protect the second insulating layer 110 during the subsequent etching process of the third insulating layer, thereby maintaining the EFH of the device isolation layer uniformly. To this end, the passivation layer 112 may be formed of a material having a different etching selectivity from that of the second insulating layer 110. For example, the protective film 112 may be formed of a nitride film and may have a thickness of 10 kPa to 200 kPa.

Referring to FIG. 1D, a third insulating layer 114 for device isolation layer is formed on the passivation layer 112. For example, the third insulating film 114 may be formed of an HDP film. Specifically, in detail, the HDP film may be formed by injecting a mixed gas of SiH 4 , O 2 , He, and H 2 . For example, SiH 4 may be injected in an amount of 10 sccm to 200 sccm, O 2 to 10 sccm to 500 sccm, H 2 to 10 sccm to 1000 sccm, and H 2 to 10 sccm to 1000 sccm. In addition, the low frequency (LF) may add 10W to 10000W, and the high frequency (HF) may add 10W to 10000W.

Referring to FIG. 1E, a planarization process is performed to expose the device isolation mask pattern 106. The planarization process may be performed by performing a chemical mechanical polishing (CMP) process.

Referring to FIG. 1F, the device isolation mask pattern 106 of FIG. 1E is removed. In this case, a portion of the passivation layer 112 protruding to the upper portion of the first conductive layer 104 may be removed. Next, the third conductive film (114 in FIG. 1E) is removed. In this case, a part of the second insulating film 110 protruding to the upper portion of the first conductive film 104 may also be removed, and the second insulating film 110 may be removed since the protective film 112 protects the second insulating film 110 during the etching process. ) Height can be prevented.

Referring to FIG. 1G, a treatment process is performed to change the passivation film 112 of FIG. 1F to a material for an isolation layer. For example, the treatment process may be performed by an oxidation process, and the protective film (112 in FIG. 1F) is oxidized to change to the oxide protective film 112a. As a result, the first insulating film 108, the second insulating film 110, and the oxide protective film 112a become the device isolation film 115. In addition, a cleaning process may be performed to promote oxidation of the protective film (112 in FIG. 1F) prior to the treatment process, for example, a wet cleaning process may be performed to form an upper portion of the protective film (112 in FIG. 1F). Impurities that may remain in the can be removed.

Referring to FIG. 1H, a dielectric film 116 is formed along the surfaces of the device isolation film 115 and the first conductive film 104, and the second conductive film 118 for the control gate is formed on the dielectric film 116. To form. Subsequently, although not shown in the cross section of the figure, a flash element may be formed by performing a gate patterning process.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1A to 1H are cross-sectional views for illustrating a method of forming a device isolation film of a semiconductor device according to the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 102 tunnel insulating film

104: first conductive film 106: device isolation mask pattern

108: first insulating film 110: second insulating film

112: protective film 114: third insulating film

116 dielectric film 118 second conductive film

Claims (14)

Providing a semiconductor substrate including a trench and having a tunnel insulating film, a first conductive film and a device isolation mask pattern formed on the active region; Filling the inside of the trench with a first insulating film and a second insulating film; Forming a protective film along a surface of the second insulating film; Forming a third insulating layer on the passivation layer; Performing a planarization process to expose the device isolation mask pattern; Removing the third insulating film; And And oxidizing the protective film. The method of claim 1, And forming the passivation layer with a different etching selectivity from the second insulating layer. The method of claim 1, And the protective film is formed of a nitride film. The method of claim 1, The protective film is a device isolation film forming method of a semiconductor device to form a thickness of 10 ~ 200Å. The method of claim 1, And forming the first insulating film as a spin on dielectric (SOD) film. The method of claim 5, wherein The SOD film is a device isolation film forming method of a semiconductor device formed of a polysilazane (PSZ) film. The method of claim 1, And the second insulating film is an HDP film. The method of claim 1, And the third insulating film is an HDP film. The method according to claim 7 or 8, And the HDP film is formed by injecting a mixed gas of SiH 4 , O 2 , He, and H 2 . The method of claim 9, The SiH 4 is 10sccm to 200sccm, the O 2 is 10sccm to 500sccm, the H 2 is 10sccm to 1000sccm, the H 2 is injected in an amount of 10sccm to 1000sccm device isolation film forming method of a semiconductor device. The method according to claim 7 or 8, The HDP film is a method of forming a device isolation film of a semiconductor device formed by applying a low frequency (LF) of 10W to 10000W, high frequency (HF) of 10W to 10000W. The method of claim 1, The oxidizing of the protective film is a method of forming a device isolation film of a semiconductor device performed by a treatment (treatment) process. The method of claim 12, And the treatment step oxidizes the protective film and converts the protective film into an oxidative protective film. The method of claim 12, And performing a cleaning process prior to performing the treatment process.
KR1020070114443A 2007-11-09 2007-11-09 Method of forming a isolation layer in semiconductor device KR20090048180A (en)

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