KR20090031542A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device is provided to increase the storage capacitance even without enlarging a sustain electrode by interposing only a protective film on the same layer as a data line. Gate lines(22, 24, 26) are formed on an insulating substrate. In the insulating substrate, a gate insulating layer covers the gate lines. A semiconductor pattern(42) which is made of amorphous silicon as having from 800 to 1500Å thickness is formed on the gate insulating layer as overlapping with a gate electrode. A sustain electrode(68) is formed on the same layer as the data lines(62, 64, 65, 66), and forms storage capacitance by overlapping with a pixel electrode(82). A protective film which is made of silicon nitride or silicon oxide as having 500 to 2000Å thickness covers the data lines, sustain electrode and semiconductor pattern.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device.

The liquid crystal display device is one of the flat panel display devices currently widely used, and is composed of two substrates on which two electrodes facing each other are formed and a liquid crystal layer interposed therebetween. The image is displayed in a manner that controls the amount of light transmitted through the liquid crystal layer by rearranging the liquid crystal molecules of the layer. Here, two opposite electrodes may be formed on one of two substrates.

In a typical case, a plurality of pixel regions are defined by crossing a plurality of gate lines and a plurality of data lines in a thin film transistor substrate, which is one of two substrates of a liquid crystal display, and each pixel region is electrically connected to a gate line and a data line. A thin film transistor and a pixel electrode electrically connected to the thin film transistor are formed.

In such a liquid crystal display, a storage capacitor is formed on the thin film transistor substrate in order to stably maintain the liquid crystal voltage applied to the liquid crystal positioned between the two substrates. To this end, a storage capacitor electrode line is formed on the same layer as the gate line, which is parallel to the gate line, and the storage capacitor electrode line overlaps the pixel electrode to form the storage capacitor. However, in order to increase the luminance of the liquid crystal display or to increase the response speed, the capacitance of the capacitance must be increased. In this thin film transistor substrate structure, the area of the capacitance electrode line is inevitably widened, which inevitably leads to a decrease in the aperture ratio. There is a problem.

The present invention is to increase the capacitance of the holding capacitance without reducing the aperture ratio.

According to an exemplary embodiment, a liquid crystal display device includes a first insulating substrate, a gate line formed on the first insulating substrate, a gate wiring including a gate electrode, a gate insulating film covering the gate wiring, a semiconductor pattern formed on the gate insulating film, A data line formed on the gate insulating layer and insulated from and intersecting with the gate line, a data line including a source electrode connected to the data line and connected to the semiconductor pattern, and a drain electrode corresponding to the source electrode and connected to the semiconductor pattern, and the data line. A contact hole formed in the layer, formed between two adjacent data lines, covering the storage capacitor electrode line including the storage capacitor electrode insulated from and intersecting the gate line, the data wiring, the storage capacitor electrode line, and the semiconductor pattern and exposing the drain electrode. With a shield, and see A pixel electrode formed on the film and connected to the drain electrode through a contact hole and overlapping the storage capacitor electrode line, a second insulating substrate parallel to the first insulating substrate, a common electrode formed on the second insulating substrate, a pixel electrode, and And a liquid crystal layer sandwiched between the pixel electrode and the common electrode so as to form a liquid crystal capacitor together with the common electrode, wherein the liquid crystal capacitor is not less than 90% of the holding capacitance of the pixel electrode and the storage capacitor electrode, and the liquid crystal layer is in OCB mode. Features.

The display device may further include a common connection line connecting the plurality of storage capacitor electrode lines to one.

The common connection line is insulated from and crosses the data line and may be made of the same material as the pixel electrode.

The common connection line is insulated from and crosses the data line and may be made of the same material as the gate line.

A plurality of contact holes exposing a plurality of storage capacitor electrode lines may be formed in the passivation layer, and a common connection line may be connected to the plurality of storage capacitor electrode lines through the plurality of contact holes.

The display device may further include an auxiliary connection line connected to the plurality of storage capacitor electrode lines.

The plurality of storage capacitor electrode lines and the auxiliary connection lines may be formed of the same material.

A gate pad formed at one end of the gate line, a data pad formed at one end of the data line, a first contact hole exposing the gate pad in the passivation layer and a gate insulating film, a second contact hole exposing the data pad in the passivation layer, and first and second contacts It may further include an auxiliary gate pad and an auxiliary data pad covering the gate pad and the data pad through the hole.

The capacitance formed between the storage capacitor electrode line and the pixel electrode may have a size of 95% or more of the capacitance of the liquid crystal layer.

In the liquid crystal display according to the present invention, the storage capacitance can be increased without reducing the aperture ratio, and the response speed can be improved.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a layout view of a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views of a thin film transistor substrate taken along cut lines II-II ′ and III-III ′ of FIG. 1.

On the insulating substrate 10, a gate wiring 22, 24, or 26 having a thickness of 1000 to 3500 mW is formed of a conductive material such as aluminum or aluminum alloy, chromium or chromium alloy, molybdenum or molybdenum alloy, chromium nitride or molybdenum nitride. . The gate wires 22, 24, and 26 are formed on the gate line 22 extending in the horizontal direction, the gate pad 24 formed at one end of the gate line 22 to be in electrical contact with an external driving circuit (not shown), and As part of the gate line 22, the gate electrode 26 is included as one electrode of the thin film transistor.

In this case, the gate wirings 22, 24, and 26 may be formed in a double layer or more structure. In this case, at least one layer is preferably formed of a metal material having low resistance characteristics.

On the insulating substrate 10, a gate insulating film 30 having a thickness of 2500 to 4500 Å made of an insulating material such as silicon nitride or silicon oxide covers the gate wirings 22, 24, and 26.

On the gate insulating film 30, a semiconductor pattern 42 of 800-1500 Å thickness is formed which overlaps with the gate electrode 26 and is made of amorphous silicon or the like. On the semiconductor pattern 42, ohmic contact layers 55 and 56 having a thickness of 500 to 800 GPa formed of amorphous silicon or the like doped with N-type impurities at a high concentration are formed.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, a data line 62 having a thickness of 500 to 3500 Å made of a conductive material such as aluminum or an aluminum alloy, chromium or chromium alloy, molybdenum or molybdenum alloy, chromium nitride or molybdenum nitride, etc. 64, 65, 66 and the storage capacitor electrode line 68 are formed.

The data lines 62, 64, 65, and 66 extend in the vertical direction and are connected to one end of the data line 62 and the data line 62 that cross the gate line 22 and define the pixel area. A data pad 64 in electrical contact with the circuit, a source electrode 65 protruding from the data line 62 and extending up onto one ohmic contact layer 55 and an opposite electrode of the source electrode 65; And a drain electrode 66 extending from the ohmic contact layer 56 to the gate insulating film 30 inside the pixel region.

The storage capacitor electrode line 68 is formed on the same layer as the data lines 62, 64, 65, 66, and overlaps with the pixel electrode 82 described later to form the storage capacitor. At this time, the storage capacitor electrode lines 68 are arranged in parallel with the data lines 62 alternately with the data lines 62.

Here, the data lines 62, 64, 65, 66 and the storage capacitor electrode line 68 may be formed in a double layer or more structure. In this case, at least one layer is preferably formed of a metal material having low resistance. .

The data line 62, 64, 65, 66, the storage capacitor electrode line 68, and the semiconductor pattern 42 are covered with a protective film 70 having a thickness of 500 to 2000 GPa made of an insulating material such as silicon nitride or silicon oxide.

In the passivation layer 70, first and second contact holes 72 and 74 exposing the drain electrode 66 and the data pad 64 are formed, and an agent exposing the gate pad 24 together with the gate insulating layer 30. Three contact holes 76 are formed. The protective film 70 is also provided with a fourth contact hole 78 which exposes an end portion located on the data pad 64 side of the storage capacitor electrode line 68.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from the data line 62 and generates an electric field together with the electrodes of the upper plate is formed. The pixel electrode 82 is electrically connected to the drain electrode 66 through the first contact hole 72.

Here, the pixel electrode 82 overlaps the storage capacitor electrode line 68 with the protective film 70 therebetween to form the storage capacitor. At this time, as described above, the two electrodes 82 and 68 of the storage capacitor overlap each other with the passivation film 70 having a thin thickness therebetween, so that a large capacitance even if the width of the storage capacitor electrode line 68 is narrow. To form.

In addition, an auxiliary data pad 84 and an auxiliary gate pad 86 connected to the data pad 64 and the gate pad 24 are formed on the passivation layer 70 through the second and third contact holes 74 and 76. It is. In addition, a common connection line 88 connecting all of the storage capacitor electrode lines 68 on the substrate through the fourth contact hole 78 is formed in parallel with the gate line 22 outside the pixel area.

The pixel electrode 82, the auxiliary data pad 84, the auxiliary gate pad 86, and the common connection line 88 are formed on the same layer of a transparent conductive material such as ITO or IZO.

In this case, the common connection line 88 may be formed of the same material as the gate lines 22, 24, and 26 in the process of forming the gate lines 22, 24, and 26. In this case, a plurality of contact holes that expose the common connection line 88 should be formed in the gate insulating film 30, and the plurality of storage capacitor electrode lines 68 and the common connection line formed on the gate insulating film 30 through these contact holes ( 88) is contacted.

In the present invention, the arrangement state of the storage capacitor electrode line 68 and the common connection line 88 will be described in detail with reference to FIG. 4. 4 illustrates an arrangement of gate lines, data lines, and storage electrode lines of a thin film transistor substrate according to an exemplary embodiment of the present invention.

As shown in Fig. 4, a plurality of gate lines 22 extending in the horizontal direction are arranged side by side, and a plurality of data lines 62 extending in the vertical direction are arranged side by side. Each of the gate line 22 and the data line 62 crosses each other to form a plurality of pixel areas in the display area 110 of the thin film transistor substrate.

Here, one end of the data line 62, that is, the portion that becomes the data pad, is electrically connected to the data driving circuit 300 to receive a data signal from the data driving circuit. Similarly, one end of the gate line 22, that is, the portion which becomes the gate pad, is electrically connected to a gate driving circuit (not shown) to receive a gate signal from the gate driving circuit.

Here, the storage capacitor electrode lines 68 are alternately positioned with the data lines 62, and the storage capacitor electrode lines 68 are connected to each other by the auxiliary connection line 69 outside the display area 110. In this case, the storage electrode line 68 and the auxiliary connection line 69 may be formed to be commonly connected using the same material.

On the other hand, a common connection line 88 connecting all of the storage electrode lines 68 is formed at an end portion of the storage electrode line 68 positioned on the upper side of the substrate, that is, the data driving circuit. In this case, as described with reference to FIGS. 1 to 3, the common connection line 88 may be formed of a material different from that of the storage capacitor electrode line 68, for example, the same material as that of the pixel electrode 82, or It is preferable to form the same material as the gate wirings 22, 24, and 26. This is to prevent the common connection line 88 from being shorted to a portion of the data line 62 connected to the data driving circuit 300 outside the display area 110.

The storage capacitor electrode line 68 is electrically connected to the data driving circuit 300 to receive a common electrode potential from the data driving circuit 300.

Next, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 5A to 7C and FIGS. 1 to 4.

First, as shown in FIGS. 5A, 5B, and 5C, a gate wiring metal layer is deposited on the insulating substrate 10, and then the metal layer is patterned by a photolithography process to form gate wirings 22, 24, and 26. do. The gate wirings 22, 24, and 26 include a gate line 22, a gate pad 24, and a gate electrode 26.

Subsequently, a gate insulating layer 30 made of an insulating material such as silicon nitride is deposited on the insulating substrate 10 to cover the gate lines 22, 24, and 26.

Subsequently, an amorphous silicon layer and an amorphous silicon layer doped with a conductive impurity are sequentially formed on the gate insulating layer 30, and the two silicon layers are patterned by a photolithography process to form a semiconductor pattern 42 and an ohmic contact layer pattern ( 52).

6A, 6B, and 6C, after depositing a metal layer for data wiring on the exposed front surface of the substrate, the metal layer is patterned by a photolithography process to form data wirings 62, 64, 65, and 66. And the storage capacitor electrode line 68 are formed. The data lines 62, 64, 65, and 66 include a data line 62, a data pad 64, a source electrode 65, and a drain electrode 66. At this time, the storage capacitor electrode line 68 is formed so as to be alternately arranged with the data line 62.

Subsequently, the ohmic contact layer pattern 52 is etched using the source electrode 65 and the drain electrode 66 as a mask to contact the ohmic contact layer 55 and the drain electrode 66 contacting the source electrode 65. The resistive contact layer 56 is separated.

Next, as shown in FIGS. 7A, 7B, and 7C, a protective film 70 covering the data lines 62, 64, 65, and 66, the storage capacitor electrode line 68, and the semiconductor pattern 42 is formed. At this time, the protective film 70 is formed by thinly depositing an insulating material layer such as silicon nitride, and it is preferable to properly consider the thickness thereof in consideration of the capacitance of the desired holding capacitance.

Subsequently, the passivation layer 70 and the gate insulating layer 30 are patterned by a photolithography process to form first to fourth contact holes 72, 74, 76, and 78.

Next, as shown in FIGS. 1, 2, and 3, ITO or IZO is placed on the exposed front surface of the substrate including the wiring portions exposed through the first to fourth contact holes 72, 74, 76, and 78. The transparent conductive layer thus formed is deposited.

Subsequently, the transparent conductive layer is patterned by a photolithography process to pass through the pixel electrode 82, the second and third contact holes 74 and 76 connected to the drain electrode 66 through the first contact hole 72. Through the auxiliary data pad 84 and the auxiliary gate pad 86 and the fourth contact hole 78 connected to the data pad 64 and the gate pad 24, all of the storage capacitor electrode lines 68 on the substrate are connected. The common connection line 88 is formed.

The common connection line 88 may be formed of the same material as the gate lines 22, 24, and 26. To this end, a common connection line is formed in the process of forming the gate lines 22, 24, and 26, and a gate insulating layer 30, which is a subsequent process, is formed. Subsequently, a plurality of contact holes exposing a common connection line are formed in the gate insulating film 30, and then the storage capacitor electrode line 68 is formed while forming the data lines 62, 64, 65, and 66. In this process, the storage capacitor electrode line 68 is commonly connected to the common connection line through a plurality of contact holes exposing the common connection line.

  As described above, in the present invention, the storage capacitor is formed by overlapping the storage capacitor electrode line and the pixel electrode formed of the same material as the data line on the same layer as the data line with a thin protective film therebetween.

The present invention can be applied to all liquid crystal display modes. In particular, the present invention has a great advantage when applied to an OCB (Optically Compensated Birefringence) mode liquid crystal display.

In the liquid crystal display of the OCB mode, the difference between the dielectric constant in the initial state and the dielectric constant in the later state is very large as gray is changed due to the large Δε of the liquid crystal. Is inevitable.

On the other hand, the response waveform (time-luminance) curve measured in the liquid crystal display of all modes has a two step waveform showing two steps, as shown in FIG.

Since the response speed is measured when the total brightness changes from 10% to 90%, the response speed is measured slowly when the two-step portion is below 90% brightness.

However, in the OCB mode liquid crystal display, a two-stage waveform occurs in the first frame and maintains a normal luminance in the second or third frame. Therefore, when the storage capacitance is increased so that the brightness of the two-step portion is 90% or more, preferably 95% or more, the response speed can be increased by maintaining the normal brightness in the first frame.

Table 1 measures the luminance value of the 2-step portion on the response speed waveform (time-luminance) curve according to the ratio of the capacitance Cst of the holding capacitance to the capacitance Clc of the liquid crystal in the OCB structured liquid crystal display device. It is shown.

Clc: Cst 1.00: 0.70 1.00: 0.91 2nd position (luminance%) 81.8%  87.3%

It can be seen that when the capacitance of the storage capacitor increases, the position of the two-step is close to 90% of the luminance. Therefore, the storage capacitance can be increased to increase the response speed by over 90% of the two-step positions. In particular, when the storage capacitance is increased to be 95% or more in the 2-step position, faster response speed can be obtained.

In the present invention, in order to increase the response speed of the liquid crystal display, the capacitance of the storage capacitor is increased to be 90% or more of the capacitance of the liquid crystal. For this purpose, the storage capacitor as described with reference to FIGS. Applied to the liquid crystal display device of OCB mode. That is, in the present invention, the storage capacitor electrode line overlapping the pixel electrode is formed on the same layer as the data line with only the protective film interposed therebetween, so that the storage capacitor electrode line overlapping the pixel electrode is formed on the same layer as the gate line via the protective film and the gate insulating film. Compared with the conventional liquid crystal display device, the storage capacitance can be increased without widening the storage capacitor electrode line, which is advantageous in the aperture ratio.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

1 is a layout view of a thin film transistor substrate according to an embodiment of the present invention,

2 and 3 are cross-sectional views of a thin film transistor substrate taken along cut lines II-II 'and III-III' of FIG. 1,

4 is a wiring diagram of a gate line, a data line, and a storage capacitor electrode line in a thin film transistor substrate according to an exemplary embodiment of the present invention.

5A is a layout view of a substrate in a first manufacturing step for manufacturing a thin film transistor substrate according to an embodiment of the present invention;

5B and 5C are cross-sectional views of the substrate according to Vb-Vb ′ and Vc-Vc ′ of FIG. 5a;

FIG. 6A is a layout view of a substrate in a subsequent manufacturing step of FIG. 5A;

6B and 6C are cross-sectional views of the substrate according to VIb-VIb ′ and VIc-VIc ′ of FIG. 6A;

FIG. 7A is a layout view of a substrate in a subsequent manufacturing step of FIG. 6A,

7B and 7C are cross-sectional views of the substrate according to Vb-Vb 'and Vc-Vc' of Fig. 7A;

8 shows a V (liquid crystal voltage)-T (time) curve in the liquid crystal display.

Claims (9)

First insulating substrate, A gate wiring including a gate line and a gate electrode formed on the first insulating substrate; A gate insulating film covering the gate wiring, A semiconductor pattern formed on the gate insulating layer, A data line formed on the gate insulating layer and insulated from and intersecting the gate line, a data electrode connected to the data line to be connected to the semiconductor pattern, and a drain electrode corresponding to the source electrode to be connected to the semiconductor pattern; Wiring, A storage capacitor electrode line formed on the same layer as the data line and formed between two adjacent data lines and including a storage capacitor electrode insulated from and intersecting the gate line; A protective film covering the data line, the storage capacitor electrode line and the semiconductor pattern and having a contact hole exposing the drain electrode; A pixel electrode formed on the passivation layer, connected to the drain electrode through the contact hole, and overlapping the storage capacitor electrode line; A second insulating substrate parallel to the first insulating substrate, A common electrode formed on the second insulating substrate, A liquid crystal layer interposed between the pixel electrode and the common electrode to form a liquid crystal capacitor together with the pixel electrode and the common electrode, The liquid crystal capacitor is 90% or more of the storage capacitor formed by the pixel electrode and the storage capacitor electrode, And the liquid crystal layer is in OCB mode. In claim 1, And a common connection line connecting the plurality of storage capacitor electrode lines to one. In claim 2, And the common connection line is insulated from and crosses the data line and made of the same material as the pixel electrode. In claim 2, And the common connection line is insulated from and crosses the data line and made of the same material as the gate line. In claim 3, And a plurality of contact holes exposing a plurality of the storage capacitor electrode lines in the passivation layer, and the common connection line is connected to the plurality of storage capacitor electrode lines through the plurality of contact holes. In claim 2, And a plurality of auxiliary connection lines connected to a plurality of the storage capacitor electrode lines. In claim 6, The plurality of storage capacitor electrode lines and the auxiliary connection line are formed of the same material. In claim 1, A gate pad formed at one end of the gate line, A data pad formed at one end of the data line, A first contact hole exposing the gate pad in the protective film and the gate insulating film, A second contact hole exposing the data pad in the passivation layer, and An auxiliary gate pad and an auxiliary data pad covering the gate pad and the data pad through the first and second contact holes Liquid crystal display further comprising. In claim 1, The capacitance formed between the storage capacitor electrode line and the pixel electrode has a size of 95% or more of the capacitance of the liquid crystal layer.

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