KR20080042793A - Thin film transistor substrate, fabricating method thereof and liquid crystal display - Google Patents

Abstract

A thin film transistor substrate, a method for manufacturing the same, and a liquid crystal display are provided to increase electric capacity without widening areas of storage capacitance lines, thereby improving response speed. Gate wiring(22,24,26) is formed on an insulating substrate, including first gate lines, gate electrodes(26) connected with the first gate lines, and second gate lines arranged apart from the first gate lines. A gate insulating film covers the gate wiring. Semiconductor patterns(42) are formed on the gate insulating film, overlapped with the gate electrodes. Data wiring(62,64,65,66) is formed on the gate insulating film, including data lines(62) crossing the first and second gate lines, and source and drain electrodes(65,66). Storage capacitance conductor patterns(68) are overlapped with a part of the second gate lines to form first storage capacitance. A passivation layer covers the data wiring, the storage capacitance conductor patterns, and the semiconductor patterns. First and second contact holes(72,74) expose the drain electrode and the storage capacitance conductor patterns. Pixel electrodes(82) are connected with the drain electrode and the storage capacitance conductor patterns through the first and second contact holes, and form second storage capacitance by overlapping a part of the second gate lines.

Description

Thin film transistor substrate, manufacturing method thereof and liquid crystal display device {THIN FILM TRANSISTOR SUBSTRATE, FABRICATING METHOD THEREOF AND LIQUID CRYSTAL DISPLAY}

The present invention relates to a thin film transistor substrate and a liquid crystal display device.

The liquid crystal display device is one of the flat panel display devices currently widely used, and is composed of two substrates on which two electrodes facing each other are formed and a liquid crystal layer interposed therebetween. The image is displayed in a manner that controls the amount of light transmitted through the liquid crystal layer by rearranging the liquid crystal molecules of the layer. Here, two opposite electrodes may be formed on one of two substrates.

In a typical case, a plurality of pixel regions are defined by crossing a plurality of gate lines and a plurality of data lines in a thin film transistor substrate, which is one of two substrates of a liquid crystal display, and each pixel region is electrically connected to a gate line and a data line. A thin film transistor and a pixel electrode electrically connected to the thin film transistor are formed.

In such a liquid crystal display, a storage capacitor is formed on the thin film transistor substrate in order to stably maintain the liquid crystal voltage applied to the liquid crystal positioned between the two substrates. To this end, a storage capacitor electrode line is formed on the same layer as the gate line, which is parallel to the gate line, and the storage capacitor electrode line overlaps the pixel electrode to form the storage capacitor. However, in order to increase the luminance of the liquid crystal display or to increase the response speed, the capacitance of the capacitance must be increased. In this thin film transistor substrate structure, the area of the capacitance electrode line is inevitably widened, which inevitably leads to a decrease in the aperture ratio. There is a problem.

The present invention seeks to increase the capacitance of the holding capacitance without reducing the aperture ratio.

In order to achieve the above technical problem, a thin film transistor substrate, an insulating substrate, and an insulating substrate are formed on the substrate, and are disposed at predetermined intervals from a first gate line, a gate electrode connected to the first gate line, and the first gate line. A gate wiring including a second gate line, a gate insulating film covering the gate wiring, a semiconductor pattern overlapping the gate electrode on the gate insulating film, a data line formed on the gate insulating film, and crossing the first and second gate lines; A storage capacitor conductor pattern overlapping a portion of the data wiring including the source electrode and the drain electrode and the second gate line to form the first storage capacitor, a protective film covering the data wiring, the storage capacitor conductor pattern and the semiconductor pattern, and a drain on the protective film. First and second contact holes exposing an electrode and a storage capacitor conductor pattern, respectively, over the protective film; 2 and are in contact via the hole connected to the drain electrode and the storage capacitor conductors, and includes the pixel electrodes forming the second storage capacitor to overlap the second gate line of the part.

And a thin film transistor substrate, an opposing substrate facing the thin film transistor substrate, and a liquid crystal layer interposed between the thin film transistor substrate and the opposing substrate.

The capacitance of the first holding capacitor and the second holding capacitor may be greater than 90% of the capacitance of the liquid crystal layer.

According to another aspect of the present invention, there is provided a method of fabricating a thin film transistor substrate, wherein the first gate line, the gate electrode connected to the first gate line, and the first gate line are disposed side by side at a predetermined interval on the insulating substrate. Forming a gate wiring including a second gate line, forming a gate insulating film covering the gate wiring, forming a semiconductor pattern overlapping the gate electrode on the gate insulating film, and forming a first and second gate lines on the gate insulating film Forming a storage capacitor conductor pattern overlapping a portion of the data wiring including a data line, a source electrode and a drain electrode and a second gate line to form a first storage capacitor, the data wiring and a storage capacitor pattern And forming a passivation layer covering the semiconductor pattern, wherein the drain electrode and the storage capacitor are formed on the passivation layer. Forming first and second contact holes that expose the entire pattern, respectively, connected to the drain electrode and the storage capacitor pattern through the first and second contact holes on the passivation layer, and with a portion of the gate line of the second gate wiring; Forming pixel electrodes overlapping each other to form a second storage capacitor.

In the liquid crystal display device according to the present invention, it is possible to increase the capacitance of the storage capacitance without reducing the aperture ratio, thereby improving the response speed.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along the cutting line II-II ′ of FIG. 1.

Gate wirings 22, 24, 26 and 1000-500 kW thick gate wirings and holding capacitor wirings made of a conductive material such as aluminum or an aluminum alloy, chromium or chromium alloy, molybdenum or molybdenum alloy, chromium nitride or molybdenum nitride on the insulating substrate 10 (27, 28) are formed.

The gate wires 22, 24, and 26 are formed on the gate line 22 extending in the horizontal direction, the gate pad 24 formed at one end of the gate line 22 to be in electrical contact with an external driving circuit (not shown), and As part of the gate line 22, the gate electrode 26 is included as one electrode of the thin film transistor.

In addition, the storage capacitor wirings 28 and 29 are connected to the rectangular storage capacitor electrode pattern 28 and the adjacent storage capacitor electrode patterns 28 positioned between the two gate lines 22 and are parallel to the gate lines 22. And the storage capacitor electrode line 29 extending in the horizontal direction.

In this case, the gate wirings 22, 24, 26 and the storage capacitor wirings 28, 29 may be formed in a double layer or more structure. In this case, at least one layer is preferably formed of a metal material having low resistance characteristics. Do.

On the insulating substrate 10, a gate insulating film 30 having a thickness of 2500 to 4500 Å made of an insulating material such as silicon nitride or silicon oxide covers the gate wirings 22, 24 and 26 and the storage capacity wirings 28 and 29. .

On the gate insulating film 30, a semiconductor pattern 42 of 800-1500 Å thickness is formed which overlaps with the gate electrode 26 and is made of amorphous silicon or the like. On the semiconductor pattern 42, ohmic contact layers 55 and 56 having a thickness of 500 to 800 GPa formed of amorphous silicon or the like doped with N-type impurities at a high concentration are formed.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, a data line 62 having a thickness of 500 to 3500 Å made of a conductive material such as aluminum or an aluminum alloy, chromium or chromium alloy, molybdenum or molybdenum alloy, chromium nitride or molybdenum nitride, etc. 64, 65, 66 and the storage capacitor conductor 68 are formed.

The data lines 62, 64, 65, and 66 extend in the vertical direction and are connected to one end of the data line 62 and the data line 62 that cross the gate line 22 and define the pixel area. A data pad 64 in electrical contact with the circuit, a source electrode 65 protruding from the data line 62 and extending up onto one ohmic contact layer 55 and an opposite electrode of the source electrode 65; And a drain electrode 66 extending from the ohmic contact layer 56 to the gate insulating film 30 inside the pixel region.

The storage capacitor conductor pattern 68 is formed in an island shape on the same layer as the data wires 62, 64, 65, and 66, and the storage capacitor electrode pattern is disposed below the gate insulating film 30. Overlap with (28) to form a holding capacity. At this time, the storage capacitor conductor pattern 68 is electrically connected to the pixel electrode 82 described later to receive an image voltage.

Here, the data lines 62, 64, 65, 66 and the storage capacitor conductor pattern 68 may be formed in a double layer or more structure. In this case, at least one layer may be formed of a metal material having low resistance. desirable.

The data wirings 62, 64, 65, 66, the storage capacitor conductor pattern 68, and the semiconductor pattern 42 are covered with a protective film 70 having a thickness of 500 to 2000 Å made of an insulating material such as silicon nitride or silicon oxide. have.

In the passivation layer 70, first and second contact holes 72 and 74 exposing the drain electrode 66 and the data pad 64 are formed, and an agent exposing the gate pad 24 together with the gate insulating layer 30. Three contact holes 76 are formed. In the protective film 70, a fourth contact hole 78 exposing the storage capacitor conductor pattern 68 is also formed.

The pixel electrode 82 connected to the drain electrode 66 and the storage capacitor conductor pattern 68 is formed on the passivation layer 70 through the first and fourth contact holes 72 and 78.

In addition, an auxiliary data pad 84 and an auxiliary gate pad 86 connected to the data pad 64 and the gate pad 24 are formed on the passivation layer 70 through the second and third contact holes 74 and 76. It is.

Here, the pixel electrode 82, the auxiliary data pad 84, and the auxiliary gate pad 86 are formed of a transparent conductive material such as ITO or IZO.

In the present invention, the pixel electrode 82 overlaps with the storage capacitor wirings 28 and 29, and the storage capacitor is formed with the protection capacitor electrode line 29 interposed between the protective film 70 and the gate insulating film 30.

In addition, the pixel electrode 82 is connected to the storage capacitor conductor pattern 68, whereby the storage capacitor conductor pattern 68 is disposed between the storage capacitor electrode pattern 28 and the gate insulating film 30. To form different retention capacities. In this case, since the thickness of the insulating film interposed between the two electrodes 28 and 68 is thin, the same overlapping area is formed as compared with the case where the storage capacitor electrode pattern 28 overlaps the pixel electrode 82 to form the storage capacitor. Even larger capacitances can be formed.

Therefore, in the present invention, the capacitance can be increased without increasing the area of the storage capacitor wirings 28 and 29, so that the aperture ratio can be improved compared to the capacitance.

Next, a method of manufacturing the thin film transistor substrate according to the first embodiment of the present invention will be described in detail with reference to FIGS. 3A to 6B and FIGS. 1 and 2.

First, as shown in FIGS. 3A and 3B, after depositing a metal layer for gate wiring on the insulating substrate 10, the metal layer is patterned by a photolithography process to form the gate wirings 22, 24, and 26 and the storage capacitor wiring ( 28, 29). The gate wirings 22, 24, and 26 include a gate line 22, a gate pad 24, and a gate electrode 26, and the storage capacitor wirings 28 and 29 include the storage capacitor electrode pattern 28 and the storage capacitor. The electrode wire 29 is included.

Next, as shown in FIGS. 4A and 4B, a gate insulating film 30 made of an insulating material such as silicon nitride is deposited on the insulating substrate 10 to form the gate wirings 22, 24, and 26 and the storage capacitor wiring 28. , 29).

Subsequently, an amorphous silicon layer and an amorphous silicon layer doped with a conductive impurity are sequentially formed on the gate insulating layer 30, and then the two silicon layers are patterned by a photolithography process to form a semiconductor pattern 42 and an ohmic contact layer pattern. Form 52.

Next, as shown in FIGS. 5A, 5B, and 6C, after depositing a metal layer for data wiring on the exposed front surface of the substrate, the metal layer is patterned by a photolithography process to form data wirings 62, 64, 65, and 66. And the storage capacitor conductor pattern 68. The data lines 62, 64, 65, and 66 include a data line 62, a data pad 64, a source electrode 65, and a drain electrode 66. At this time, the storage capacitor conductor pattern 68 is formed to overlap the storage capacitor electrode pattern 28.

Subsequently, the ohmic contact layer pattern 52 is etched using the source electrode 65 and the drain electrode 66 as a mask to contact the ohmic contact layer 55 and the drain electrode 66 contacting the source electrode 65. The resistive contact layer 56 is separated.

Next, as shown in FIGS. 6A and 6B, silicon nitride or silicon oxide on the entire surface of the substrate including the data wirings 62, 64, 65, and 66, the storage capacitor conductor pattern 68, and the semiconductor pattern 42. The protective film 70 is formed by, for example.

Subsequently, the passivation layer 70 and the gate insulating layer 30 are patterned by a photolithography process to form first to fourth contact holes 72, 74, 76, and 78. In this case, the first, second and fourth contact holes 72, 74, and 78 are formed in the passivation layer 70, and the drain electrode 66, the data pad 64, and the storage capacitor conductor pattern 68, respectively. Reveals. In addition, the third contact hole 76 is formed in the protective film 70 and the gate insulating film 30 to expose the gate pad 24.

Next, as shown in FIGS. 1 and 2, a transparent conductive layer made of ITO or IZO on a substrate exposed front surface including a wiring portion exposed through the first to fourth contact holes 72, 74, 76, and 78. Deposit.

Next, the transparent conductive layer is patterned by a photolithography process to connect the pixel electrode 82 connected to the drain electrode 66 and the storage capacitor pattern 68 through the first and fourth contact holes 72 and 78, The auxiliary data pad 84 and the auxiliary gate pad 86 are formed to be connected to the data pad 64 and the gate pad 24 through the second and third contact holes 74 and 76.

In the above-described first embodiment of the present invention, the storage capacitor conductor pattern 68 is formed as an island shape in an area between two adjacent gate lines, that is, the pixel area. ) May be formed in various ways without being limited to the contents set forth in the first embodiment of the present invention. For example, the storage capacitor conductor 68 may be formed in a bar shape at an edge portion of the pixel area. At this time, the storage capacitor conductor pattern 68 and the storage capacitor electrode pattern 28 forming the storage capacitor are also formed in a bar shape. This will be described with reference to FIGS. 7 and 8.

7 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view of the thin film transistor substrate taken along the cutting line VII-VIII of FIG. 7.

In this embodiment, the storage capacitor electrode pattern 28 is formed in a bar shape and is located at both edge portions of the pixel region. Of course, each of the storage capacitor electrode patterns 28 is connected to the storage capacitor electrode line 29.

The storage capacitor conductor pattern 68 that forms the storage capacitor electrode pattern 28 and the storage capacitor also overlaps the storage capacitor electrode pattern 28 on the gate insulating film 30.

The fourth contact hole 78 serving as a path connecting the storage capacitor conductor pattern 68 and the pixel electrode 82 may be formed by exposing any portion of the storage capacitor conductor pattern 68 and may be formed in one or more portions. .

In the liquid crystal display device having such a structure, the storage capacitor electrode line 29 and the pixel electrode 82 form the storage capacitor with the gate insulating film 30 and the protective film 70 interposed therebetween. In addition, each of the storage capacitor electrode patterns 28 and the storage capacitor conductor pattern 68 overlapping each other form another storage capacitor with the gate insulating film 30 interposed therebetween.

Such a storage capacitor in the present invention can form a larger capacitance even when the storage capacitor electrode pattern 28 overlaps only the pixel electrode 82 to form the storage capacitor. Therefore, in the present invention, the capacitance can be increased without increasing the area of the storage capacitor wirings 28 and 29, so that the aperture ratio can be improved compared to the capacitance.

In this embodiment, since the bar-shaped storage capacitor electrode pattern 28 or the storage capacitor conductor pattern 68 is positioned between the pixel electrode 82 and the data line 62, the pixel electrode 82 and the data line There is an advantage that can prevent the side light leakage occurring between the (62).

In the above-described first and second embodiments of the present invention, the case where the storage capacitor wiring is formed separately is taken as an example, but a part of the gate line can be formed as the storage capacitor electrode. This will be described with reference to FIGS. 9 and 10.

FIG. 9 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention, and FIG. 10 is a cross-sectional view of the thin film transistor substrate taken along the cutting line VII-VII 'of FIG. 9.

In this embodiment, the pixel electrode is formed to overlap the portion of the gate line of the gate wiring positioned at the front end, not the magnetic end, to form the storage capacitor. Thus, a portion of the gate line is maintained without forming a wiring for the storage capacitor. Used as capacitive wiring.

In the drawing, the pixel electrode 82 affected by the gate signal from the gate line 22 of the (n) th gate wiring Gn is the gate line 22 of the (n-1) th gate wiring Gn-1. The area is extended to overlap with.

The storage capacitor conductor pattern 68 overlaps a part of the gate line 22 on the gate insulating film 30, and is formed on the same layer as the data lines 62, 64, 65, and 66. A fourth contact hole 78 exposing the storage capacitor conductor pattern 68 is formed in the passivation layer 70, and the pixel electrode 82 is disposed on the front gate line 22 through the fourth contact hole 78. It is connected to the storage capacitor conductor pattern 68 which is located.

In this embodiment, the storage capacitor conductor pattern 68 overlaps the gate line 22 to form the storage capacitor with the gate insulating film 30 interposed therebetween. At this time, the storage capacitor conductor pattern 68 on the gate line 22 of the (n-1) th gate line Gn-1 is gated from the gate line 22 of the (n) th gate line Gn. A signal is received from the pixel electrode 82 which is affected by the signal.

The liquid crystal display device in this embodiment can significantly increase the size of the capacitance as compared with the case where only the pixel electrode 82 and the gate line 22 are overlapped to form the storage capacitance. In this embodiment, by using a part of the gate line as the storage capacitor wiring, since no separate wiring is formed in the pixel region, the aperture ratio can be further improved.

FIG. 11 is a layout view of a thin film transistor substrate according to a fourth exemplary embodiment of the present invention, and FIG. 12 is a cross-sectional view of the thin film transistor substrate taken along the cutting line XII-XII ′ of FIG. 11.

Gate wirings 22, 24, 26 and a storage capacitor electrode line having a thickness of 1000 to 3500 mW of a conductive material such as aluminum or an aluminum alloy, chromium or chromium alloy, molybdenum or molybdenum alloy, chromium nitride or molybdenum nitride on the insulating substrate 10 27 is formed.

The gate wires 22, 24, and 26 are formed on the gate line 22 extending in the horizontal direction, the gate pad 24 formed at one end of the gate line 22 to be in electrical contact with an external driving circuit (not shown), and As part of the gate line 22, the gate electrode 26 is included as one electrode of the thin film transistor.

In addition, the storage capacitor electrode line 27 is positioned between the two gate lines 22 and extends in the horizontal direction in parallel with the gate line 22.

At this time, the gate wirings 22, 24, 26 and the storage capacitor electrode lines 27 can be formed in a double layer or more structure. In this case, at least one layer is preferably formed of a metal material having low resistance characteristics.

On the insulating substrate 10, a gate insulating film 30 having a thickness of 2500 to 4500 kV made of an insulating material such as silicon nitride or silicon oxide covers the gate wirings 22, 24, and 26 and the storage capacitor electrode pattern 27.

Here, the first contact hole 32 exposing the storage capacitor electrode line 27 is formed in the gate insulating film 30.

On the gate insulating film 30, a semiconductor pattern 42 of 800-1500 Å thickness is formed which overlaps with the gate electrode 26 and is made of amorphous silicon or the like. On the semiconductor pattern 42, ohmic contact layers 55 and 56 having a thickness of 500 to 800 GPa formed of amorphous silicon or the like doped with N-type impurities at a high concentration are formed.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, a data line 62 having a thickness of 500 to 3500 Å made of a conductive material such as aluminum or an aluminum alloy, chromium or chromium alloy, molybdenum or molybdenum alloy, chromium nitride or molybdenum nitride, etc. 64, 65, 66 and the storage capacitor conductor pattern 67 are formed.

The data lines 62, 64, 65, and 66 extend in the vertical direction and are connected to one end of the data line 62 and the data line 62 that cross the gate line 22 and define the pixel area. A data pad 64 in electrical contact with the circuit, a source electrode 65 protruding from the data line 62 and extending up onto one ohmic contact layer 55 and an opposite electrode of the source electrode 65; And a drain electrode 66 extending from the ohmic contact layer 56 to the gate insulating film 30 inside the pixel region.

The storage capacitor conductor pattern 67 is formed on the same layer as the data lines 62, 64, 65, 66, and is connected to the storage capacitor electrode line 27 through the first contact hole 32. The storage capacitor conductor pattern 67 overlaps with the pixel electrode 82 described later to form a storage capacitor. At this time, the storage capacitor conductor pattern 67 is connected to the storage capacitor electrode line 27 to receive a common voltage.

Here, the data lines 62, 64, 65, 66 and the storage capacitor conductor pattern 67 may be formed in a double layer or more structure. In this case, at least one layer may be formed of a metal material having low resistance. desirable.

The data wirings 62, 64, 65, 66, the storage capacitor conductor pattern 67, and the semiconductor pattern 42 are covered with a protective film 70 having a thickness of 500 to 2000 Å made of an insulating material such as silicon nitride or silicon oxide. have.

In the passivation layer 70, first and second contact holes 72 and 74 exposing the drain electrode 66 and the data pad 64 are formed, and an agent exposing the gate pad 24 together with the gate insulating layer 30. Three contact holes 76 are formed.

The pixel electrode 82 connected to the drain electrode 66 is formed on the passivation layer 70 through the first contact hole 72.

In addition, an auxiliary data pad 84 and an auxiliary gate pad 86 connected to the data pad 64 and the gate pad 24 are formed on the passivation layer 70 through the second and third contact holes 74 and 76. It is.

Here, the pixel electrode 82, the auxiliary data pad 84, and the auxiliary gate pad 86 are formed of a transparent conductive material such as ITO or IZO.

In the present invention, the pixel electrode 82 overlaps with the storage capacitor electrode line 27, and the storage capacitor is formed with the protection capacitor electrode line 27 interposed between the passivation film 70 and the gate insulating film 30.

In addition, the pixel electrode 82 overlaps with the storage capacitor conductor pattern 67 connected to the storage capacitor electrode line 27. The pixel electrode 82 is separated from the storage capacitor conductor pattern 67 by another passivation layer 70. To form a maintenance dose. In this case, since the thickness of the insulating film interposed between the two electrodes 27 and 67 is thin, it has the same overlapping area as compared with the case where the storage capacitor electrode line 27 overlaps the pixel electrode 82 to form the storage capacitor. Even larger capacitances can be formed.

Therefore, in the present invention, the capacitance can be increased without increasing the area of the wiring for the maintenance capacitance, thereby improving the aperture ratio compared to the capacitance.

Next, a method of manufacturing a thin film transistor substrate according to a fourth exemplary embodiment of the present invention will be described with reference to FIGS. 13A to 17B and FIGS. 11 and 12.

First, as shown in FIGS. 13A and 13B, after depositing a metal layer on the insulating substrate 10, the metal layer is patterned by a photolithography process to form the gate wirings 22, 24, 26, and the storage capacitor electrode line 27. To form. The gate wirings 22, 24, and 26 include a gate line 22, a gate pad 24, and a gate electrode 26.

Next, as shown in FIGS. 14A and 14B, a gate insulating film 30 made of an insulating material such as silicon nitride is deposited on the insulating substrate 10 to form the gate wirings 22, 24, 26, and the storage capacitor electrode line 27. ). Subsequently, an amorphous silicon layer 40 and an amorphous silicon layer 50 doped with conductive impurities are sequentially formed on the gate insulating layer 30.

Subsequently, the two silicon layers 40 and 50 and the gate insulating layer 30 are patterned by a photolithography process to form a first contact hole 32 exposing the storage capacitor electrode pattern 27.

Next, as shown in FIGS. 15A and 15B, the amorphous silicon layer 40 and the amorphous silicon layer 50 doped with conductive impurities are patterned by a photolithography process to form a semiconductor pattern 42 and an ohmic contact layer pattern. Form 52.

Next, as shown in Figs. 16A and 16B, a metal layer is deposited on the exposed front surface of the substrate, and then patterned by the photolithography process to form the metal layer for data wirings 62, 64, 65, 66 and the storage capacitor conductor. The pattern 67 is formed. The data lines 62, 64, 65, and 66 include a data line 62, a data pad 64, a source electrode 65, and a drain electrode 66. At this time, the storage capacitor conductor pattern 67 is connected to the storage capacitor electrode line 27 through the first contact hole 32.

Subsequently, the ohmic contact layer pattern 52 is etched using the source electrode 65 and the drain electrode 66 as a mask to contact the ohmic contact layer 55 and the drain electrode 66 contacting the source electrode 65. The resistive contact layer 56 is separated.

Next, as shown in FIGS. 17A and 17B, silicon nitride or silicon oxide on the entire surface of the substrate including the data wirings 62, 64, 65, and 66, the storage capacitor conductor pattern 67, and the semiconductor pattern 42. The protective film 70 is formed by, for example.

Subsequently, the passivation layer 70 and the gate insulating layer 30 are patterned by a photolithography process to form second to fourth contact holes 72, 74, and 76. In this case, the second and third contact holes 72 and 74 are formed in the passivation layer 70, and expose the drain electrode 66 and the data pad 64, respectively. In addition, the third contact hole 76 is formed in the passivation layer 70 and the gate insulating layer 30 to expose the gate pad 24.

Next, as shown in FIGS. 11 and 12, a transparent conductive layer made of ITO or IZO is deposited on the exposed surface of the substrate including the wiring portions exposed through the second to fourth contact holes 72, 74, and 76. do.

Subsequently, the transparent conductive layer is patterned by a photolithography process to pass through the pixel electrode 82, the third and fourth contact holes 74 and 76 connected to the drain electrode 66 through the second contact hole 72. An auxiliary data pad 84 and an auxiliary gate pad 86 connected to the data pad 64 and the gate pad 24 are formed.

In the above-described fourth embodiment of the present invention, the storage capacitor conductor pattern 67 is formed in an area between two neighboring gate lines, that is, in the pixel region, and the shape of the storage capacitor conductor pattern 67 is exemplified. And positions can be formed in various ways without being limited to the contents set forth in the fourth embodiment of the present invention. For example, the storage capacitor conductor pattern 67 may be formed in a bar shape at an edge portion of the pixel region. This will be described with reference to FIGS. 18 and 19.

FIG. 18 is a layout view of a thin film transistor substrate according to a fifth exemplary embodiment of the present invention, and FIG. 19 is a cross-sectional view of the thin film transistor substrate taken along the cutting line VII- ′ ′ of FIG. 18.

In this embodiment, the storage capacitor conductor pattern 67 is formed in a bar shape and is located at both edges of the pixel region. Here, the storage capacitor conductor pattern 67 is connected to the storage capacitor electrode line 27 through the first contact hole 32 formed in the gate insulating film 30.

  Here, the storage capacitor electrode line 27 forms a storage capacitor with the pixel electrode 82 interposed between the gate insulating film 30 and the protective film 70. In addition, the storage capacitor conductor pattern 67 forms another storage capacitor with the pixel electrode 82 with the protective film 70 therebetween.

Such a storage capacitor in the present invention can form a larger capacitance even when the storage capacitor electrode line 27 overlaps only the pixel electrode 82 to form the storage capacitor. Therefore, in the present invention, the capacitance can be increased without increasing the area of the wirings 27 and 67 for the storage capacitance, thereby improving the aperture ratio compared to the capacitance.

In addition, in this embodiment, since the bar-shaped storage capacitor conductor pattern 67 is located between the pixel electrode 82 and the data line 62, the side surface generated between the pixel electrode 82 and the data line 62. There is an advantage to stop the light leakage.

In the above-described fourth and fifth embodiments of the present invention, the case where the storage capacitor wiring is separately formed is taken as an example, but a part of the gate line can be formed as the storage capacitor electrode. This will be described with reference to FIGS. 20 and 21.

20 is a layout view of a thin film transistor substrate according to a sixth exemplary embodiment of the present invention, and FIG. 21 is a cross-sectional view of the thin film transistor substrate taken along the cutting line VII-XI ′ of FIG. 20.

In this embodiment, the pixel electrode overlaps with a part of the front gate line to form the storage capacitor. A portion of the gate line is used as the storage capacitor wiring without separately forming wiring for the storage capacitor.

In the drawing, the pixel electrode 82 affected by the gate signal from the gate line 22 of the (n) th gate wiring Gn is the gate line 22 of the (n-1) th gate wiring Gn-1. The area is extended to overlap with.

The storage capacitor conductor pattern 67 overlaps a part of the gate line 22 on the gate insulating film 30, and is formed on the same layer as the data lines 62, 64, 65, and 66. A fourth contact hole 78 exposing such a storage capacitor conductor pattern 67 is formed in the protective film 70. Then, the storage capacitor conductor pattern 67 on the gate line 22 of the (n-1) th gate line Gn-1 is gated from the gate line 22 of the (n) th gate line Gn. It is connected to the pixel electrode 82 that is affected.

In this embodiment, the storage capacitor conductor pattern 67 overlaps the gate line 22 to form the storage capacitor with the gate insulating film 30 interposed therebetween. At this time, the storage capacitor conductor pattern 68 on the gate line 22 of the (n-1) th gate line Gn-1 is gated from the gate line 22 of the (n) th gate line Gn. A signal is received from the pixel electrode 82 which is affected by the signal.

The liquid crystal display device in this embodiment can significantly increase the size of the capacitance as compared with the case where only the pixel electrode 82 and the gate line 22 are overlapped to form the storage capacitance. In this embodiment, by using a part of the gate line as the storage capacitor wiring, since no separate wiring is formed in the pixel region, the aperture ratio can be further improved.

The present invention can be applied to all liquid crystal display modes. In particular, the present invention has a great advantage when applied to an OCB (Optically Compensated Birefringence) mode liquid crystal display.

In the OCB mode liquid crystal display device, the difference between the permittivity value in the initial state and the permittivity value in the later state is very large as gray is changed due to the large Δε of the liquid crystal. Is inevitable.

On the other hand, the response speed waveform (time-luminance) curve measured in the liquid crystal display of all modes has a two step waveform showing two steps, as shown in FIG.

Since the response speed is measured when the total brightness changes from 10% to 90%, the response speed is measured slowly when the two-step portion is below 90% brightness.

However, in the OCB mode liquid crystal display, a two-stage waveform occurs in the first frame and maintains a normal luminance in the second or third frame. Therefore, when the capacitance of the holding capacitor is increased so that the brightness of the two-step portion is 90% or more, preferably 95% or more, the response speed can be increased by maintaining the normal brightness in the first frame.

Table 1 measures the luminance value of the 2-step portion on the response speed waveform (time-luminance) curve according to the ratio of the capacitance Cst of the holding capacitance to the capacitance Clc of the liquid crystal in the OCB structured liquid crystal display device. It is shown.

Clc: Cst 1.00: 0.70 1.00: 0.91 2nd position (luminance%) 81.8%  87.3%

It can be seen that when the capacitance of the storage capacitor increases, the position of the two-step is close to 90% of the luminance. Accordingly, the response speed can be increased by increasing the capacitance of the holding capacitance to make the two-step position exceed 90%. In particular, when the capacitance of the holding capacitance is increased so that the position of the two-step becomes 95% or more, a faster response speed can be obtained.

In the present invention, in order to increase the response speed of the liquid crystal display, the capacitance of the holding capacitor is increased to be 90% or more of the capacitance of the liquid crystal. For this purpose, in the first to sixth embodiments of the present invention described above, The holding capacitor is applied to the liquid crystal display of OCB mode. That is, the present invention uses the wirings forming the above-described storage capacitors, but increases its area so that the capacitance of the storage capacitors formed by these wirings is 90% or more of the capacitance of the liquid crystal. At this time, by increasing the capacitance of the storage capacitor via only one insulating film of the protective film or the gate insulating film, there is no need to increase the area of the wiring for the storage capacitor. Thereby, the capacitance of the holding capacitance can be increased without reducing the aperture ratio.

1 is a layout view of a thin film transistor substrate according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along the cutting line II-II ′ shown in FIG. 1.

3A is a layout view of a substrate in a first step for fabricating a thin film transistor substrate according to the first embodiment of the present invention;

3B is a cross-sectional view of the substrate along the cutting line IIIb-IIIb 'shown in FIG. 3A,

4A is a layout view of a substrate in the next manufacturing step of FIG. 3A,

4B is a cross-sectional view of the substrate along the cutting line IVb-IVb ′ shown in FIG. 4A;

FIG. 5A is a layout view of a substrate in a subsequent manufacturing step of FIG. 4A,

FIG. 5B is a cross-sectional view of the substrate along the cutting line Vb-Vb ′ shown in FIG. 5A;

FIG. 6A is a layout view of a substrate in a subsequent manufacturing step of FIG. 5A;

FIG. 6B is a cross-sectional view of the substrate along the cutting line VIb-VIb ′ shown in FIG. 6A;

7 is a layout view of a thin film transistor substrate according to a second exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view of the thin film transistor substrate taken along the cutting line VIII-VIII ′ shown in FIG. 7.

9 is a layout view of a thin film transistor substrate according to a third exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view of the thin film transistor substrate taken along the cutting line VIII-VIII ′ shown in FIG. 9.

11 is a layout view of a thin film transistor substrate according to a fourth exemplary embodiment of the present invention.

12 is a cross-sectional view of the thin film transistor substrate taken along the cutting line?-? 'Shown in FIG.

13A is a layout view of a substrate in a first step for fabricating a thin film transistor substrate according to a fourth embodiment of the present invention;

FIG. 13B is a sectional view of the substrate along the cutting line XIIIb-XIIIb 'shown in FIG. 13A;

FIG. 14A is a layout view of a substrate in a subsequent manufacturing step of FIG. 13A, and FIG.

FIG. 14B is a cross-sectional view of the substrate along the cutting line XIVb-XIVb 'shown in FIG. 14A, and FIG.

FIG. 15A is a layout view of a substrate in a subsequent manufacturing step of FIG. 14A, and FIG.

FIG. 15B is a cross-sectional view of the substrate along the cutting line XVB-VVB 'shown in FIG. 15A, and FIG.

FIG. 16A is a layout view of a substrate in a subsequent manufacturing step of FIG. 15A,

FIG. 16B is a cross-sectional view of the substrate along the cutting line XVIb-XVIb 'shown in FIG. 16A;

FIG. 17A is a layout view of a substrate in a subsequent manufacturing step of FIG. 16A, and FIG.

FIG. 17B is a cross-sectional view of the substrate along the cutting line VIIb-VIIb 'shown in FIG. 17A, and FIG.

18 is a layout view of a thin film transistor substrate according to a fifth exemplary embodiment of the present invention.

FIG. 19 is a cross-sectional view of the thin film transistor substrate taken along the cutting line VIII-VIII ′ shown in FIG. 18.

20 is a layout view of a thin film transistor substrate according to a sixth exemplary embodiment of the present invention.

FIG. 21 is a cross-sectional view of the thin film transistor substrate taken along the cutting line VI-XI ′ of FIG. 20.

22 illustrates a response speed waveform curve in the liquid crystal display.

Claims (4)

Insulation board, A gate wiring formed on the insulating substrate and including a first gate line, a gate electrode connected to the first gate line, and a second gate line disposed at a predetermined distance from the first gate line; A gate insulating film covering the gate wiring, A semiconductor pattern formed on the gate insulating layer to overlap the gate electrode; A storage capacitor formed on the gate insulating film and overlapping a portion of the data line including a data line, a source electrode and a drain electrode intersecting the first and second gate lines, and a portion of the second gate line to form a first storage capacitor; Conductor Pattern, A protective film covering the data line, the storage capacitor conductor pattern, and the semiconductor pattern; First and second contact holes exposing the drain electrode and the storage capacitor conductor pattern to the passivation layer, respectively; A pixel electrode connected to the drain electrode and the storage capacitor conductor pattern on the passivation layer through the first and second contact holes and overlapping a portion of the second gate line to form a second storage capacitor; Thin film transistor substrate comprising a. The thin film transistor substrate according to claim 1, An opposing substrate facing the thin film transistor substrate, Liquid crystal layer interposed between the thin film transistor substrate and the opposite substrate Liquid crystal display comprising a. In claim 2, And a capacitance of the first storage capacitor and the second storage capacitor is greater than 90% of the capacitance of the liquid crystal layer. Forming a gate wiring on the insulating substrate, the gate wiring including a first gate line, a gate electrode connected to the first gate line, and a second gate line disposed to be parallel to the first gate line at a predetermined distance; Forming a gate insulating film covering the gate wiring; Forming a semiconductor pattern on the gate insulating layer, the semiconductor pattern overlapping the gate electrode; A storage capacitor pattern on the gate insulating layer, the data line including a data line crossing the first and second gate lines, a source electrode and a drain electrode, and a first storage capacitor overlapping a portion of the second gate line to form a first storage capacitor. Forming a step, Forming a protective film covering the data line, the storage capacitor conductor pattern, and the semiconductor pattern; Forming first and second contact holes in the passivation layer to expose the drain electrode and the storage capacitor conductor pattern, respectively; A pixel electrode connected to the drain electrode and the storage capacitor conductor pattern through the first and second contact holes on the passivation layer and overlapping a portion of the gate line of the second gate wiring to form a second storage capacitor; Forming steps Method of manufacturing a thin film transistor substrate comprising a.

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