KR20090030504A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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Publication number
KR20090030504A
KR20090030504A KR1020070095861A KR20070095861A KR20090030504A KR 20090030504 A KR20090030504 A KR 20090030504A KR 1020070095861 A KR1020070095861 A KR 1020070095861A KR 20070095861 A KR20070095861 A KR 20070095861A KR 20090030504 A KR20090030504 A KR 20090030504A
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South Korea
Prior art keywords
etching
metal silicide
film
layer
silicide layer
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KR1020070095861A
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Korean (ko)
Inventor
강혜란
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주식회사 하이닉스반도체
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Priority to KR1020070095861A priority Critical patent/KR20090030504A/en
Publication of KR20090030504A publication Critical patent/KR20090030504A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

Abstract

The present invention is to provide a method for manufacturing a semiconductor device for preventing the formation of a bowing profile (micro-loading) to prevent the formation of a bowing profile (micro-loading) during the ultra-fine pattern etching, the present invention is to provide a metal on a substrate Forming a silicide layer, forming a mask pattern having an opening exposing the metal silicide layer on the metal silicide layer, and in-phase bias power and source power of 3.5 to 7.5 times the bias power in a plasma etching apparatus. Provided by a pulse modulation method, and providing a mask pattern dry etching the metal silicide layer using an etching mask.

Description

Manufacturing method of semiconductor device {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

TECHNICAL FIELD This invention relates to a semiconductor technology. Specifically, It is related with the manufacturing method of the semiconductor element for forming the ultra-fine pattern below a limit resolution.

As semiconductor devices become more integrated and higher performance, the semiconductor industry is experiencing rapid growth. In addition, the rapid growth of the semiconductor industry has intensified the demand for higher integration and higher performance of semiconductor devices.

Since the semiconductor device repeats each unit process, such as a deposition process, an ion implantation process, a photographic process, an etching process, and a cleaning process, and implements a desired circuit pattern on the semiconductor substrate and a specific material film, high integration and high performance are achieved. The development of each unit process technology should be supported.

Among them, an etching process, particularly a dry etching process, is an essential process technology for forming an ultrafine circuit pattern having a good etching profile.

Recently, a double patterning scheme has been introduced to form an ultrafine pattern having a size below the limit resolution.

The double patterning scheme forms a multi-layer hard mask on the object to be etched, patternes the hard mask to a pitch below the limit resolution through two photolithography and etching processes, and then etches the etching object using the patterned hard mask as an etch mask. With this technique, it is possible to form ultra-fine patterns below the limit resolution.

However, as the pattern becomes very fine, it is not easy to vertically etch the structure including the metal silicide layer using a dry etching process.

For example, in the gate formation process of a 38nm-class flash memory device using a double patterning scheme, a space is narrowed to 30 nm or less when etching a tungsten silicide layer (WSi x ) used as a control gate after patterning a hard mask. High source power (e.g., bias power of 70-80W and 800-800), which is about 10 to 14 times the bias power when etching tungsten silicide film, as in the case of 60 nm or more devices. Using a source power of 1000 W), high source power produces high density density ions. Plasma ions are patterned in areas where patterns are loose, such as the surrounding area. It is oriented normally in the direction of, so that anisotropic etching is normally performed, but the gap between patterns is narrow like the cell area. In there is a problem in that plasma ions are directed are the isotropic etching (istropic etch) proceeds The tungsten silicide film is the generation Boeing profile (bowing profile) is not perpendicular to the etching that is bent etched arcuate along towards the pattern edges.

In addition, the aspect ratio of the densely patterned region, such as the cell region, is very high due to the thick hard mask used in the double patterning scheme, so that the metal silicide layer of the dense region during dry etching Since the amount of plasma ions reached is reduced compared to the amount of plasma ions reaching the metal silicide film in the coarse region, the micro loading effect in which the pattern density decreases in the etch rate of the dense region compared to the coarse region. ), A problem of inferior etching uniformity occurs between the dense and coarse areas.

1 is a photograph showing a problem of the prior art.

As shown in part A of FIG. 1, in the dense region where the gap between the patterns is narrow during the dry etching of the metal silicide layer, the metal silicide layer is isotropically etched to confirm that the boeing profile is generated.

In addition, since the etching rate of the dense region is lower than that of the coarse region, the etching depth of the tungsten silicide film is different between the coarse region and the dense region, thereby confirming that a uniform pattern is not formed.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and is a method of manufacturing a semiconductor device capable of preventing the formation of a bowing profile of a metal silicide film and eliminating the difference in etch rate between a region having a dense pattern density and a coarse region. The purpose is to provide.

According to an aspect of the present invention, there is provided a method of forming a metal silicide layer on a substrate, forming a mask pattern having an opening exposing the metal silicide layer on the metal silicide layer, and plasma etching. Supplying a bias power and a source power having a magnitude of 3.5 times to 7.5 times the bias power in an in-phase pulse modulation manner in the equipment, and dry etching the metal silicide layer using the mask pattern as an etch mask. It provides a method of manufacturing.

According to the present invention, by lowering the source power when etching the metal silicide layer, the plasma density is lowered, and the source power and the bias power are supplied in an in-phase pulse modulation method so that the anisotropic etching can be effectively performed even in a narrow space, and the pattern of the vertical profile Can be formed.

In addition, by using the in-phase pulse plasma to improve the straightness of the plasma, it is possible to prevent the micro loading effect (improved etching uniformity between the coarse region and the dense region).

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, the same reference numerals throughout the specification represent the same components.

First embodiment

2 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

First, as shown in FIG. 2, the metal silicide layer 101 is formed on the substrate 100, and the first hard mask layers 102, 103, 104 and the second hard layer are formed on the metal silicide layer 101. The mask films 105, 106, and 107, the third hard mask film 108, and the first bottom anti-reflective film (Bottom Anti Reflective Voating) 109 are sequentially formed.

The first hard mask layers 102, 103, and 104 may be formed by stacking a silicon oxynitride layer (SiON) 102, a TEOS layer 103, and an amorphous carbon layer 104. The second hard mask films 105, 106, and 107 may be formed by stacking the first silicon oxynitride film 105, the polysilicon film 106, and the second silicon oxide film 107. The hard mask film 108 may be formed of a polysilicon film.

Subsequently, a photoresist is applied on the first lower antireflection film 109 and the photoresist is patterned by an exposure and development process to form a first photoresist pattern PR1. It is preferable that the pitch P1 of the first photoresist pattern PR1 be twice the size of the desired pitch, and the width W1 be 1/4 the size of the pitch P1.

3, after patterning the first lower anti-reflection film 109 and the third hard mask film 108 using the first photoresist pattern PR1 as a mask, the first photoresist pattern PR1 is patterned. ) And the first lower anti-reflection film 109 are removed.

Subsequently, as shown in FIG. 4, a second lower antireflection film 110 is formed on the second hard mask film 107 including the patterned third hard mask film 108, and the second lower antireflection film ( The second photoresist pattern PR2 is formed by applying the photoresist on 110 and patterning the photoresist so as to remain between the patterned third hard mask layers 108.

Here, the pitch P2 and the width W2 of the second photoresist pattern PR2 may be the same size as the pitch P1 and the width W1 of the first photoresist pattern PR1.

Subsequently, as shown in FIG. 5, the second lower anti-reflection film 110 and the second hard mask films 107 and 106 are masked using the second photoresist pattern PR2 and the patterned third hard mask film 108. , 105).

In the initial etching process, the second lower anti-reflective film 110 is etched using the second photoresist pattern PR2 as an etch mask to expose the patterned third hard mask film 108. Subsequently, etching is performed on the second silicon oxynitride layer 107 by using the second photoresist pattern PR2 as a mask, wherein the third hard mask layer 108 made of polysilicon is etched due to the difference in etching selectivity. Instead, the second silicon oxynitride film 107 is selectively etched. Subsequently, as the second silicon oxynitride layer 107 is etched, etching is performed on the exposed polysilicon layer 106. In this case, the third hard mask layer 108 made of polysilicon also includes the polysilicon layer 106. Etched at the same ratio as, only a part of the third hard mask layer 108 remains. Next, as the polysilicon layer 106 is etched, etching is performed on the exposed first silicon oxynitride layer 105. In this case, the remaining third hard mask layer 108 serves as a barrier to form a third hard mask. The second hard mask films 105, 106, and 107 under the mask film 108 are not attacked.

Thereafter, the remaining second photoresist pattern PR2, the second lower anti-reflection film 110, and the third hard mask film 108 are removed.

As a result, the second hard mask films 105, 106, and 107 are patterned to a pitch corresponding to half of the pitches of the first and second photoresist patterns PR1 and PR2.

Subsequently, as shown in FIG. 6, the first hard mask films 104, 103, 102 are patterned using the patterned second hard mask films 105, 106, and 107 as a mask, and the remaining second hard mask films are patterned. Remove (105, 106, 107).

Subsequently, as shown in FIGS. 7A and 7B, in-phase pulse modulation is performed on a bias power and a source power having a magnitude of 3.5 to 7.5 times the bias power in the plasma etching equipment. The metal silicide layer 101 is dry etched so that the substrate 100 is exposed using the patterned first hard mask layers 104, 103, and 102 as an etching mask.

At this time, the bias power can be used in the range of 70 to 80W, the source power can be used in the range of 245 to 600W lower than the conventional.

As such, when the low source power is used, the plasma density is lowered, so that the isotropic etching characteristic is reduced in the dense region (see FIG. 7A) where the spacing between patterns is narrow, such as the cell region. Formation is prevented.

The in-phase pulse modulation method is a method of forming a plasma in which the bias power is on when the source power is on and the bias power is off when the source power is off. When the source power and the bias power are simultaneously turned on and off at a suitable period, the electron density charged on the substrate 100 is relatively decreased, so that the ion direction is directed toward the pattern edge, thereby reducing isotropic etching and anisotropic etching. This week is fulfilled.

In addition, when the source power is on, the bias power is also turned on so that the straightness of the plasma ions is improved, thereby reducing the micro loading effect, thereby densifying the region (see FIG. 7A). ) And the coarse region (see (b) of FIG. 7) to secure the etching uniformity.

As the plasma is not formed continuously but periodically formed using the in-phase pulse modulation method, plasma etching is performed periodically and stopped for the remaining periods, thereby reducing plasma damage.

Subsequently, an over etch process is performed for a predetermined time for complete etching of the metal silicide layer 101.

Second embodiment

8 to 14 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

First, as shown in FIG. 8, the tunneling insulating film 201, the floating film conductive film 202, the dielectric film 203, the control gate polysilicon film 204, and the metal silicide film are formed on the substrate 100. 101 is formed sequentially.

The tunneling insulating film 201 preferably includes at least one of an oxynitride film and a silicon oxide film. The dielectric film 203 preferably has an oxide oxide (ONO) structure in which the first oxide film, the nitride film, and the second oxide film are sequentially stacked. However, the dielectric film 203 may be formed using only an oxide film or a material having a high dielectric constant.

The floating gate conductive layer 202 may be formed by depositing a polysilicon layer and then performing a POCl 3 deposition process or an ion implantation process to reduce resistance. The metal silicide film 101 may be formed of a tungsten silicide film.

Subsequently, the first hard mask films 102, 103, 104, the second hard mask films 105, 106, and 107, the third hard mask film 108, and the first lower antireflection film on the metal silicide film 101 are formed. (Bottom Anti Reflective Voating, 109) is formed sequentially.

The first hard mask layers 102, 103, and 104 may be formed by stacking a silicon oxynitride layer (SiON) 102, a TEOS layer 103, and an amorphous carbon layer 104.

The second hard mask films 105, 106, and 107 may be formed by stacking the first silicon oxynitride film 105, the polysilicon film 106, and the second silicon oxide film 107. The hard mask film 108 may be formed of a polysilicon film.

Subsequently, a photoresist is applied on the first lower antireflection film 109 and the photoresist is patterned by an exposure and development process to form a first photoresist pattern PR1. It is preferable that the pitch P1 of the first photoresist pattern PR1 be twice the size of the desired pitch, and the width W1 be 1/4 the size of the pitch P1.

Subsequently, as shown in FIG. 9, after patterning the first lower anti-reflection film 109 and the third hard mask film 108 using the first photoresist pattern PR1 as a mask, the first photoresist pattern PR1 is patterned. ) And the first lower anti-reflection film 109 are removed.

Subsequently, as shown in FIG. 10, a second lower antireflection film 110 is formed on the second hard mask film 107 including the patterned third hard mask film 108, and the second lower antireflection film is formed. A photoresist is applied on the 110 and the photoresist is patterned to remain between the patterned third hard mask films 108 to form a second photoresist pattern PR2.

Here, the pitch P2 and the width W2 of the second photoresist pattern PR2 may be the same size as the pitch P1 and the width W1 of the first photoresist pattern PR1.

Subsequently, as shown in FIG. 11, the second lower anti-reflection film 110 and the second hard mask films 105 and 106 are masked using the second photoresist pattern PR2 and the patterned third hard mask film 108. 107).

In the initial etching process, the second lower anti-reflective film 110 is etched using the second photoresist pattern PR2 as an etch mask to expose the patterned third hard mask film 108. Subsequently, etching is performed on the second silicon oxynitride layer 107 using the second photoresist pattern PR2 as a mask. At this time, due to the difference in etching selectivity, the third hard mask layer 108 made of polysilicon is almost formed. Only the second silicon oxynitride film 107 is selectively etched without being etched. Subsequently, as the second silicon oxynitride layer 107 is etched, etching is performed on the exposed polysilicon layer 106. In this case, the third hard mask layer 108 made of polysilicon also includes the polysilicon layer 106. Etched at the same ratio as, only a part of the third hard mask layer 108 remains. Next, as the polysilicon layer 106 is etched, etching is performed on the exposed first silicon oxynitride layer 105. In this case, the remaining third hard mask layer 108 serves as a barrier to form a third layer. The second hard mask films 105, 106, and 107 under the hard mask film 108 are not attacked.

Thereafter, the remaining second photoresist pattern PR2, the second lower anti-reflection film 110, and the third hard mask film 108 are removed.

As a result, the second hard mask films 105, 106, and 107 are patterned to have a pitch corresponding to half of the pitches of the first and second photoresist patterns PR1 and PR2.

Subsequently, as shown in FIG. 12, the first hard mask films 104, 103, 102 are patterned using the patterned second hard mask films 105, 106, and 107 as a mask, and the remaining second hard mask films are patterned. Remove (105, 106, 107).

Subsequently, as shown in FIGS. 13A and 13B, in-phase pulse modulation is performed on a bias power and a source power having a magnitude of 3.5 times to 7.5 times the bias power in the plasma etching equipment. The metal silicide layer 101 is dry etched so that the substrate 100 is exposed using the patterned first hard mask layers 104, 103, and 102 as an etching mask.

At this time, for example, the bias power may be used in the range of 70 to 80W, and the source power may be used in the range of 245 to 600W, which is lower than the conventional one.

As such, when the low source power is used, the plasma density is lowered, so that the isotropic etching is reduced in a dense region having a narrow interval between patterns such as a cell region, thereby preventing the formation of a boeing profile (Fig. 13). (a)).

The in-phase pulse modulation method is a method of forming a plasma in which the bias power is on when the source power is on and the bias power is off when the source power is off. In addition, when the source power and the bias power are simultaneously turned on / off at an appropriate period, the electron density occupied by the substrate is relatively decreased, thereby reducing the direction of the ion toward the pattern edge, thereby reducing isotropic etching and anisotropic etching.

In addition, when the source power is on, the bias power is also turned on so that the straightness of the plasma ions is improved, thereby reducing the micro loading effect, thereby densifying the region (see FIG. 7A). ) And the coarse region (see (b) of FIG. 7) ensures the etching uniformity.

As the in-phase pulse modulation method is used, plasma is not formed continuously but is periodically formed. Accordingly, plasma etching is performed periodically and stopped for the remaining period, thereby reducing plasma damage.

Thereafter, an over etching process is performed to completely etch the metal silicide layer 101. In the over-etching process, a condition in which the selectivity to the polysilicon film is minimized so as to minimize the etching of the lower control silicon polysilicon film 204, for example, in an oxygen gas atmosphere having a high flow rate of about 30 to 60 sccm. Do it.

Subsequently, as shown in FIG. 14, the gate is formed by etching the control gate conductive film 204, the dielectric film 203, and the floating gate conductive film 202 exposed by removing the metal silicide film 101. do.

The etching process may be performed in-situ in the same etching equipment, that is, in a process chamber of an etching apparatus capable of multi-purpose etching, or may use individual etching equipment according to the type of material film to be etched. It may also be carried out.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a photograph showing the problems of the prior art.

2 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a first embodiment of the present invention.

8 to 14 are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

100: substrate

101: metal silicide film

102, 103, and 104: first hard mask film

105, 106, 107: second hard mask film

108: third hard mask film

109, 110: first and second lower antireflection film

PR1, PR2: first and second photoresist patterns

Claims (5)

Forming a metal silicide film on the substrate; Forming a mask pattern on the metal silicide layer, the mask pattern having an opening exposing the metal silicide layer; Supplying a bias power and a source power having a magnitude of 3.5 times to 7.5 times the bias power in an in-phase pulse modulation method in a plasma etching apparatus, and dry etching the metal silicide layer using the mask pattern as an etching mask. Method of manufacturing a semiconductor device. Sequentially forming a tunneling insulating film, a floating gate conductive film, a dielectric film, a control gate polysilicon film, and a metal silicide film on the substrate; Forming a mask pattern on the metal silicide layer, the mask pattern having an opening exposing the metal silicide layer; Supplying a bias power and a source power having a magnitude of 3.5 times to 7.5 times the bias power in an in-phase pulse modulation method in a plasma etching apparatus, and dry etching the metal silicide layer using the mask pattern as an etching mask; And forming a gate by patterning the polysilicon layer for the control gate, the dielectric layer, and the conductive layer for the floating gate exposed as the metal silicide layer is etched. The method according to claim 1 or 2, The bias power is used in the range of 70 to 80W, and the source power is used in the range of 245 to 6000W. The method of claim 2, Etching the metal silicide layer, A main etching step of etching the metal silicide layer until the control gate polysilicon layer is exposed; An additional etching step after the control gate polysilicon layer is exposed Method of manufacturing a semiconductor device comprising a. The method of claim 4, wherein The method of manufacturing a semiconductor device using an oxygen gas having a flow rate of 30 to 60sccm in the over etching step.
KR1020070095861A 2007-09-20 2007-09-20 Method for fabricating semiconductor device KR20090030504A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110177669A1 (en) * 2010-01-15 2011-07-21 Applied Materials, Inc. Method of controlling trench microloading using plasma pulsing

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110177669A1 (en) * 2010-01-15 2011-07-21 Applied Materials, Inc. Method of controlling trench microloading using plasma pulsing
US8658541B2 (en) * 2010-01-15 2014-02-25 Applied Materials, Inc. Method of controlling trench microloading using plasma pulsing

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